[coreboot-gerrit] Change in coreboot[master]: intel/i440bx: Implement EARLY_CBMEM_INIT
Keith Hui (Code Review)
gerrit at coreboot.org
Sun Sep 3 00:55:54 CEST 2017
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21350
Change subject: intel/i440bx: Implement EARLY_CBMEM_INIT
......................................................................
intel/i440bx: Implement EARLY_CBMEM_INIT
Implement cbmem_top() and postcar frame required for cbmem support in
romstage. Boot tested on asus/p2b-ls. Boards to move to this setup in
followup patches.
The change is guarded by LATE_CBMEM_INIT as appropriate to avoid
breaking boards not yet thus migrated, until they get dropped past 4.7.
Brought to you by https://review.coreboot.org/c/20977/.
Change-Id: Ie70372ccb32b0a96a8e0054b8ecadd2ea30d6221
Signed-off-by: Keith Hui <buurin at gmail.com>
---
M src/northbridge/intel/i440bx/Makefile.inc
M src/northbridge/intel/i440bx/northbridge.c
A src/northbridge/intel/i440bx/ram_calc.c
3 files changed, 105 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21350/1
diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc
index 2e00926..50aeece 100644
--- a/src/northbridge/intel/i440bx/Makefile.inc
+++ b/src/northbridge/intel/i440bx/Makefile.inc
@@ -17,8 +17,10 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y)
ramstage-y += northbridge.c
+ramstage-$(CONFIG_EARLY_CBMEM_INIT) += ram_calc.c
romstage-y += raminit.c
romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c
+romstage-$(CONFIG_EARLY_CBMEM_INIT) += ram_calc.c
endif
diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c
index dba7880..e2f0c2a 100644
--- a/src/northbridge/intel/i440bx/northbridge.c
+++ b/src/northbridge/intel/i440bx/northbridge.c
@@ -67,7 +67,9 @@
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
+#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
set_late_cbmem_top(tomk * 1024);
+#endif
}
assign_resources(dev->link_list);
}
diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c
new file mode 100644
index 0000000..30687c6
--- /dev/null
+++ b/src/northbridge/intel/i440bx/ram_calc.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Keith Hui <buurin at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <cpu/intel/romstage.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <commonlib/helpers.h>
+#include "i440bx.h"
+
+void *cbmem_top(void)
+{
+ /* Base of TSEG is top of usable DRAM */
+ /*
+ * SMRAM - System Management RAM Control Register
+ * 0x72
+ * [7:4] Not relevant to this function.
+ * [3:3] Global SMRAM Enable (G_SMRAME)
+ * [2:0] Hardwired to 010.
+
+ * ESMRAMC - Extended System Management RAM Control
+ * 0x73
+ * [7:7] H_SMRAM_EN
+ * 1 = When G_SMRAME=1, High SMRAM space is enabled at
+ * 0x100A0000-0x100FFFFF and forwarded to DRAM address
+ * 0x000A0000-0x000FFFFF.
+ * 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at
+ * 0x000A0000-0x000BFFFF.
+ * [6:3] Not relevant to this function.
+ * [2:1] TSEG Size (T_SZ)
+ * Selects the size of the TSEG memory block, if enabled.
+ * 00 = 128KiB
+ * 01 = 256KiB
+ * 10 = 512KiB
+ * 11 = 1MiB
+ * [0:0] TSEG_EN
+ * When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to
+ * appear between DRAM address (TOM-<TSEG Size>) to TOM.
+
+ * Source: 440BX datasheet, pages 3-28 thru 3-29.
+ */
+ unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB;
+
+ printk(BIOS_DEBUG, "cbmem DRB7 = %08lx\n", tom);
+
+ int tseg = pci_read_config8(NB, ESMRAMC) & 0x7; // H_SMRAM_EN and T_SZ
+ int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; // G_SMRAME
+ if ((tseg & 0x1) && gsmrame) {
+ int tseg_size = 128 * KiB * (1 << (tseg >> 1));
+ tom -= tseg_size;
+ }
+ printk(BIOS_DEBUG, "cbmem tom = %08lx\n", tom);
+ return (void *)tom;
+}
+
+#define ROMSTAGE_RAM_STACK_SIZE 0x5000
+
+/* setup_stack_and_mtrrs() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use.
+ */
+void *setup_stack_and_mtrrs(void)
+{
+ struct postcar_frame pcf;
+ uintptr_t top_of_ram;
+
+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) {
+ printk(BIOS_ERR, "Unable to initialize postcar frame. Attempting to proceed using low memory.\n");
+ postcar_frame_init_lowmem(&pcf);
+ }
+
+ /* Cache the ROM as WP just below 4GiB. */
+ postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,
+ MTRR_TYPE_WRPROT);
+
+ top_of_ram = (uintptr_t)cbmem_top();
+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+ postcar_frame_add_mtrr(&pcf, 0, top_of_ram, MTRR_TYPE_WRBACK);
+
+ /* If TSEG is enabled, add the MTRR for that region here. */
+
+ /* Save the number of MTRRs to setup. Return the stack location
+ * pointing to the number of MTRRs.
+ */
+ return postcar_commit_mtrrs(&pcf);
+
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie70372ccb32b0a96a8e0054b8ecadd2ea30d6221
Gerrit-Change-Number: 21350
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin at gmail.com>
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