<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21350">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/i440bx: Implement EARLY_CBMEM_INIT<br><br>Implement cbmem_top() and postcar frame required for cbmem support in<br>romstage. Boot tested on asus/p2b-ls. Boards to move to this setup in<br>followup patches.<br><br>The change is guarded by LATE_CBMEM_INIT as appropriate to avoid<br>breaking boards not yet thus migrated, until they get dropped past 4.7.<br><br>Brought to you by https://review.coreboot.org/c/20977/.<br><br>Change-Id: Ie70372ccb32b0a96a8e0054b8ecadd2ea30d6221<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>M src/northbridge/intel/i440bx/Makefile.inc<br>M src/northbridge/intel/i440bx/northbridge.c<br>A src/northbridge/intel/i440bx/ram_calc.c<br>3 files changed, 105 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21350/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc<br>index 2e00926..50aeece 100644<br>--- a/src/northbridge/intel/i440bx/Makefile.inc<br>+++ b/src/northbridge/intel/i440bx/Makefile.inc<br>@@ -17,8 +17,10 @@<br> ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BX),y)<br> <br> ramstage-y += northbridge.c<br>+ramstage-$(CONFIG_EARLY_CBMEM_INIT) += ram_calc.c<br> <br> romstage-y += raminit.c<br> romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c<br>+romstage-$(CONFIG_EARLY_CBMEM_INIT) += ram_calc.c<br> <br> endif<br>diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c<br>index dba7880..e2f0c2a 100644<br>--- a/src/northbridge/intel/i440bx/northbridge.c<br>+++ b/src/northbridge/intel/i440bx/northbridge.c<br>@@ -67,7 +67,9 @@<br> ram_resource(dev, idx++, 0, 640);<br> ram_resource(dev, idx++, 768, tolmk - 768);<br> <br>+#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)<br> set_late_cbmem_top(tomk * 1024);<br>+#endif<br> }<br> assign_resources(dev->link_list);<br> }<br>diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c<br>new file mode 100644<br>index 0000000..30687c6<br>--- /dev/null<br>+++ b/src/northbridge/intel/i440bx/ram_calc.c<br>@@ -0,0 +1,101 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Keith Hui <buurin@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#define __SIMPLE_DEVICE__<br>+<br>+#include <arch/io.h><br>+#include <cbmem.h><br>+#include <cpu/intel/romstage.h><br>+#include <console/console.h><br>+#include <cpu/x86/mtrr.h><br>+#include <commonlib/helpers.h><br>+#include "i440bx.h"<br>+<br>+void *cbmem_top(void)<br>+{<br>+ /* Base of TSEG is top of usable DRAM */<br>+ /*<br>+ * SMRAM - System Management RAM Control Register<br>+ * 0x72<br>+ * [7:4] Not relevant to this function.<br>+ * [3:3] Global SMRAM Enable (G_SMRAME)<br>+ * [2:0] Hardwired to 010.<br>+<br>+ * ESMRAMC - Extended System Management RAM Control<br>+ * 0x73<br>+ * [7:7] H_SMRAM_EN<br>+ * 1 = When G_SMRAME=1, High SMRAM space is enabled at<br>+ * 0x100A0000-0x100FFFFF and forwarded to DRAM address<br>+ * 0x000A0000-0x000FFFFF.<br>+ * 0 = When G_SMRAME=1, Compatible SMRAM space is enabled at<br>+ * 0x000A0000-0x000BFFFF.<br>+ * [6:3] Not relevant to this function.<br>+ * [2:1] TSEG Size (T_SZ)<br>+ * Selects the size of the TSEG memory block, if enabled.<br>+ * 00 = 128KiB<br>+ * 01 = 256KiB<br>+ * 10 = 512KiB<br>+ * 11 = 1MiB<br>+ * [0:0] TSEG_EN<br>+ * When SMRAM[G_SMRAME] and this bit are 1, TSEG is enabled to<br>+ * appear between DRAM address (TOM-<TSEG Size>) to TOM.<br>+<br>+ * Source: 440BX datasheet, pages 3-28 thru 3-29.<br>+ */<br>+ unsigned long tom = pci_read_config8(NB, DRB7) * 8 * MiB;<br>+<br>+ printk(BIOS_DEBUG, "cbmem DRB7 = %08lx\n", tom);<br>+<br>+ int tseg = pci_read_config8(NB, ESMRAMC) & 0x7; // H_SMRAM_EN and T_SZ<br>+ int gsmrame = pci_read_config8(NB, SMRAM) & 0x8; // G_SMRAME<br>+ if ((tseg & 0x1) && gsmrame) {<br>+ int tseg_size = 128 * KiB * (1 << (tseg >> 1));<br>+ tom -= tseg_size;<br>+ }<br>+ printk(BIOS_DEBUG, "cbmem tom = %08lx\n", tom);<br>+ return (void *)tom;<br>+}<br>+<br>+#define ROMSTAGE_RAM_STACK_SIZE 0x5000<br>+<br>+/* setup_stack_and_mtrrs() determines the stack to use after<br>+ * cache-as-ram is torn down as well as the MTRR settings to use.<br>+ */<br>+void *setup_stack_and_mtrrs(void)<br>+{<br>+ struct postcar_frame pcf;<br>+ uintptr_t top_of_ram;<br>+<br>+ if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) {<br>+ printk(BIOS_ERR, "Unable to initialize postcar frame. Attempting to proceed using low memory.\n");<br>+ postcar_frame_init_lowmem(&pcf);<br>+ }<br>+<br>+ /* Cache the ROM as WP just below 4GiB. */<br>+ postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE,<br>+ MTRR_TYPE_WRPROT);<br>+<br>+ top_of_ram = (uintptr_t)cbmem_top();<br>+ /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */<br>+ postcar_frame_add_mtrr(&pcf, 0, top_of_ram, MTRR_TYPE_WRBACK);<br>+<br>+ /* If TSEG is enabled, add the MTRR for that region here. */<br>+<br>+ /* Save the number of MTRRs to setup. Return the stack location<br>+ * pointing to the number of MTRRs.<br>+ */<br>+ return postcar_commit_mtrrs(&pcf);<br>+<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21350">change 21350</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie70372ccb32b0a96a8e0054b8ecadd2ea30d6221 </div>
<div style="display:none"> Gerrit-Change-Number: 21350 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>