[coreboot-gerrit] Change in coreboot[master]: superio/winbond/*: Unify w*_set_clksel_48()
Keith Hui (Code Review)
gerrit at coreboot.org
Sat Sep 2 02:10:18 CEST 2017
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/21331
Change subject: superio/winbond/*: Unify w*_set_clksel_48()
......................................................................
superio/winbond/*: Unify w*_set_clksel_48()
This function is identical throughout all Winbond superios in
the tree, so move it into superio/winbond/common/early_init.c,
renamed from early_serial.c because it now does more than just
early serial.
Change all affected mainboards to use the unified function.
Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b
Signed-off-by: Keith Hui <buurin at gmail.com>
---
M src/mainboard/advansus/a785e-i/romstage.c
M src/mainboard/avalue/eax-785e/romstage.c
M src/mainboard/bcom/winnetp680/romstage.c
M src/mainboard/msi/ms6178/romstage.c
M src/mainboard/supermicro/h8dme/romstage.c
M src/mainboard/supermicro/h8dmr/romstage.c
M src/mainboard/supermicro/h8dmr_fam10/romstage.c
M src/mainboard/supermicro/h8qme_fam10/romstage.c
M src/mainboard/tyan/s8226/romstage.c
M src/mainboard/via/epia-m700/romstage.c
M src/mainboard/winent/pl6064/romstage.c
M src/mainboard/winnet/g170/romstage.c
M src/superio/winbond/Makefile.inc
R src/superio/winbond/common/early_init.c
M src/superio/winbond/common/winbond.h
15 files changed, 26 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/21331/1
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index d143724..7714f72 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -100,7 +100,7 @@
enable_rs780_dev8();
sb800_clk_output_48Mhz();
- w83627hf_set_clksel_48(PNP_DEV(0x2e, 0));
+ winbond_set_clksel_48(PNP_DEV(0x2e, 0));
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index d32e7b2..e574ecd 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -100,7 +100,7 @@
enable_rs780_dev8();
sb800_clk_output_48Mhz();
- w83627hf_set_clksel_48(CLK_DEV);
+ winbond_set_clksel_48(CLK_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index 4ba528c..0703ba6 100644
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -78,7 +78,7 @@
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
- w83697hf_set_clksel_48(SERIAL_DEV);
+ winbond_set_clksel_48(SERIAL_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c
index d7cbc32..2f1180e 100644
--- a/src/mainboard/msi/ms6178/romstage.c
+++ b/src/mainboard/msi/ms6178/romstage.c
@@ -33,7 +33,7 @@
void mainboard_romstage_entry(unsigned long bist)
{
- w83627hf_set_clksel_48(DUMMY_DEV);
+ winbond_set_clksel_48(DUMMY_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index cacdd41..9deb940 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -140,7 +140,7 @@
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- w83627hf_set_clksel_48(DUMMY_DEV);
+ winbond_set_clksel_48(DUMMY_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 550bb89..9da1ab5 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -120,7 +120,7 @@
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- w83627hf_set_clksel_48(DUMMY_DEV);
+ winbond_set_clksel_48(DUMMY_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index eb6edff..7ba4f60 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -130,7 +130,7 @@
post_code(0x32);
- w83627hf_set_clksel_48(DUMMY_DEV);
+ winbond_set_clksel_48(DUMMY_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index edede81..3c255c5 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -195,7 +195,7 @@
post_code(0x32);
- w83627hf_set_clksel_48(DUMMY_DEV);
+ winbond_set_clksel_48(DUMMY_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index 220098d..3731e88 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -53,7 +53,7 @@
report_bist_failure(bist);
sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
- w83627dhg_set_clksel_48(DUMMY_DEV);
+ winbond_set_clksel_48(DUMMY_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
sb7xx_51xx_disable_wideio(0);
post_code(0x34);
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index 2f8ecce..faf87c7 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -378,7 +378,7 @@
*/
pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);
/* EmbedComInit(); */
- w83697hf_set_clksel_48(DUMMY_DEV);
+ winbond_set_clksel_48(DUMMY_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
/* enable_vx800_serial(); */
diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c
index 624163b..a8f64cf 100644
--- a/src/mainboard/winent/pl6064/romstage.c
+++ b/src/mainboard/winent/pl6064/romstage.c
@@ -59,7 +59,7 @@
/* Note: must do this AFTER the early_setup! It is counting on some
* early MSR setup for CS5536.
*/
- w83627hf_set_clksel_48(SERIAL_DEV);
+ winbond_set_clksel_48(SERIAL_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/mainboard/winnet/g170/romstage.c b/src/mainboard/winnet/g170/romstage.c
index 9ac02d0..4b549bb 100644
--- a/src/mainboard/winnet/g170/romstage.c
+++ b/src/mainboard/winnet/g170/romstage.c
@@ -79,7 +79,7 @@
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
- w83697hf_set_clksel_48(SERIAL_DEV);
+ winbond_set_clksel_48(SERIAL_DEV);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc
index ae4b283..b0b7b8c 100644
--- a/src/superio/winbond/Makefile.inc
+++ b/src/superio/winbond/Makefile.inc
@@ -14,7 +14,7 @@
##
## include generic winbond pre-ram stage driver
-romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_serial.c
+romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_init.c
subdirs-y += w83627dhg
subdirs-y += w83627ehg
diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_init.c
similarity index 88%
rename from src/superio/winbond/common/early_serial.c
rename to src/superio/winbond/common/early_init.c
index aebbd38..7c3ce2b 100644
--- a/src/superio/winbond/common/early_serial.c
+++ b/src/superio/winbond/common/early_init.c
@@ -15,7 +15,7 @@
*/
/*
- * A generic romstage (pre-ram) driver for Winbond variant Super I/O chips.
+ * A generic romstage (pre-ram) driver for various Winbond Super I/O chips.
*
* The following is derived directly from the vendor Winbond's data-sheets:
*
@@ -79,3 +79,14 @@
pnp_write_config(dev, offset, byte);
pnp_exit_conf_state(dev);
}
+
+void winbond_set_clksel_48(pnp_devfn_t dev)
+{
+ u8 reg8;
+
+ pnp_enter_conf_state(dev);
+ reg8 = pnp_read_config(dev, 0x24);
+ reg8 |= (1 << 6); /* Set the clock input to 48MHz. */
+ pnp_write_config(dev, 0x24, reg8);
+ pnp_exit_conf_state(dev);
+}
diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h
index 6e67eeb..e472018 100644
--- a/src/superio/winbond/common/winbond.h
+++ b/src/superio/winbond/common/winbond.h
@@ -22,6 +22,7 @@
void winbond_enable_serial(pnp_devfn_t dev, uint16_t iobase);
void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state);
+void winbond_set_clksel_48(pnp_devfn_t dev);
void pnp_enter_conf_state(pnp_devfn_t dev);
void pnp_exit_conf_state(pnp_devfn_t dev);
--
To view, visit https://review.coreboot.org/21331
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b
Gerrit-Change-Number: 21331
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin at gmail.com>
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