<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21331">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">superio/winbond/*: Unify w*_set_clksel_48()<br><br>This function is identical throughout all Winbond superios in<br>the tree, so move it into superio/winbond/common/early_init.c,<br>renamed from early_serial.c because it now does more than just<br>early serial.<br><br>Change all affected mainboards to use the unified function.<br><br>Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>M src/mainboard/advansus/a785e-i/romstage.c<br>M src/mainboard/avalue/eax-785e/romstage.c<br>M src/mainboard/bcom/winnetp680/romstage.c<br>M src/mainboard/msi/ms6178/romstage.c<br>M src/mainboard/supermicro/h8dme/romstage.c<br>M src/mainboard/supermicro/h8dmr/romstage.c<br>M src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>M src/mainboard/supermicro/h8qme_fam10/romstage.c<br>M src/mainboard/tyan/s8226/romstage.c<br>M src/mainboard/via/epia-m700/romstage.c<br>M src/mainboard/winent/pl6064/romstage.c<br>M src/mainboard/winnet/g170/romstage.c<br>M src/superio/winbond/Makefile.inc<br>R src/superio/winbond/common/early_init.c<br>M src/superio/winbond/common/winbond.h<br>15 files changed, 26 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/21331/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c<br>index d143724..7714f72 100644<br>--- a/src/mainboard/advansus/a785e-i/romstage.c<br>+++ b/src/mainboard/advansus/a785e-i/romstage.c<br>@@ -100,7 +100,7 @@<br>        enable_rs780_dev8();<br>  sb800_clk_output_48Mhz();<br> <br>- w83627hf_set_clksel_48(PNP_DEV(0x2e, 0));<br>+    winbond_set_clksel_48(PNP_DEV(0x2e, 0));<br>      winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br> <br>      console_init();<br>diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c<br>index d32e7b2..e574ecd 100644<br>--- a/src/mainboard/avalue/eax-785e/romstage.c<br>+++ b/src/mainboard/avalue/eax-785e/romstage.c<br>@@ -100,7 +100,7 @@<br>         enable_rs780_dev8();<br>  sb800_clk_output_48Mhz();<br> <br>- w83627hf_set_clksel_48(CLK_DEV);<br>+     winbond_set_clksel_48(CLK_DEV);<br>       winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br> <br>      console_init();<br>diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c<br>index 4ba528c..0703ba6 100644<br>--- a/src/mainboard/bcom/winnetp680/romstage.c<br>+++ b/src/mainboard/bcom/winnetp680/romstage.c<br>@@ -78,7 +78,7 @@<br>   /* Enable multifunction for northbridge. */<br>   pci_write_config8(ctrl.d0f0, 0x4f, 0x01);<br> <br>- w83697hf_set_clksel_48(SERIAL_DEV);<br>+  winbond_set_clksel_48(SERIAL_DEV);<br>    winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>         console_init();<br> <br>diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c<br>index d7cbc32..2f1180e 100644<br>--- a/src/mainboard/msi/ms6178/romstage.c<br>+++ b/src/mainboard/msi/ms6178/romstage.c<br>@@ -33,7 +33,7 @@<br> <br> void mainboard_romstage_entry(unsigned long bist)<br> {<br>-        w83627hf_set_clksel_48(DUMMY_DEV);<br>+   winbond_set_clksel_48(DUMMY_DEV);<br>     winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br> <br>      console_init();<br>diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c<br>index cacdd41..9deb940 100644<br>--- a/src/mainboard/supermicro/h8dme/romstage.c<br>+++ b/src/mainboard/supermicro/h8dme/romstage.c<br>@@ -140,7 +140,7 @@<br>     if (bist == 0)<br>                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);<br> <br>-      w83627hf_set_clksel_48(DUMMY_DEV);<br>+   winbond_set_clksel_48(DUMMY_DEV);<br>     winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br> <br>      console_init();<br>diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c<br>index 550bb89..9da1ab5 100644<br>--- a/src/mainboard/supermicro/h8dmr/romstage.c<br>+++ b/src/mainboard/supermicro/h8dmr/romstage.c<br>@@ -120,7 +120,7 @@<br>     if (bist == 0)<br>                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);<br> <br>-      w83627hf_set_clksel_48(DUMMY_DEV);<br>+   winbond_set_clksel_48(DUMMY_DEV);<br>     winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br> <br>      console_init();<br>diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>index eb6edff..7ba4f60 100644<br>--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>@@ -130,7 +130,7 @@<br> <br>  post_code(0x32);<br> <br>-  w83627hf_set_clksel_48(DUMMY_DEV);<br>+   winbond_set_clksel_48(DUMMY_DEV);<br>     winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br> <br>      console_init();<br>diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c<br>index edede81..3c255c5 100644<br>--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c<br>+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c<br>@@ -195,7 +195,7 @@<br> <br>  post_code(0x32);<br> <br>-  w83627hf_set_clksel_48(DUMMY_DEV);<br>+   winbond_set_clksel_48(DUMMY_DEV);<br>     winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br> <br>      console_init();<br>diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c<br>index 220098d..3731e88 100644<br>--- a/src/mainboard/tyan/s8226/romstage.c<br>+++ b/src/mainboard/tyan/s8226/romstage.c<br>@@ -53,7 +53,7 @@<br>       report_bist_failure(bist);<br> <br>         sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */<br>-       w83627dhg_set_clksel_48(DUMMY_DEV);<br>+  winbond_set_clksel_48(DUMMY_DEV);<br>     winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>         sb7xx_51xx_disable_wideio(0);<br>         post_code(0x34);<br>diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c<br>index 2f8ecce..faf87c7 100644<br>--- a/src/mainboard/via/epia-m700/romstage.c<br>+++ b/src/mainboard/via/epia-m700/romstage.c<br>@@ -378,7 +378,7 @@<br>         */<br>   pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01);<br>      /* EmbedComInit(); */<br>-        w83697hf_set_clksel_48(DUMMY_DEV);<br>+   winbond_set_clksel_48(DUMMY_DEV);<br>     winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>         /* enable_vx800_serial(); */<br> <br>diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c<br>index 624163b..a8f64cf 100644<br>--- a/src/mainboard/winent/pl6064/romstage.c<br>+++ b/src/mainboard/winent/pl6064/romstage.c<br>@@ -59,7 +59,7 @@<br>   /* Note: must do this AFTER the early_setup! It is counting on some<br>    * early MSR setup for CS5536.<br>         */<br>-  w83627hf_set_clksel_48(SERIAL_DEV);<br>+  winbond_set_clksel_48(SERIAL_DEV);<br>    winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>         console_init();<br> <br>diff --git a/src/mainboard/winnet/g170/romstage.c b/src/mainboard/winnet/g170/romstage.c<br>index 9ac02d0..4b549bb 100644<br>--- a/src/mainboard/winnet/g170/romstage.c<br>+++ b/src/mainboard/winnet/g170/romstage.c<br>@@ -79,7 +79,7 @@<br>        /* Enable multifunction for northbridge. */<br>   pci_write_config8(ctrl.d0f0, 0x4f, 0x01);<br> <br>- w83697hf_set_clksel_48(SERIAL_DEV);<br>+  winbond_set_clksel_48(SERIAL_DEV);<br>    winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>         console_init();<br> <br>diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc<br>index ae4b283..b0b7b8c 100644<br>--- a/src/superio/winbond/Makefile.inc<br>+++ b/src/superio/winbond/Makefile.inc<br>@@ -14,7 +14,7 @@<br> ##<br> <br> ## include generic winbond pre-ram stage driver<br>-romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_serial.c<br>+romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_init.c<br> <br> subdirs-y += w83627dhg<br> subdirs-y += w83627ehg<br>diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_init.c<br>similarity index 88%<br>rename from src/superio/winbond/common/early_serial.c<br>rename to src/superio/winbond/common/early_init.c<br>index aebbd38..7c3ce2b 100644<br>--- a/src/superio/winbond/common/early_serial.c<br>+++ b/src/superio/winbond/common/early_init.c<br>@@ -15,7 +15,7 @@<br>  */<br> <br> /*<br>- * A generic romstage (pre-ram) driver for Winbond variant Super I/O chips.<br>+ * A generic romstage (pre-ram) driver for various Winbond Super I/O chips.<br>  *<br>  * The following is derived directly from the vendor Winbond's data-sheets:<br>  *<br>@@ -79,3 +79,14 @@<br>         pnp_write_config(dev, offset, byte);<br>  pnp_exit_conf_state(dev);<br> }<br>+<br>+void winbond_set_clksel_48(pnp_devfn_t dev)<br>+{<br>+   u8 reg8;<br>+<br>+  pnp_enter_conf_state(dev);<br>+   reg8 = pnp_read_config(dev, 0x24);<br>+   reg8 |= (1 << 6); /* Set the clock input to 48MHz. */<br>+  pnp_write_config(dev, 0x24, reg8);<br>+   pnp_exit_conf_state(dev);<br>+}<br>diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h<br>index 6e67eeb..e472018 100644<br>--- a/src/superio/winbond/common/winbond.h<br>+++ b/src/superio/winbond/common/winbond.h<br>@@ -22,6 +22,7 @@<br> <br> void winbond_enable_serial(pnp_devfn_t dev, uint16_t iobase);<br> void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state);<br>+void winbond_set_clksel_48(pnp_devfn_t dev);<br> <br> void pnp_enter_conf_state(pnp_devfn_t dev);<br> void pnp_exit_conf_state(pnp_devfn_t dev);<br></pre><p>To view, visit <a href="https://review.coreboot.org/21331">change 21331</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21331"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b </div>
<div style="display:none"> Gerrit-Change-Number: 21331 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>