[coreboot-gerrit] Change in coreboot[master]: mainboard/google/coral: Modify TCPU, TSR1 and TSR2
Tim Chen (Code Review)
gerrit at coreboot.org
Fri Sep 1 09:32:36 CEST 2017
Tim Chen has uploaded this change for review. ( https://review.coreboot.org/21314
Change subject: mainboard/google/coral: Modify TCPU, TSR1 and TSR2
......................................................................
mainboard/google/coral: Modify TCPU, TSR1 and TSR2
Copy default baseboard DPTF setting from
baseboard/acpi/dptf.asl to variant/acpi/dptf.asl.
Update the DPTF parameters based on thermal test result.
(ZHY(Uster)_A_DPTF_0901_V1.xlsx)
1. Update DPTF TCPU critical trigger point.
TCPU critical point: 99
TCPU passive point: 90
2. Update DPTF TSR1 passive trigger point.
TSR2 critical point: 90
TSR2 passive point: 48
3. Update DPTF TSR2 passive trigger point.
TSR2 passive point: 62
BUG=b:65269959
BRANCH=master
TEST=build and boot on coral/santa dut
Change-Id: Idbace723e54ca747c3e9874c5fc58e06ace0f65e
Signed-off-by: Tim Chen <Tim-Chen at quantatw.com>
---
M src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl
1 file changed, 70 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/21314/1
diff --git a/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl
index f3ff04b..eb0116c 100644
--- a/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl
@@ -13,4 +13,73 @@
* GNU General Public License for more details.
*/
-#include <baseboard/acpi/dptf.asl>
+#define DPTF_CPU_PASSIVE 90
+#define DPTF_CPU_CRITICAL 99
+#define DPTF_CPU_ACTIVE_AC0 90
+#define DPTF_CPU_ACTIVE_AC1 80
+#define DPTF_CPU_ACTIVE_AC2 70
+#define DPTF_CPU_ACTIVE_AC3 60
+#define DPTF_CPU_ACTIVE_AC4 50
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "Battery"
+#define DPTF_TSR0_PASSIVE 120
+#define DPTF_TSR0_CRITICAL 125
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "Ambient"
+#define DPTF_TSR1_PASSIVE 48
+#define DPTF_TSR1_CRITICAL 90
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "Charger"
+#define DPTF_TSR2_PASSIVE 62
+#define DPTF_TSR2_CRITICAL 90
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 2 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 12000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 8000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
--
To view, visit https://review.coreboot.org/21314
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idbace723e54ca747c3e9874c5fc58e06ace0f65e
Gerrit-Change-Number: 21314
Gerrit-PatchSet: 1
Gerrit-Owner: Tim Chen <Tim-Chen at quantatw.com>
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