<p>Tim Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21314">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/coral: Modify TCPU, TSR1 and TSR2<br><br>Copy default baseboard DPTF setting from<br>baseboard/acpi/dptf.asl to variant/acpi/dptf.asl.<br><br>Update the DPTF parameters based on thermal test result.<br>(ZHY(Uster)_A_DPTF_0901_V1.xlsx)<br><br>1. Update DPTF TCPU critical trigger point.<br> TCPU critical point: 99<br> TCPU passive point: 90<br><br>2. Update DPTF TSR1 passive trigger point.<br> TSR2 critical point: 90<br> TSR2 passive point: 48<br><br>3. Update DPTF TSR2 passive trigger point.<br> TSR2 passive point: 62<br><br>BUG=b:65269959<br>BRANCH=master<br>TEST=build and boot on coral/santa dut<br><br>Change-Id: Idbace723e54ca747c3e9874c5fc58e06ace0f65e<br>Signed-off-by: Tim Chen <Tim-Chen@quantatw.com><br>---<br>M src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl<br>1 file changed, 70 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/21314/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl<br>index f3ff04b..eb0116c 100644<br>--- a/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl<br>+++ b/src/mainboard/google/reef/variants/coral/include/variant/acpi/dptf.asl<br>@@ -13,4 +13,73 @@<br> * GNU General Public License for more details.<br> */<br> <br>-#include <baseboard/acpi/dptf.asl><br>+#define DPTF_CPU_PASSIVE 90<br>+#define DPTF_CPU_CRITICAL 99<br>+#define DPTF_CPU_ACTIVE_AC0 90<br>+#define DPTF_CPU_ACTIVE_AC1 80<br>+#define DPTF_CPU_ACTIVE_AC2 70<br>+#define DPTF_CPU_ACTIVE_AC3 60<br>+#define DPTF_CPU_ACTIVE_AC4 50<br>+<br>+#define DPTF_TSR0_SENSOR_ID 0<br>+#define DPTF_TSR0_SENSOR_NAME "Battery"<br>+#define DPTF_TSR0_PASSIVE 120<br>+#define DPTF_TSR0_CRITICAL 125<br>+<br>+#define DPTF_TSR1_SENSOR_ID 1<br>+#define DPTF_TSR1_SENSOR_NAME "Ambient"<br>+#define DPTF_TSR1_PASSIVE 48<br>+#define DPTF_TSR1_CRITICAL 90<br>+<br>+#define DPTF_TSR2_SENSOR_ID 2<br>+#define DPTF_TSR2_SENSOR_NAME "Charger"<br>+#define DPTF_TSR2_PASSIVE 62<br>+#define DPTF_TSR2_CRITICAL 90<br>+<br>+#define DPTF_ENABLE_CHARGER<br>+<br>+/* Charger performance states, board-specific values from charger and EC */<br>+Name (CHPS, Package () {<br>+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */<br>+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */<br>+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */<br>+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */<br>+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */<br>+})<br>+<br>+Name (DTRT, Package () {<br>+ /* CPU Throttle Effect on CPU */<br>+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 },<br>+<br>+ /* CPU Effect on Temp Sensor 0 */<br>+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },<br>+<br>+#ifdef DPTF_ENABLE_CHARGER<br>+ /* Charger Effect on Temp Sensor 2 */<br>+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 },<br>+#endif<br>+<br>+ /* CPU Effect on Temp Sensor 1 */<br>+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 },<br>+})<br>+<br>+Name (MPPC, Package ()<br>+{<br>+ 0x2, /* Revision */<br>+ Package () { /* Power Limit 1 */<br>+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */<br>+ 3000, /* PowerLimitMinimum */<br>+ 12000, /* PowerLimitMaximum */<br>+ 1000, /* TimeWindowMinimum */<br>+ 1000, /* TimeWindowMaximum */<br>+ 200 /* StepSize */<br>+ },<br>+ Package () { /* Power Limit 2 */<br>+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */<br>+ 8000, /* PowerLimitMinimum */<br>+ 15000, /* PowerLimitMaximum */<br>+ 1000, /* TimeWindowMinimum */<br>+ 1000, /* TimeWindowMaximum */<br>+ 1000 /* StepSize */<br>+ }<br>+})<br></pre><p>To view, visit <a href="https://review.coreboot.org/21314">change 21314</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21314"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idbace723e54ca747c3e9874c5fc58e06ace0f65e </div>
<div style="display:none"> Gerrit-Change-Number: 21314 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tim Chen <Tim-Chen@quantatw.com> </div>