[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Remove amdlib functions from fixme.c
Marshall Dawson (Code Review)
gerrit at coreboot.org
Tue Oct 31 02:15:29 CET 2017
Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22248
Change subject: amd/stoneyridge: Remove amdlib functions from fixme.c
......................................................................
amd/stoneyridge: Remove amdlib functions from fixme.c
Convert functionality to use coreboot-centric functions and defined
values. This change should have not functional effect.
BUG=b:62241048
Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/fixme.c
1 file changed, 50 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/22248/1
diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c
index 214e7bb..541fca3 100644
--- a/src/soc/amd/stoneyridge/fixme.c
+++ b/src/soc/amd/stoneyridge/fixme.c
@@ -13,79 +13,72 @@
* GNU General Public License for more details.
*/
+#include <device/device.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/lapic_def.h>
+#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdfam15.h>
#include <soc/pci_devs.h>
+#include <soc/pci_devs.h>
+#include <soc/northbridge.h>
+#include <soc/southbridge.h>
#include <agesawrapper.h>
-#include <amdlib.h>
+#define ROM_BASE ((uintptr_t)(0x100000000ull - CONFIG_ROM_SIZE))
+
+/*
+ * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,
+ * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining
+ * MMIO to posted. Route all I/O to the southbridge.
+ */
void amd_initcpuio(void)
{
- UINT64 MsrReg;
- UINT32 PciData;
- PCI_ADDR PciAddress;
- AMD_CONFIG_PARAMS StdHeader;
+ msr_t topmem = rdmsr(TOP_MEM); /* todo: build bsp_topmem() earlier */
+ u32 base, limit;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xf4);
- PciData = 1;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
- /* The platform BIOS needs to ensure the memory ranges of SB800
- * legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and
- * ACPI) are set to non-posted regions.
- */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
- /* last address before processor local APIC at FEE00000 */
- PciData = 0x00fedf00;
- PciData |= 1 << 7; /* set NP (non-posted) bit */
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
- /* lowest NP address is HPET at FED00000 */
- PciData = (0xfed00000 >> 8) | 3;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
+ base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
+ limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;
+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
- /* Map the remaining PCI hole as posted MMIO */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8c);
- PciData = 0x00fecf00; /* last address before non-posted range */
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
- MsrReg = (MsrReg >> 8) | 3;
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
- PciData = (UINT32)MsrReg;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
+ base = (topmem.lo >> 8) | MMIO_WE | MMIO_RE;
+ limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO + 8, limit);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO + 8, base);
- /* Send all IO (0000-FFFF) to southbridge. */
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xc4);
- PciData = 0x0000f000;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xc0);
- PciData = 0x00000003;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
+ /* Send all I/O (0000-0xffff) to southbridge */
+ base = 0 | MMIO_WE | MMIO_RE;
+ limit = ALIGN_DOWN(0xffff, 4 * KiB);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_IO_LIMIT0, limit);
+ pci_write_config32(SOC_ADDR_DEV, D18F1_IO_BASE0, base);
}
+/* Set the MMIO Configuration Base Address and Bus Range. */
void amd_initmmio(size_t max_bus)
{
- UINT64 MsrReg;
- AMD_CONFIG_PARAMS StdHeader;
+ msr_t mmconf, base, mask;
+ msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+ int rom_mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;
- /*
- Set the MMIO Configuration Base Address and Bus Range onto MMIO
- configuration base Address MSR register.
- */
- MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
- (LibAmdBitScanReverse(max_bus) << 2)
- | 1;
- LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader);
+ mmconf.hi = 0;
+ mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS
+ | (fms(max_bus) << MMIO_BUS_RANGE_SHIFT)
+ | MMIO_RANGE_EN;
+ wrmsr(MMIO_CONF_BASE, mmconf);
- /* Set ROM cache onto WP to decrease post time */
- MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
- LibAmdMsrWrite(0x20c, &MsrReg, &StdHeader);
- MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
- LibAmdMsrWrite(0x20d, &MsrReg, &StdHeader);
+ /* Set ROM flash to WP to allow cacheability */
+ base.hi = 0;
+ base.lo = ROM_BASE | MTRR_TYPE_WRPROT;
+ wrmsr(MTRR_PHYS_BASE(rom_mtrr), base);
- if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {
- LibAmdMsrRead(0x1b, &MsrReg, &StdHeader);
- MsrReg |= 1 << 11;
- LibAmdMsrWrite(0x1b, &MsrReg, &StdHeader);
- }
+ mask.hi = (1 << (cpu_phys_address_size() - 32)) - 1;
+ mask.lo = (0xffffffff - CACHE_ROM_SIZE + 1) | MTRR_PHYS_MASK_VALID;
+ wrmsr(MTRR_PHYS_MASK(rom_mtrr), mask);
}
--
To view, visit https://review.coreboot.org/22248
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75
Gerrit-Change-Number: 22248
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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