<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22248">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Remove amdlib functions from fixme.c<br><br>Convert functionality to use coreboot-centric functions and defined<br>values. This change should have not functional effect.<br><br>BUG=b:62241048<br><br>Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/fixme.c<br>1 file changed, 50 insertions(+), 57 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/22248/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c<br>index 214e7bb..541fca3 100644<br>--- a/src/soc/amd/stoneyridge/fixme.c<br>+++ b/src/soc/amd/stoneyridge/fixme.c<br>@@ -13,79 +13,72 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include <device/device.h><br>+#include <cpu/cpu.h><br>+#include <cpu/x86/lapic_def.h><br>+#include <cpu/x86/msr.h><br> #include <cpu/x86/mtrr.h><br>+#include <cpu/amd/mtrr.h><br>+#include <cpu/amd/amdfam15.h><br> #include <soc/pci_devs.h><br>+#include <soc/pci_devs.h><br>+#include <soc/northbridge.h><br>+#include <soc/southbridge.h><br> #include <agesawrapper.h><br>-#include <amdlib.h><br> <br>+#define ROM_BASE ((uintptr_t)(0x100000000ull - CONFIG_ROM_SIZE))<br>+<br>+/*<br>+ * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,<br>+ * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining<br>+ * MMIO to posted. Route all I/O to the southbridge.<br>+ */<br> void amd_initcpuio(void)<br> {<br>- UINT64 MsrReg;<br>- UINT32 PciData;<br>- PCI_ADDR PciAddress;<br>- AMD_CONFIG_PARAMS StdHeader;<br>+ msr_t topmem = rdmsr(TOP_MEM); /* todo: build bsp_topmem() earlier */<br>+ u32 base, limit;<br> <br> /* Enable legacy video routing: D18F1xF4 VGA Enable */<br>- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xf4);<br>- PciData = 1;<br>- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);<br> <br>- /* The platform BIOS needs to ensure the memory ranges of SB800<br>- * legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and<br>- * ACPI) are set to non-posted regions.<br>- */<br>- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);<br>- /* last address before processor local APIC at FEE00000 */<br>- PciData = 0x00fedf00;<br>- PciData |= 1 << 7; /* set NP (non-posted) bit */<br>- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);<br>- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);<br>- /* lowest NP address is HPET at FED00000 */<br>- PciData = (0xfed00000 >> 8) | 3;<br>- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);<br>+ /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */<br>+ base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;<br>+ limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);<br> <br>- /* Map the remaining PCI hole as posted MMIO */<br>- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8c);<br>- PciData = 0x00fecf00; /* last address before non-posted range */<br>- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);<br>- LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);<br>- MsrReg = (MsrReg >> 8) | 3;<br>- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);<br>- PciData = (UINT32)MsrReg;<br>- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);<br>+ /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */<br>+ base = (topmem.lo >> 8) | MMIO_WE | MMIO_RE;<br>+ limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO + 8, limit);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO + 8, base);<br> <br>- /* Send all IO (0000-FFFF) to southbridge. */<br>- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xc4);<br>- PciData = 0x0000f000;<br>- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);<br>- PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xc0);<br>- PciData = 0x00000003;<br>- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);<br>+ /* Send all I/O (0000-0xffff) to southbridge */<br>+ base = 0 | MMIO_WE | MMIO_RE;<br>+ limit = ALIGN_DOWN(0xffff, 4 * KiB);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_IO_LIMIT0, limit);<br>+ pci_write_config32(SOC_ADDR_DEV, D18F1_IO_BASE0, base);<br> }<br> <br>+/* Set the MMIO Configuration Base Address and Bus Range. */<br> void amd_initmmio(size_t max_bus)<br> {<br>- UINT64 MsrReg;<br>- AMD_CONFIG_PARAMS StdHeader;<br>+ msr_t mmconf, base, mask;<br>+ msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);<br>+ int rom_mtrr = (mtrr_cap.lo & MTRR_CAP_VCNT) - 2;<br> <br>- /*<br>- Set the MMIO Configuration Base Address and Bus Range onto MMIO<br>- configuration base Address MSR register.<br>- */<br>- MsrReg = CONFIG_MMCONF_BASE_ADDRESS |<br>- (LibAmdBitScanReverse(max_bus) << 2)<br>- | 1;<br>- LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader);<br>+ mmconf.hi = 0;<br>+ mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS<br>+ | (fms(max_bus) << MMIO_BUS_RANGE_SHIFT)<br>+ | MMIO_RANGE_EN;<br>+ wrmsr(MMIO_CONF_BASE, mmconf);<br> <br>- /* Set ROM cache onto WP to decrease post time */<br>- MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;<br>- LibAmdMsrWrite(0x20c, &MsrReg, &StdHeader);<br>- MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;<br>- LibAmdMsrWrite(0x20d, &MsrReg, &StdHeader);<br>+ /* Set ROM flash to WP to allow cacheability */<br>+ base.hi = 0;<br>+ base.lo = ROM_BASE | MTRR_TYPE_WRPROT;<br>+ wrmsr(MTRR_PHYS_BASE(rom_mtrr), base);<br> <br>- if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) {<br>- LibAmdMsrRead(0x1b, &MsrReg, &StdHeader);<br>- MsrReg |= 1 << 11;<br>- LibAmdMsrWrite(0x1b, &MsrReg, &StdHeader);<br>- }<br>+ mask.hi = (1 << (cpu_phys_address_size() - 32)) - 1;<br>+ mask.lo = (0xffffffff - CACHE_ROM_SIZE + 1) | MTRR_PHYS_MASK_VALID;<br>+ wrmsr(MTRR_PHYS_MASK(rom_mtrr), mask);<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/22248">change 22248</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75 </div>
<div style="display:none"> Gerrit-Change-Number: 22248 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>