[coreboot-gerrit] Change in coreboot[master]: soc/amd: Pass number of buses to mmio_init

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22247


Change subject: soc/amd: Pass number of buses to mmio_init
......................................................................

soc/amd: Pass number of buses to mmio_init

This patch lays the groundwork for a subsequent patch that will eliminate
the amdlib functions from fixme.c.

Put the CONFIG value on the stack for amd_initmmio().  Eventually
LibAmdBitScanReverse() will be replaced with fms() which doesn't work
well with absolute values.

Change-Id: If875f46cff4cd8e63271939e122b22688552c4b4
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/common/agesawrapper.h
M src/soc/amd/stoneyridge/bootblock/bootblock.c
M src/soc/amd/stoneyridge/fixme.c
3 files changed, 4 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/22247/1

diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h
index b42f531..a9e6209 100644
--- a/src/soc/amd/common/agesawrapper.h
+++ b/src/soc/amd/common/agesawrapper.h
@@ -51,7 +51,7 @@
 
 VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly);
 VOID amd_initcpuio(void);
-VOID amd_initmmio(void);
+VOID amd_initmmio(size_t max_bus);
 const void *agesawrapper_locate_module(const CHAR8 name[8]);
 
 void OemPostParams(AMD_POST_PARAMS *PostParams);
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c
index 1712b51..7545a59 100644
--- a/src/soc/amd/stoneyridge/bootblock/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c
@@ -39,7 +39,7 @@
 
 void bootblock_soc_early_init(void)
 {
-	amd_initmmio();
+	amd_initmmio(CONFIG_MMCONF_BUS_NUMBER);
 
 	if (!boot_cpu())
 		bootblock_soc_init(); /* APs will not return */
diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c
index 60cc2d1..214e7bb 100644
--- a/src/soc/amd/stoneyridge/fixme.c
+++ b/src/soc/amd/stoneyridge/fixme.c
@@ -63,7 +63,7 @@
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 }
 
-void amd_initmmio(void)
+void amd_initmmio(size_t max_bus)
 {
 	UINT64                        MsrReg;
 	AMD_CONFIG_PARAMS             StdHeader;
@@ -73,7 +73,7 @@
 	  configuration base Address MSR register.
 	*/
 	MsrReg = CONFIG_MMCONF_BASE_ADDRESS |
-			(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2)
+			(LibAmdBitScanReverse(max_bus) << 2)
 			| 1;
 	LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader);
 

-- 
To view, visit https://review.coreboot.org/22247
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If875f46cff4cd8e63271939e122b22688552c4b4
Gerrit-Change-Number: 22247
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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