[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Remove duplicate LPC decode setup

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22246


Change subject: amd/stoneyridge: Remove duplicate LPC decode setup
......................................................................

amd/stoneyridge: Remove duplicate LPC decode setup

Delete the LPC I/O decode configuration from fixme.c.  This code is
superseded by early_setup.c.

Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
---
M src/soc/amd/stoneyridge/fixme.c
1 file changed, 0 insertions(+), 7 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/22246/1

diff --git a/src/soc/amd/stoneyridge/fixme.c b/src/soc/amd/stoneyridge/fixme.c
index d3f5f6c..60cc2d1 100644
--- a/src/soc/amd/stoneyridge/fixme.c
+++ b/src/soc/amd/stoneyridge/fixme.c
@@ -66,8 +66,6 @@
 void amd_initmmio(void)
 {
 	UINT64                        MsrReg;
-	UINT32                        PciData;
-	PCI_ADDR                      PciAddress;
 	AMD_CONFIG_PARAMS             StdHeader;
 
 	/*
@@ -78,11 +76,6 @@
 			(LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2)
 			| 1;
 	LibAmdMsrWrite(0xc0010058, &MsrReg, &StdHeader);
-
-	/* For serial port */
-	PciData = 0xff03ffd5;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, PCU_DEV, LPC_FUNC, 0x44);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Set ROM cache onto WP to decrease post time */
 	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571
Gerrit-Change-Number: 22246
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
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