[coreboot-gerrit] Change in coreboot[master]: md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown

[Roy Mingi Park (Code Review)]

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/22236


Change subject: md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown
......................................................................

md/google/soraka: enable 8254 Static Clock Gating for XTAL shutdown

8254 Static Clock Gating should be enabled for XTAL OSC shutdown
which has a power impact.

BUG=None
BRANCH=None
TEST=Build for kabylake board with the clock_gate_8254 policy in
devicetree set to 1.
iotools mmio_read32 0xfdc43300 should return 0x1f

Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8
Signed-off-by: Roy Mingi Park <roy.mingi.park at intel.com>
---
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/soc/intel/skylake/chip.c
2 files changed, 8 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/22236/1

diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 1c342a4..40f0f0f 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -60,6 +60,7 @@
 	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
 	register "PmTimerDisabled" = "1"
+	register "clock_gate_8254" = "1"               # CGE for 8254 PIT
 
 	register "pirqa_routing" = "PCH_IRQ11"
 	register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index dfa813a..7247b4a 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -204,6 +204,10 @@
 	params->SendVrMbxCmd = config->SendVrMbxCmd;
 
 	soc_irq_settings(params);
+
+    /* Enable CGE for 8254 PIT due to xtal requirement */
+	params->Early8254ClockGatingEnable = config->clock_gate_8254;
+
 }
 
 void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
@@ -808,6 +812,9 @@
 	fsp_display_upd_value("SendVrMbxCmd", 1,
 		original->SendVrMbxCmd,
 		params->SendVrMbxCmd);
+	fsp_display_upd_value("Early8254ClockGatingEnable", 1,
+		original->Early8254ClockGatingEnable,
+		params->Early8254ClockGatingEnable);
 }
 
 static void pci_set_subsystem(device_t dev, unsigned int vendor,

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I87fb6fa86f10be6e3c888dd3590d0e77a2b886e8
Gerrit-Change-Number: 22236
Gerrit-PatchSet: 1
Gerrit-Owner: Roy Mingi Park <roy.mingi.park at intel.com>
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