[coreboot-gerrit] Change in coreboot[master]: inteltool: Add southbridge and CPU definitions for skylake

[Maximilian Schander (Code Review)]

Maximilian Schander has uploaded this change for review. ( https://review.coreboot.org/22211


Change subject: inteltool: Add southbridge and CPU definitions for skylake
......................................................................

inteltool: Add southbridge and CPU definitions for skylake

Southbridge definitions were partially taken from devices and
driver updates. CPU definition from Acer notebook.

Change-Id: Id9501f11a79cb314bc407760b22006a3375e669d
Signed-off-by: Maximilian Schander <maxschander at googlemail.com>
---
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
2 files changed, 33 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/22211/1

diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index f873590..7283b65 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -111,6 +111,8 @@
 	  "4th generation (Haswell family) Core Processor ULT" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U,
 	  "5th generation (Broadwell family) Core Processor ULT" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M,
+	  "6th generation (Skylake family) Core Processor (Mobile)" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, "6th generation (Skylake-S/H family) Core Processor (Workstation)" },
 	/* Southbridges (LPC controllers) */
@@ -200,6 +202,26 @@
 	  "Wildcat Point Low Power SKU" },
 	{ PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_B150,
+	  "Sunrise Point (B150)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_H110,
+	  "Sunrise Point (H110)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_H170,
+	  "Sunrise Point (H170)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_HM170,
+	  "Sunrise Point (HM170)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_HM175,
+	  "Sunrise Point (HM175)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Q150,
+	  "Sunrise Point (Q150)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Q170,
+	  "Sunrise Point (Q170)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_QM170,
+	  "Sunrise Point (QM170)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_QM175,
+	  "Sunrise Point (QM175)" },
+	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Z170,
+	  "Sunrise Point (Z170)" },
 	{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM236, "CM236" },
 };
 
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index d4aa96f..4f3950d 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -139,6 +139,16 @@
 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM	0x9cc3
 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP	0x9cc5
 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA	0xa102
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_B150    0xa148
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_H110    0xa143
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_H170    0xa144
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_HM170   0xa14e
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_HM175   0xa152
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Q150    0xa147
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Q170    0xa146
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_QM170   0xa14d
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_QM175   0xa153
+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Z170    0xa145
 #define PCI_DEVICE_ID_INTEL_CM236		0xa150
 #define PCI_DEVICE_ID_INTEL_82810		0x7120
 #define PCI_DEVICE_ID_INTEL_82810_DC	0x7122
@@ -208,6 +218,7 @@
 #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3	0x0c08 /* Haswell (Xeon E3 v3) */
 #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U	0x0a04 /* Haswell-ULT */
 #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U	0x1604 /* Broadwell-ULT */
+#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M  0x1910 /* Skylake (Mobile) */
 #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST	0x1918
 
 #if !defined(__DARWIN__) && !defined(__FreeBSD__)

-- 
To view, visit https://review.coreboot.org/22211
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id9501f11a79cb314bc407760b22006a3375e669d
Gerrit-Change-Number: 22211
Gerrit-PatchSet: 1
Gerrit-Owner: Maximilian Schander <maxschander at googlemail.com>
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