<p>Maximilian Schander has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22211">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">inteltool: Add southbridge and CPU definitions for skylake<br><br>Southbridge definitions were partially taken from devices and<br>driver updates. CPU definition from Acer notebook.<br><br>Change-Id: Id9501f11a79cb314bc407760b22006a3375e669d<br>Signed-off-by: Maximilian Schander <maxschander@googlemail.com><br>---<br>M util/inteltool/inteltool.c<br>M util/inteltool/inteltool.h<br>2 files changed, 33 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/22211/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c<br>index f873590..7283b65 100644<br>--- a/util/inteltool/inteltool.c<br>+++ b/util/inteltool/inteltool.c<br>@@ -111,6 +111,8 @@<br> "4th generation (Haswell family) Core Processor ULT" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U,<br> "5th generation (Broadwell family) Core Processor ULT" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M,<br>+ "6th generation (Skylake family) Core Processor (Mobile)" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST, "6th generation (Skylake-S/H family) Core Processor (Workstation)" },<br> /* Southbridges (LPC controllers) */<br>@@ -200,6 +202,26 @@<br> "Wildcat Point Low Power SKU" },<br> { PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_B150,<br>+ "Sunrise Point (B150)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_H110,<br>+ "Sunrise Point (H110)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_H170,<br>+ "Sunrise Point (H170)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_HM170,<br>+ "Sunrise Point (HM170)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_HM175,<br>+ "Sunrise Point (HM175)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Q150,<br>+ "Sunrise Point (Q150)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Q170,<br>+ "Sunrise Point (Q170)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_QM170,<br>+ "Sunrise Point (QM170)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_QM175,<br>+ "Sunrise Point (QM175)" },<br>+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Z170,<br>+ "Sunrise Point (Z170)" },<br> { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM236, "CM236" },<br> };<br> <br>diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h<br>index d4aa96f..4f3950d 100644<br>--- a/util/inteltool/inteltool.h<br>+++ b/util/inteltool/inteltool.h<br>@@ -139,6 +139,16 @@<br> #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3<br> #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5<br> #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102<br>+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_B150 0xa148<br>+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_H110 0xa143<br>+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_H170 0xa144<br>+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_HM170 0xa14e<br>+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_HM175 0xa152<br>+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Q150 0xa147<br>+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Q170 0xa146<br>+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_QM170 0xa14d<br>+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_QM175 0xa153<br>+#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LPC_Z170 0xa145<br> #define PCI_DEVICE_ID_INTEL_CM236 0xa150<br> #define PCI_DEVICE_ID_INTEL_82810 0x7120<br> #define PCI_DEVICE_ID_INTEL_82810_DC 0x7122<br>@@ -208,6 +218,7 @@<br> #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3 0x0c08 /* Haswell (Xeon E3 v3) */<br> #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U 0x0a04 /* Haswell-ULT */<br> #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U 0x1604 /* Broadwell-ULT */<br>+#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */<br> #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918<br> <br> #if !defined(__DARWIN__) && !defined(__FreeBSD__)<br></pre><p>To view, visit <a href="https://review.coreboot.org/22211">change 22211</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22211"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id9501f11a79cb314bc407760b22006a3375e669d </div>
<div style="display:none"> Gerrit-Change-Number: 22211 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maximilian Schander <maxschander@googlemail.com> </div>