[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: provide common LPDDR4 memory init

[Nick Vaccaro (Code Review)]

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/22204


Change subject: soc/intel/cannonlake: provide common LPDDR4 memory init
......................................................................

soc/intel/cannonlake: provide common LPDDR4 memory init

Instead of having the mainboards duplicate logic surrounding
LPDDR4 initialization provide helpers to do the heavy lifting.
It also handles the quirks of the FSP configuration which allows
the mainboard porting to focus on the schematic/design.

BUG=b:64395641
BRANCH=None
TEST=None

Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834
Signed-off-by: Nick Vaccaro <nvaccaro at google.com>
---
M src/soc/intel/cannonlake/Makefile.inc
A src/soc/intel/cannonlake/include/soc/meminit.h
A src/soc/intel/cannonlake/meminit.c
3 files changed, 150 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/22204/1

diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 8dfff91..bd00b13 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -21,6 +21,7 @@
 
 romstage-y += gpio.c
 romstage-y += gspi.c
+romstage-y += meminit.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
 romstage-y += reset.c
diff --git a/src/soc/intel/cannonlake/include/soc/meminit.h b/src/soc/intel/cannonlake/include/soc/meminit.h
new file mode 100644
index 0000000..6c74703
--- /dev/null
+++ b/src/soc/intel/cannonlake/include/soc/meminit.h
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_CANNONLAKE_MEMINIT_H_
+#define _SOC_CANNONLAKE_MEMINIT_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <fsp/soc_binding.h>
+
+
+/* Number of dq bits controlled per dqs */
+#define DQ_BITS_PER_DQS 8
+
+/* Channel identification. */
+enum {
+	LP4_CH0 = 0,
+	LP4_CH1,
+	LP4_NUM_CHANNELS
+};
+
+/* Cannon Lake PCH family skus */
+typedef enum {
+	CANNONLAKE_U,
+	CANNONLAKE_Y
+} cannonlake_type;
+
+/* Board-specific lpddr4 dq mapping information */
+struct lpddr4_cfg {
+	/* DQ byte map Ch0 and Ch1 */
+	const u8 dq_map[LP4_NUM_CHANNELS][12];
+
+	/* DQS CPU<>DRAM map Ch0 and Ch1 */
+	const u8 dqs_map[LP4_NUM_CHANNELS][DQ_BITS_PER_DQS];
+
+	/* Rcomp resistor */
+	const u16 rcomp_resistor[3];
+};
+
+/*
+ * The cnl_lpddr4_cfg struct contains the board-specific info
+ * needed to inialize a Cannon Lake based board to use lpddr4 memory
+ * Only additional information needed is the spd index to use, which
+ * will get passed into meminit_lpddr4() as an input parameter.
+ */
+struct cnl_lpddr4_cfg {
+
+	/* Cannonlake PCH Type */
+	const cannonlake_type cnl_type;
+
+	/* Board-specific lpddr4 info */
+	const struct lpddr4_cfg *board_lpddr4_cfg;
+};
+
+/*
+ * Initialize default LPDDR4 settings for the board's version of cannonlake
+ * using the spd file specified by spd_index.  The spd_index is an index into
+ * the SPD_SOURCES array defined in spd/Makefile.inc.
+ */
+void meminit_lpddr4(FSP_M_CONFIG *cfg, const struct cnl_lpddr4_cfg *cnl_cfg,
+		size_t spd_index);
+
+#endif /* _SOC_CANNONLAKE_MEMINIT_H_ */
diff --git a/src/soc/intel/cannonlake/meminit.c b/src/soc/intel/cannonlake/meminit.c
new file mode 100644
index 0000000..ab1f95e
--- /dev/null
+++ b/src/soc/intel/cannonlake/meminit.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <console/console.h>
+#include <fsp/util.h>
+#include <soc/meminit.h>
+#include <string.h>
+#include <spd_bin.h>
+
+void meminit_lpddr4(FSP_M_CONFIG *mem_cfg,
+		const struct cnl_lpddr4_cfg *cnl_cfg,
+		size_t spd_index)
+{
+	const struct lpddr4_cfg *lpddr4_config = cnl_cfg->board_lpddr4_cfg;
+
+	/* rcomp targets for CNL-U and CNL-Y LPDDR4 */
+	const u8 lpddr4_rcomp_targets[] = { 80, 40, 40, 40, 30 };
+
+	memcpy(&mem_cfg->DqByteMapCh0, &lpddr4_config->dq_map[LP4_CH0],
+		sizeof(mem_cfg->DqByteMapCh0));
+	memcpy(&mem_cfg->DqByteMapCh1, &lpddr4_config->dq_map[LP4_CH1],
+		sizeof(mem_cfg->DqByteMapCh1));
+
+	memcpy(&mem_cfg->DqsMapCpu2DramCh0, &lpddr4_config->dqs_map[LP4_CH0],
+		sizeof(mem_cfg->DqsMapCpu2DramCh0));
+	memcpy(&mem_cfg->DqsMapCpu2DramCh1, &lpddr4_config->dqs_map[LP4_CH1],
+		sizeof(mem_cfg->DqsMapCpu2DramCh1));
+
+	memcpy(&mem_cfg->RcompResistor, &lpddr4_config->rcomp_resistor,
+		sizeof(mem_cfg->RcompResistor));
+
+	memcpy(&mem_cfg->RcompTarget, &lpddr4_rcomp_targets,
+		sizeof(mem_cfg->RcompTarget));
+
+	if (cnl_cfg->cnl_type == CANNONLAKE_Y) {
+		mem_cfg->DqPinsInterleaved = 0;
+		mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
+		mem_cfg->ECT = 1; /* Early Command Training Enabled */
+	} else if (cnl_cfg->cnl_type == CANNONLAKE_U) {
+		mem_cfg->DqPinsInterleaved = 1;
+		mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA VREF_DQ_B->CHB */
+	}
+
+	/* Get the memory spd index */
+	printk(BIOS_DEBUG, "SPD INDEX = %u\n", spd_index);
+
+	struct region_device spd_rdev;
+
+	if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)
+		die("spd.bin not found\n");
+
+	mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);
+	/* Memory leak is ok since we have memory mapped boot media */
+	mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);
+	mem_cfg->RefClk = 0; /* Auto Select CLK freq */
+	mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+}
+
+uint8_t fsp_memory_soc_version(void)
+{
+	/* Bump this value when the memory configuration parameters change. */
+	return 1;
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834
Gerrit-Change-Number: 22204
Gerrit-PatchSet: 1
Gerrit-Owner: Nick Vaccaro <nvaccaro at google.com>
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