<p>Nick Vaccaro has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22204">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: provide common LPDDR4 memory init<br><br>Instead of having the mainboards duplicate logic surrounding<br>LPDDR4 initialization provide helpers to do the heavy lifting.<br>It also handles the quirks of the FSP configuration which allows<br>the mainboard porting to focus on the schematic/design.<br><br>BUG=b:64395641<br>BRANCH=None<br>TEST=None<br><br>Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834<br>Signed-off-by: Nick Vaccaro <nvaccaro@google.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>A src/soc/intel/cannonlake/include/soc/meminit.h<br>A src/soc/intel/cannonlake/meminit.c<br>3 files changed, 150 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/22204/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 8dfff91..bd00b13 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -21,6 +21,7 @@<br> <br> romstage-y += gpio.c<br> romstage-y += gspi.c<br>+romstage-y += meminit.c<br> romstage-y += memmap.c<br> romstage-y += pmutil.c<br> romstage-y += reset.c<br>diff --git a/src/soc/intel/cannonlake/include/soc/meminit.h b/src/soc/intel/cannonlake/include/soc/meminit.h<br>new file mode 100644<br>index 0000000..6c74703<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/include/soc/meminit.h<br>@@ -0,0 +1,75 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef _SOC_CANNONLAKE_MEMINIT_H_<br>+#define _SOC_CANNONLAKE_MEMINIT_H_<br>+<br>+#include <stddef.h><br>+#include <stdint.h><br>+#include <fsp/soc_binding.h><br>+<br>+<br>+/* Number of dq bits controlled per dqs */<br>+#define DQ_BITS_PER_DQS 8<br>+<br>+/* Channel identification. */<br>+enum {<br>+ LP4_CH0 = 0,<br>+ LP4_CH1,<br>+ LP4_NUM_CHANNELS<br>+};<br>+<br>+/* Cannon Lake PCH family skus */<br>+typedef enum {<br>+ CANNONLAKE_U,<br>+ CANNONLAKE_Y<br>+} cannonlake_type;<br>+<br>+/* Board-specific lpddr4 dq mapping information */<br>+struct lpddr4_cfg {<br>+ /* DQ byte map Ch0 and Ch1 */<br>+ const u8 dq_map[LP4_NUM_CHANNELS][12];<br>+<br>+ /* DQS CPU<>DRAM map Ch0 and Ch1 */<br>+ const u8 dqs_map[LP4_NUM_CHANNELS][DQ_BITS_PER_DQS];<br>+<br>+ /* Rcomp resistor */<br>+ const u16 rcomp_resistor[3];<br>+};<br>+<br>+/*<br>+ * The cnl_lpddr4_cfg struct contains the board-specific info<br>+ * needed to inialize a Cannon Lake based board to use lpddr4 memory<br>+ * Only additional information needed is the spd index to use, which<br>+ * will get passed into meminit_lpddr4() as an input parameter.<br>+ */<br>+struct cnl_lpddr4_cfg {<br>+<br>+ /* Cannonlake PCH Type */<br>+ const cannonlake_type cnl_type;<br>+<br>+ /* Board-specific lpddr4 info */<br>+ const struct lpddr4_cfg *board_lpddr4_cfg;<br>+};<br>+<br>+/*<br>+ * Initialize default LPDDR4 settings for the board's version of cannonlake<br>+ * using the spd file specified by spd_index. The spd_index is an index into<br>+ * the SPD_SOURCES array defined in spd/Makefile.inc.<br>+ */<br>+void meminit_lpddr4(FSP_M_CONFIG *cfg, const struct cnl_lpddr4_cfg *cnl_cfg,<br>+ size_t spd_index);<br>+<br>+#endif /* _SOC_CANNONLAKE_MEMINIT_H_ */<br>diff --git a/src/soc/intel/cannonlake/meminit.c b/src/soc/intel/cannonlake/meminit.c<br>new file mode 100644<br>index 0000000..ab1f95e<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/meminit.c<br>@@ -0,0 +1,74 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2016 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+#include <console/console.h><br>+#include <fsp/util.h><br>+#include <soc/meminit.h><br>+#include <string.h><br>+#include <spd_bin.h><br>+<br>+void meminit_lpddr4(FSP_M_CONFIG *mem_cfg,<br>+ const struct cnl_lpddr4_cfg *cnl_cfg,<br>+ size_t spd_index)<br>+{<br>+ const struct lpddr4_cfg *lpddr4_config = cnl_cfg->board_lpddr4_cfg;<br>+<br>+ /* rcomp targets for CNL-U and CNL-Y LPDDR4 */<br>+ const u8 lpddr4_rcomp_targets[] = { 80, 40, 40, 40, 30 };<br>+<br>+ memcpy(&mem_cfg->DqByteMapCh0, &lpddr4_config->dq_map[LP4_CH0],<br>+ sizeof(mem_cfg->DqByteMapCh0));<br>+ memcpy(&mem_cfg->DqByteMapCh1, &lpddr4_config->dq_map[LP4_CH1],<br>+ sizeof(mem_cfg->DqByteMapCh1));<br>+<br>+ memcpy(&mem_cfg->DqsMapCpu2DramCh0, &lpddr4_config->dqs_map[LP4_CH0],<br>+ sizeof(mem_cfg->DqsMapCpu2DramCh0));<br>+ memcpy(&mem_cfg->DqsMapCpu2DramCh1, &lpddr4_config->dqs_map[LP4_CH1],<br>+ sizeof(mem_cfg->DqsMapCpu2DramCh1));<br>+<br>+ memcpy(&mem_cfg->RcompResistor, &lpddr4_config->rcomp_resistor,<br>+ sizeof(mem_cfg->RcompResistor));<br>+<br>+ memcpy(&mem_cfg->RcompTarget, &lpddr4_rcomp_targets,<br>+ sizeof(mem_cfg->RcompTarget));<br>+<br>+ if (cnl_cfg->cnl_type == CANNONLAKE_Y) {<br>+ mem_cfg->DqPinsInterleaved = 0;<br>+ mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */<br>+ mem_cfg->ECT = 1; /* Early Command Training Enabled */<br>+ } else if (cnl_cfg->cnl_type == CANNONLAKE_U) {<br>+ mem_cfg->DqPinsInterleaved = 1;<br>+ mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA VREF_DQ_B->CHB */<br>+ }<br>+<br>+ /* Get the memory spd index */<br>+ printk(BIOS_DEBUG, "SPD INDEX = %u\n", spd_index);<br>+<br>+ struct region_device spd_rdev;<br>+<br>+ if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0)<br>+ die("spd.bin not found\n");<br>+<br>+ mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev);<br>+ /* Memory leak is ok since we have memory mapped boot media */<br>+ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev);<br>+ mem_cfg->RefClk = 0; /* Auto Select CLK freq */<br>+ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;<br>+}<br>+<br>+uint8_t fsp_memory_soc_version(void)<br>+{<br>+ /* Bump this value when the memory configuration parameters change. */<br>+ return 1;<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/22204">change 22204</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22204"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 </div>
<div style="display:none"> Gerrit-Change-Number: 22204 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com> </div>