[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Fix broken GNVS offset for chromeos

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22177


Change subject: soc/intel/apollolake: Fix broken GNVS offset for chromeos
......................................................................

soc/intel/apollolake: Fix broken GNVS offset for chromeos

Change 03a235(soc/intel/apollolake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.

This change fixes the above issue by reducing the size of unused array.

BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.

Change-Id: I279bfc4c702e46b88c1c7a067a24326ff8fed368
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/apollolake/include/soc/nvs.h
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/22177/1

diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index dd0746b..2c9a4b5 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -47,7 +47,7 @@
 	uint8_t		ecps; /* 0x2C - SGX Enabled status */
 	uint64_t	emna; /* 0x2D - 0x34 EPC base address */
 	uint64_t	elng; /* 0x35 - 0x3C EPC Length */
-	uint8_t		unused[212];
+	uint8_t		unused[195];
 
 	/* ChromeOS specific (0x100 - 0xfff) */
 	chromeos_acpi_t chromeos;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I279bfc4c702e46b88c1c7a067a24326ff8fed368
Gerrit-Change-Number: 22177
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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