[coreboot-gerrit] Change in coreboot[master]: nautilus: adapting board configuration setting.
Chris Wang (Code Review)
gerrit at coreboot.org
Wed Oct 25 15:48:00 CEST 2017
Hello Chris Wang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/22175
to review the following change.
Change subject: nautilus: adapting board configuration setting.
......................................................................
nautilus: adapting board configuration setting.
1.update gpio table to meet nautilus's schematic design.
2.add SPD data by RAM ID.
K4E8E324EB-EGCF # 0b0000
K4E6E304EB-EGCF # 0b0001
K4EBE304EB-EGCG # 0b0010
3.add elan touchpad support.
BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot
Change-Id: I29d8a76b170aee64bb0125276df0e4709012daba
Signed-off-by: Chris Wang <chriswang at ami.corp-partner.google.com>
---
M src/mainboard/google/poppy/variants/nautilus/Makefile.inc
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/gpio.c
3 files changed, 49 insertions(+), 40 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/22175/1
diff --git a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc
index b7ae5e7..2854c86 100644
--- a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc
+++ b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc
@@ -1,5 +1,7 @@
-SPD_SOURCES = empty # 0b0000
+SPD_SOURCES = samsung_dimm_K4E8E324EB-EGCF # 0b0000
+SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0001
+SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0010
bootblock-y += gpio.c
ramstage-y += gpio.c
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 9530cd9..9d08efc 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -232,7 +232,15 @@
device i2c 50 on end
end
end # I2C #1
- device pci 15.2 on end # I2C #2
+ device pci 15.2 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"
+ register "wake" = "GPE0_DW0_05"
+ device i2c 15 on end
+ end
+ end # I2C #2
device pci 15.3 on end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c
index 6f7a3e7..0bc16a2 100644
--- a/src/mainboard/google/poppy/variants/nautilus/gpio.c
+++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c
@@ -53,13 +53,13 @@
PAD_CFG_NC(GPP_A18),
/* A19 : ISH_GP1 ==> NC */
PAD_CFG_NC(GPP_A19),
- /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */
- PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST),
+ /* A20 : ISH_GP2 ==> NC */
+ PAD_CFG_NC(GPP_A20),
/* A21 : ISH_GP3 ==> NC */
PAD_CFG_NC(GPP_A21),
- /* A22 : ISH_GP4 ==> NC */
- PAD_CFG_NC(GPP_A22),
- /* A23 : ISH_GP5 ==> NC */
+ /* A22 : ISH_GP4 ==> DIG_IRQ_L */
+ PAD_CFG_GPI_APIC(GPP_A22, NONE, PLTRST),
+ /* A23 : ISH_GP5 ==> SPK_PA_EN ##### */
PAD_CFG_NC(GPP_A23),
/* B0 : CORE_VID0 ==> NC(TP42) */
@@ -68,16 +68,18 @@
PAD_CFG_NC(GPP_B1),
/* B2 : VRALERT# ==> NC */
PAD_CFG_NC(GPP_B2),
- /* B3 : CPU_GP2 ==> NC */
- PAD_CFG_NC(GPP_B3),
+ /* B3 : CPU_GP2 ==> TP_INT_L */
+ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
/* B4 : CPU_GP3 ==> NC */
PAD_CFG_NC(GPP_B4),
- /* B5 : SRCCLKREQ0# ==> NC */
- PAD_CFG_NC(GPP_B5),
+ /* B5 : SRCCLKREQ0# ==> TP_INT_L - for wake event */
+ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT),
/* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */
PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* B7 : SRCCLKREQ2# ==> NC */
PAD_CFG_NC(GPP_B7),
+ /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
+ PAD_CFG_GPO(GPP_B8, 0, DEEP),
/* B9 : SRCCLKREQ4# ==> NC */
PAD_CFG_NC(GPP_B9),
/* B10 : SRCCLKREQ5# ==> NC */
@@ -109,21 +111,21 @@
/* B18 : GSPI0_MOSI ==> NC */
PAD_CFG_NC(GPP_B18),
#endif
- /* B19 : GSPI1_CS# ==> NC */
- PAD_CFG_NC(GPP_B19),
+ /* B19 : GSPI1_CS# ==> PEN_EJECT - for notification */
+ PAD_CFG_GPI(GPP_B19, NONE, DEEP),
/* B20 : GSPI1_CLK ==> NC */
PAD_CFG_NC(GPP_B20),
- /* B21 : GSPI1_MISO ==> NC */
- PAD_CFG_NC(GPP_B21),
+ /* B21 : GSPI1_MISO ==> PEN_EJECT - for wake event */
+ PAD_CFG_GPI_ACPI_SCI(GPP_B21, NONE, DEEP, NONE),
/* B22 : GSPI1_MOSI ==> NC */
PAD_CFG_NC(GPP_B22),
/* B23 : SM1ALERT# ==> NC */
PAD_CFG_NC(GPP_B23),
- /* C0 : SMBCLK ==> NC */
- PAD_CFG_NC(GPP_C0),
- /* C1 : SMBDATA ==> NC */
- PAD_CFG_NC(GPP_C1),
+ /* C0 : SMBCLK ==> SMBCLK */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+ /* C1 : SMBDATA ==> SMBDATA */
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
/* C2 : SMBALERT# ==> NC */
PAD_CFG_NC(GPP_C2),
/* C3 : SML0CLK ==> NC */
@@ -136,13 +138,13 @@
PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),
/* C7 : SM1DATA ==> NC */
PAD_CFG_NC(GPP_C7),
- /* C8 : UART0_RXD ==> FP_INT */
- PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),
- /* C9 : UART0_TXD ==> FP_RST_ODL */
- PAD_CFG_GPO(GPP_C9, 0, DEEP),
- /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */
- PAD_CFG_GPO(GPP_C10, 1, DEEP),
- /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */
+ /* C8 : UART0_RXD ==> NC */
+ PAD_CFG_NC(GPP_C8),
+ /* C9 : UART0_TXD ==> NC */
+ PAD_CFG_NC(GPP_C9),
+ /* C10 : UART0_RTS# ==> NC */
+ PAD_CFG_NC(GPP_C10),
+ /* C11 : UART0_CTS# ==> P3300_DX_DIG_EN */
PAD_CFG_GPO(GPP_C11, 1, DEEP),
/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
PAD_CFG_GPI(GPP_C12, NONE, DEEP),
@@ -178,13 +180,13 @@
/* D0 : SPI1_CS# ==> NC */
PAD_CFG_NC(GPP_D0),
- /* D1 : SPI1_CLK ==> NC */
+ /* D1 : SPI1_CLK ==> VDD_CAM_AF_EN */
PAD_CFG_NC(GPP_D1),
- /* D2 : SPI1_MISO ==> NC */
+ /* D2 : SPI1_MISO ==> VDD_CAM_IO_EN */
PAD_CFG_NC(GPP_D2),
- /* D3 : SPI1_MOSI ==> NC */
+ /* D3 : SPI1_MOSI ==> VDD_CAM_A2P8_EN */
PAD_CFG_NC(GPP_D3),
- /* D4 : FASHTRIG ==> NC */
+ /* D4 : FASHTRIG ==> VDD_CAM_CORE_EN */
PAD_CFG_NC(GPP_D4),
/* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */
PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),
@@ -196,10 +198,10 @@
PAD_CFG_NC(GPP_D8),
/* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
PAD_CFG_GPI(GPP_D9, NONE, PLTRST),
- /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */
+ /* D10 : ISH_SPI_CLK ==> CAM_RST */
PAD_CFG_GPO(GPP_D10, 1, DEEP),
- /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */
- PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),
+ /* D11 : ISH_SPI_MISO ==> CAM_MCLK_EN */
+ PAD_CFG_GPO(GPP_D11, 1, DEEP),
/* D12 : ISH_SPI_MOSI ==> NC */
PAD_CFG_NC(GPP_D12),
/* D13 : ISH_UART0_RXD ==> NC */
@@ -231,8 +233,8 @@
PAD_CFG_NC(GPP_E1),
/* E2 : SATAXPCIE2 ==> NC */
PAD_CFG_NC(GPP_E2),
- /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */
- PAD_CFG_GPO(GPP_E3, 0, DEEP),
+ /* E3 : CPU_GP0 ==> NC */
+ PAD_CFG_NC(GPP_E3),
/* E4 : SATA_DEVSLP0 ==> NC */
PAD_CFG_NC(GPP_E4),
/* E5 : SATA_DEVSLP1 ==> NC */
@@ -321,8 +323,8 @@
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* F22 : EMMC_CLK */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
- /* F23 : RSVD ==> NC */
- PAD_CFG_NC(GPP_F23),
+ /* F23 : RSVD ==> DIG_PDCT_L */
+ PAD_CFG_GPI_APIC(GPP_F23, NONE, PLTRST),
/* G0 : SD_CMD */
PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
@@ -369,9 +371,6 @@
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
- /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
- PAD_CFG_GPO(GPP_B8, 0, DEEP),
-
#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
--
To view, visit https://review.coreboot.org/22175
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I29d8a76b170aee64bb0125276df0e4709012daba
Gerrit-Change-Number: 22175
Gerrit-PatchSet: 1
Gerrit-Owner: Chris Wang <chriswang at ami.com.tw>
Gerrit-Reviewer: Chris Wang <chriswang at ami.corp-partner.google.com>
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