<p>Chris Wang would like Chris Wang to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/22175">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nautilus: adapting board configuration setting.<br><br>1.update gpio table to meet nautilus's schematic design.<br>2.add SPD data by RAM ID.<br> K4E8E324EB-EGCF # 0b0000<br> K4E6E304EB-EGCF # 0b0001<br> K4EBE304EB-EGCG # 0b0010<br>3.add elan touchpad support.<br><br>BRANCH=master<br>BUG=b:66462881<br>TEST=emerge-nautilus coreboot<br><br>Change-Id: I29d8a76b170aee64bb0125276df0e4709012daba<br>Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com><br>---<br>M src/mainboard/google/poppy/variants/nautilus/Makefile.inc<br>M src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>M src/mainboard/google/poppy/variants/nautilus/gpio.c<br>3 files changed, 49 insertions(+), 40 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/22175/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc<br>index b7ae5e7..2854c86 100644<br>--- a/src/mainboard/google/poppy/variants/nautilus/Makefile.inc<br>+++ b/src/mainboard/google/poppy/variants/nautilus/Makefile.inc<br>@@ -1,5 +1,7 @@<br> <br>-SPD_SOURCES = empty # 0b0000<br>+SPD_SOURCES = samsung_dimm_K4E8E324EB-EGCF # 0b0000<br>+SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0001<br>+SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0010<br> <br> bootblock-y += gpio.c<br> ramstage-y += gpio.c<br>diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>index 9530cd9..9d08efc 100644<br>--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb<br>@@ -232,7 +232,15 @@<br> device i2c 50 on end<br> end<br> end # I2C #1<br>- device pci 15.2 on end # I2C #2<br>+ device pci 15.2 on<br>+ chip drivers/i2c/generic<br>+ register "hid" = ""ELAN0000""<br>+ register "desc" = ""ELAN Touchpad""<br>+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)"<br>+ register "wake" = "GPE0_DW0_05"<br>+ device i2c 15 on end<br>+ end<br>+ end # I2C #2<br> device pci 15.3 on end # I2C #3<br> device pci 16.0 on end # Management Engine Interface 1<br> device pci 16.1 off end # Management Engine Interface 2<br>diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c<br>index 6f7a3e7..0bc16a2 100644<br>--- a/src/mainboard/google/poppy/variants/nautilus/gpio.c<br>+++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c<br>@@ -53,13 +53,13 @@<br> PAD_CFG_NC(GPP_A18),<br> /* A19 : ISH_GP1 ==> NC */<br> PAD_CFG_NC(GPP_A19),<br>- /* A20 : ISH_GP2 ==> ACCEL_GYRO_INT_L */<br>- PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST),<br>+ /* A20 : ISH_GP2 ==> NC */<br>+ PAD_CFG_NC(GPP_A20),<br> /* A21 : ISH_GP3 ==> NC */<br> PAD_CFG_NC(GPP_A21),<br>- /* A22 : ISH_GP4 ==> NC */<br>- PAD_CFG_NC(GPP_A22),<br>- /* A23 : ISH_GP5 ==> NC */<br>+ /* A22 : ISH_GP4 ==> DIG_IRQ_L */<br>+ PAD_CFG_GPI_APIC(GPP_A22, NONE, PLTRST),<br>+ /* A23 : ISH_GP5 ==> SPK_PA_EN ##### */<br> PAD_CFG_NC(GPP_A23),<br> <br> /* B0 : CORE_VID0 ==> NC(TP42) */<br>@@ -68,16 +68,18 @@<br> PAD_CFG_NC(GPP_B1),<br> /* B2 : VRALERT# ==> NC */<br> PAD_CFG_NC(GPP_B2),<br>- /* B3 : CPU_GP2 ==> NC */<br>- PAD_CFG_NC(GPP_B3),<br>+ /* B3 : CPU_GP2 ==> TP_INT_L */<br>+ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),<br> /* B4 : CPU_GP3 ==> NC */<br> PAD_CFG_NC(GPP_B4),<br>- /* B5 : SRCCLKREQ0# ==> NC */<br>- PAD_CFG_NC(GPP_B5),<br>+ /* B5 : SRCCLKREQ0# ==> TP_INT_L - for wake event */<br>+ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, INVERT),<br> /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */<br> PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),<br> /* B7 : SRCCLKREQ2# ==> NC */<br> PAD_CFG_NC(GPP_B7),<br>+ /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */<br>+ PAD_CFG_GPO(GPP_B8, 0, DEEP),<br> /* B9 : SRCCLKREQ4# ==> NC */<br> PAD_CFG_NC(GPP_B9),<br> /* B10 : SRCCLKREQ5# ==> NC */<br>@@ -109,21 +111,21 @@<br> /* B18 : GSPI0_MOSI ==> NC */<br> PAD_CFG_NC(GPP_B18),<br> #endif<br>- /* B19 : GSPI1_CS# ==> NC */<br>- PAD_CFG_NC(GPP_B19),<br>+ /* B19 : GSPI1_CS# ==> PEN_EJECT - for notification */<br>+ PAD_CFG_GPI(GPP_B19, NONE, DEEP),<br> /* B20 : GSPI1_CLK ==> NC */<br> PAD_CFG_NC(GPP_B20),<br>- /* B21 : GSPI1_MISO ==> NC */<br>- PAD_CFG_NC(GPP_B21),<br>+ /* B21 : GSPI1_MISO ==> PEN_EJECT - for wake event */<br>+ PAD_CFG_GPI_ACPI_SCI(GPP_B21, NONE, DEEP, NONE),<br> /* B22 : GSPI1_MOSI ==> NC */<br> PAD_CFG_NC(GPP_B22),<br> /* B23 : SM1ALERT# ==> NC */<br> PAD_CFG_NC(GPP_B23),<br> <br>- /* C0 : SMBCLK ==> NC */<br>- PAD_CFG_NC(GPP_C0),<br>- /* C1 : SMBDATA ==> NC */<br>- PAD_CFG_NC(GPP_C1),<br>+ /* C0 : SMBCLK ==> SMBCLK */<br>+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),<br>+ /* C1 : SMBDATA ==> SMBDATA */<br>+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),<br> /* C2 : SMBALERT# ==> NC */<br> PAD_CFG_NC(GPP_C2),<br> /* C3 : SML0CLK ==> NC */<br>@@ -136,13 +138,13 @@<br> PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP),<br> /* C7 : SM1DATA ==> NC */<br> PAD_CFG_NC(GPP_C7),<br>- /* C8 : UART0_RXD ==> FP_INT */<br>- PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),<br>- /* C9 : UART0_TXD ==> FP_RST_ODL */<br>- PAD_CFG_GPO(GPP_C9, 0, DEEP),<br>- /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */<br>- PAD_CFG_GPO(GPP_C10, 1, DEEP),<br>- /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */<br>+ /* C8 : UART0_RXD ==> NC */<br>+ PAD_CFG_NC(GPP_C8),<br>+ /* C9 : UART0_TXD ==> NC */<br>+ PAD_CFG_NC(GPP_C9),<br>+ /* C10 : UART0_RTS# ==> NC */<br>+ PAD_CFG_NC(GPP_C10),<br>+ /* C11 : UART0_CTS# ==> P3300_DX_DIG_EN */<br> PAD_CFG_GPO(GPP_C11, 1, DEEP),<br> /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */<br> PAD_CFG_GPI(GPP_C12, NONE, DEEP),<br>@@ -178,13 +180,13 @@<br> <br> /* D0 : SPI1_CS# ==> NC */<br> PAD_CFG_NC(GPP_D0),<br>- /* D1 : SPI1_CLK ==> NC */<br>+ /* D1 : SPI1_CLK ==> VDD_CAM_AF_EN */<br> PAD_CFG_NC(GPP_D1),<br>- /* D2 : SPI1_MISO ==> NC */<br>+ /* D2 : SPI1_MISO ==> VDD_CAM_IO_EN */<br> PAD_CFG_NC(GPP_D2),<br>- /* D3 : SPI1_MOSI ==> NC */<br>+ /* D3 : SPI1_MOSI ==> VDD_CAM_A2P8_EN */<br> PAD_CFG_NC(GPP_D3),<br>- /* D4 : FASHTRIG ==> NC */<br>+ /* D4 : FASHTRIG ==> VDD_CAM_CORE_EN */<br> PAD_CFG_NC(GPP_D4),<br> /* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */<br> PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),<br>@@ -196,10 +198,10 @@<br> PAD_CFG_NC(GPP_D8),<br> /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */<br> PAD_CFG_GPI(GPP_D9, NONE, PLTRST),<br>- /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */<br>+ /* D10 : ISH_SPI_CLK ==> CAM_RST */<br> PAD_CFG_GPO(GPP_D10, 1, DEEP),<br>- /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */<br>- PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),<br>+ /* D11 : ISH_SPI_MISO ==> CAM_MCLK_EN */<br>+ PAD_CFG_GPO(GPP_D11, 1, DEEP),<br> /* D12 : ISH_SPI_MOSI ==> NC */<br> PAD_CFG_NC(GPP_D12),<br> /* D13 : ISH_UART0_RXD ==> NC */<br>@@ -231,8 +233,8 @@<br> PAD_CFG_NC(GPP_E1),<br> /* E2 : SATAXPCIE2 ==> NC */<br> PAD_CFG_NC(GPP_E2),<br>- /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */<br>- PAD_CFG_GPO(GPP_E3, 0, DEEP),<br>+ /* E3 : CPU_GP0 ==> NC */<br>+ PAD_CFG_NC(GPP_E3),<br> /* E4 : SATA_DEVSLP0 ==> NC */<br> PAD_CFG_NC(GPP_E4),<br> /* E5 : SATA_DEVSLP1 ==> NC */<br>@@ -321,8 +323,8 @@<br> PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),<br> /* F22 : EMMC_CLK */<br> PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),<br>- /* F23 : RSVD ==> NC */<br>- PAD_CFG_NC(GPP_F23),<br>+ /* F23 : RSVD ==> DIG_PDCT_L */<br>+ PAD_CFG_GPI_APIC(GPP_F23, NONE, PLTRST),<br> <br> /* G0 : SD_CMD */<br> PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),<br>@@ -369,9 +371,6 @@<br> <br> /* Early pad configuration in bootblock */<br> static const struct pad_config early_gpio_table[] = {<br>- /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */<br>- PAD_CFG_GPO(GPP_B8, 0, DEEP),<br>-<br> #if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)<br> /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */<br> PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),<br></pre><p>To view, visit <a href="https://review.coreboot.org/22175">change 22175</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22175"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I29d8a76b170aee64bb0125276df0e4709012daba </div>
<div style="display:none"> Gerrit-Change-Number: 22175 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Chris Wang <chriswang@ami.com.tw> </div>
<div style="display:none"> Gerrit-Reviewer: Chris Wang <chriswang@ami.corp-partner.google.com> </div>