[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Set CPU to Max Non-Turbo Ratio

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/22148


Change subject: soc/intel/apollolake: Set CPU to Max Non-Turbo Ratio
......................................................................

soc/intel/apollolake: Set CPU to Max Non-Turbo Ratio

If the Running Average Power Limits (RAPL) feature is disabled, the CPU
should be set to the Max Non-Turbo Ratio. RAPL is switched off by
CONFIG_APL_SKIP_SET_POWER_LIMITS. Furthermore, a frequency change should
be prevented by disabling Enhanced Intel Speedstep Technology (EIST). So
the CPU should run with constant frequency with this setting.

Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01
Signed-off-by: Mario Scheithauer <mario.scheithauer at siemens.com>
---
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/common/block/include/intelblocks/msr.h
2 files changed, 28 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/22148/1

diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index db9dc1b..6e7d00b 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2015-2017 Intel Corp.
+ * Copyright (C) 2017 Siemens AG.
  * (Written by Andrey Petrov <andrey.petrov at intel.com> for Intel Corp.)
  * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
  *
@@ -64,6 +65,27 @@
 	REG_SCRIPT_END
 };
 
+static void set_max_ratio(void)
+{
+	msr_t msr, perf_ctl;
+
+	perf_ctl.hi = 0;
+
+	/* Read the Max Non-Turbo Ratio from MSR PLATFORM_INFO (CEh) [15:8]. */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	perf_ctl.lo = msr.lo & 0x7f00;
+	/* Program the Maximum Non-Turbo ratio in MSR IA32_PERF_CTL (199h)
+	   [14:8]. */
+	wrmsr(MSR_IA32_PERF_CTL, perf_ctl);
+
+	/* Read MSR IA32_MISC_ENABLE (1A0h) */
+	msr = rdmsr(IA32_MISC_ENABLE);
+	/* Disable Geyserville3/EIST for a stable frequency. */
+	msr.lo &= ~ENABLE_GV3;
+	/* Write MSR IA32_MISC_ENABLE back. */
+	wrmsr(IA32_MISC_ENABLE, msr);
+}
+
 void soc_core_init(device_t cpu)
 {
 	/* Clear out pending MCEs */
@@ -84,6 +106,10 @@
 	/* Configure Core PRMRR for SGX. */
 	if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX))
 		prmrr_core_configure();
+
+	/* Set Max Non-Turbo ratio if RAPL is disabled. */
+	if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS))
+		set_max_ratio();
 }
 
 #if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 45f201c..71ee506 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright 2017 Intel Corporation.
+ * Copyright 2017 Siemens AG.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -54,6 +55,7 @@
 #define  FLEX_RATIO_EN			(1 << 16)
 #define MSR_IA32_PERF_CTL	0x199
 #define IA32_MISC_ENABLE	0x1a0
+#define  ENABLE_GV3			(1 << 16)
 /* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */
 #define BURST_MODE_DISABLE		(1 << 6)
 #define MSR_TEMPERATURE_TARGET	0x1a2

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01
Gerrit-Change-Number: 22148
Gerrit-PatchSet: 1
Gerrit-Owner: Mario Scheithauer <mario.scheithauer at siemens.com>
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