<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22148">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Set CPU to Max Non-Turbo Ratio<br><br>If the Running Average Power Limits (RAPL) feature is disabled, the CPU<br>should be set to the Max Non-Turbo Ratio. RAPL is switched off by<br>CONFIG_APL_SKIP_SET_POWER_LIMITS. Furthermore, a frequency change should<br>be prevented by disabling Enhanced Intel Speedstep Technology (EIST). So<br>the CPU should run with constant frequency with this setting.<br><br>Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/soc/intel/apollolake/cpu.c<br>M src/soc/intel/common/block/include/intelblocks/msr.h<br>2 files changed, 28 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/22148/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c<br>index db9dc1b..6e7d00b 100644<br>--- a/src/soc/intel/apollolake/cpu.c<br>+++ b/src/soc/intel/apollolake/cpu.c<br>@@ -2,6 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2015-2017 Intel Corp.<br>+ * Copyright (C) 2017 Siemens AG.<br> * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)<br> * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)<br> *<br>@@ -64,6 +65,27 @@<br> REG_SCRIPT_END<br> };<br> <br>+static void set_max_ratio(void)<br>+{<br>+ msr_t msr, perf_ctl;<br>+<br>+ perf_ctl.hi = 0;<br>+<br>+ /* Read the Max Non-Turbo Ratio from MSR PLATFORM_INFO (CEh) [15:8]. */<br>+ msr = rdmsr(MSR_PLATFORM_INFO);<br>+ perf_ctl.lo = msr.lo & 0x7f00;<br>+ /* Program the Maximum Non-Turbo ratio in MSR IA32_PERF_CTL (199h)<br>+ [14:8]. */<br>+ wrmsr(MSR_IA32_PERF_CTL, perf_ctl);<br>+<br>+ /* Read MSR IA32_MISC_ENABLE (1A0h) */<br>+ msr = rdmsr(IA32_MISC_ENABLE);<br>+ /* Disable Geyserville3/EIST for a stable frequency. */<br>+ msr.lo &= ~ENABLE_GV3;<br>+ /* Write MSR IA32_MISC_ENABLE back. */<br>+ wrmsr(IA32_MISC_ENABLE, msr);<br>+}<br>+<br> void soc_core_init(device_t cpu)<br> {<br> /* Clear out pending MCEs */<br>@@ -84,6 +106,10 @@<br> /* Configure Core PRMRR for SGX. */<br> if (IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX))<br> prmrr_core_configure();<br>+<br>+ /* Set Max Non-Turbo ratio if RAPL is disabled. */<br>+ if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS))<br>+ set_max_ratio();<br> }<br> <br> #if !IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)<br>diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h<br>index 45f201c..71ee506 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/msr.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/msr.h<br>@@ -2,6 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright 2017 Intel Corporation.<br>+ * Copyright 2017 Siemens AG.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -54,6 +55,7 @@<br> #define FLEX_RATIO_EN (1 << 16)<br> #define MSR_IA32_PERF_CTL 0x199<br> #define IA32_MISC_ENABLE 0x1a0<br>+#define ENABLE_GV3 (1 << 16)<br> /* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */<br> #define BURST_MODE_DISABLE (1 << 6)<br> #define MSR_TEMPERATURE_TARGET 0x1a2<br></pre><p>To view, visit <a href="https://review.coreboot.org/22148">change 22148</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22148"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01 </div>
<div style="display:none"> Gerrit-Change-Number: 22148 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>