[coreboot-gerrit] Change in coreboot[master]: intel/cannonlake_rvp: Disable P2SB in device tree

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22133


Change subject: intel/cannonlake_rvp: Disable P2SB in device tree
......................................................................

intel/cannonlake_rvp: Disable P2SB in device tree

Bar0 of P2SB is SBREG_BAR, avoid PCI enumeration of P2SB to keep the
base address unchanged until OS stage.

TEST=Boot up system in OS, mmio read offset 0xfd6a0000, return value is
not 0xffffffff.

Change-Id: I46a89b5e81f43d8136c70838d80bb0cc017e5245
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/22133/1

diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index c3223b1..ceebd01 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -117,7 +117,7 @@
 				device pnp 0c31.0 on end
 			end
 		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
+		device pci 1f.1 off  end # P2SB
 		device pci 1f.2 on  end # Power Management Controller
 		device pci 1f.3 on  end # Intel HDA
 		device pci 1f.4 on  end # SMBus
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 4bada02..4be0f1b 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -115,7 +115,7 @@
 				device pnp 0c31.0 on end
 			end
 		end # LPC Interface
-		device pci 1f.1 on  end # P2SB
+		device pci 1f.1 off end # P2SB
 		device pci 1f.2 on  end # Power Management Controller
 		device pci 1f.3 on  end # Intel HDA
 		device pci 1f.4 on  end # SMBus

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I46a89b5e81f43d8136c70838d80bb0cc017e5245
Gerrit-Change-Number: 22133
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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