<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22133">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/cannonlake_rvp: Disable P2SB in device tree<br><br>Bar0 of P2SB is SBREG_BAR, avoid PCI enumeration of P2SB to keep the<br>base address unchanged until OS stage.<br><br>TEST=Boot up system in OS, mmio read offset 0xfd6a0000, return value is<br>not 0xffffffff.<br><br>Change-Id: I46a89b5e81f43d8136c70838d80bb0cc017e5245<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>2 files changed, 2 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/22133/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>index c3223b1..ceebd01 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>@@ -117,7 +117,7 @@<br>                               device pnp 0c31.0 on end<br>                      end<br>           end # LPC Interface<br>-          device pci 1f.1 on  end # P2SB<br>+               device pci 1f.1 off  end # P2SB<br>               device pci 1f.2 on  end # Power Management Controller<br>                 device pci 1f.3 on  end # Intel HDA<br>           device pci 1f.4 on  end # SMBus<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>index 4bada02..4be0f1b 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>@@ -115,7 +115,7 @@<br>                             device pnp 0c31.0 on end<br>                      end<br>           end # LPC Interface<br>-          device pci 1f.1 on  end # P2SB<br>+               device pci 1f.1 off end # P2SB<br>                device pci 1f.2 on  end # Power Management Controller<br>                 device pci 1f.3 on  end # Intel HDA<br>           device pci 1f.4 on  end # SMBus<br></pre><p>To view, visit <a href="https://review.coreboot.org/22133">change 22133</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22133"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I46a89b5e81f43d8136c70838d80bb0cc017e5245 </div>
<div style="display:none"> Gerrit-Change-Number: 22133 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>