[coreboot-gerrit] Change in coreboot[master]: [WIP/TEST] Use UDELAY_TSC using calibrate_tsc_with_pit

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22101


Change subject: [WIP/TEST] Use UDELAY_TSC using calibrate_tsc_with_pit
......................................................................

[WIP/TEST] Use UDELAY_TSC using calibrate_tsc_with_pit

Change-Id: I405eae497ffd7a3c1854f98f5b592e4f00d70a97
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/model_1067x/Kconfig
M src/cpu/intel/model_6ex/Kconfig
M src/cpu/intel/model_6fx/Kconfig
M src/cpu/x86/tsc/Makefile.inc
M src/cpu/x86/tsc/delay_tsc.c
M src/northbridge/intel/gm45/Makefile.inc
6 files changed, 14 insertions(+), 10 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/22101/1

diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
index 2e154a3..2c2bd7c 100644
--- a/src/cpu/intel/model_1067x/Kconfig
+++ b/src/cpu/intel/model_1067x/Kconfig
@@ -6,7 +6,7 @@
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
 	select SSE2
-#	select UDELAY_LAPIC
+	select UDELAY_TSC
 	select TSC_SYNC_MFENCE
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig
index 10ebcc7..29563d8 100644
--- a/src/cpu/intel/model_6ex/Kconfig
+++ b/src/cpu/intel/model_6ex/Kconfig
@@ -6,7 +6,7 @@
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
 	select SSE2
-	select UDELAY_LAPIC
+	select UDELAY_TSC
 	select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
 	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
index 8f05314..20b53a5 100644
--- a/src/cpu/intel/model_6fx/Kconfig
+++ b/src/cpu/intel/model_6fx/Kconfig
@@ -6,7 +6,7 @@
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
 	select SSE2
-	select UDELAY_LAPIC
+	select UDELAY_TSC
 	select AP_IN_SIPI_WAIT
 	select TSC_SYNC_MFENCE
 	select SUPPORT_CPU_UCODE_IN_CBFS
diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc
index 9751cac..af131e7 100644
--- a/src/cpu/x86/tsc/Makefile.inc
+++ b/src/cpu/x86/tsc/Makefile.inc
@@ -1,8 +1,8 @@
 bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c
 ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
-romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
+romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c
 verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
 postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
 ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
-smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c
+smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c
 endif
diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c
index ec2f1d7..bb2c58d 100644
--- a/src/cpu/x86/tsc/delay_tsc.c
+++ b/src/cpu/x86/tsc/delay_tsc.c
@@ -97,12 +97,16 @@
 	return 0;
 }
 
+#if !IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)
+unsigned long tsc_freq_mhz(void)
+{
+	return calibrate_tsc_with_pit();
+}
+#endif
+
 static unsigned long calibrate_tsc(void)
 {
-	if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))
-		return tsc_freq_mhz();
-	else
-		return calibrate_tsc_with_pit();
+	return tsc_freq_mhz();
 }
 
 void init_timer(void)
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index fdf0012..535a975 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -34,6 +34,6 @@
 ramstage-y += northbridge.c
 ramstage-y += gma.c
 
-smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c
+#smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c
 
 endif

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I405eae497ffd7a3c1854f98f5b592e4f00d70a97
Gerrit-Change-Number: 22101
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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