<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22101">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP/TEST] Use UDELAY_TSC using calibrate_tsc_with_pit<br><br>Change-Id: I405eae497ffd7a3c1854f98f5b592e4f00d70a97<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/model_1067x/Kconfig<br>M src/cpu/intel/model_6ex/Kconfig<br>M src/cpu/intel/model_6fx/Kconfig<br>M src/cpu/x86/tsc/Makefile.inc<br>M src/cpu/x86/tsc/delay_tsc.c<br>M src/northbridge/intel/gm45/Makefile.inc<br>6 files changed, 14 insertions(+), 10 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/22101/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig<br>index 2e154a3..2c2bd7c 100644<br>--- a/src/cpu/intel/model_1067x/Kconfig<br>+++ b/src/cpu/intel/model_1067x/Kconfig<br>@@ -6,7 +6,7 @@<br>     select ARCH_RAMSTAGE_X86_32<br>   select SMP<br>    select SSE2<br>-# select UDELAY_LAPIC<br>+  select UDELAY_TSC<br>     select TSC_SYNC_MFENCE<br>        select SUPPORT_CPU_UCODE_IN_CBFS<br>      select CPU_INTEL_COMMON<br>diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig<br>index 10ebcc7..29563d8 100644<br>--- a/src/cpu/intel/model_6ex/Kconfig<br>+++ b/src/cpu/intel/model_6ex/Kconfig<br>@@ -6,7 +6,7 @@<br>         select ARCH_RAMSTAGE_X86_32<br>   select SMP<br>    select SSE2<br>-  select UDELAY_LAPIC<br>+  select UDELAY_TSC<br>     select AP_IN_SIPI_WAIT<br>        select TSC_SYNC_MFENCE<br>        select SUPPORT_CPU_UCODE_IN_CBFS<br>diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig<br>index 8f05314..20b53a5 100644<br>--- a/src/cpu/intel/model_6fx/Kconfig<br>+++ b/src/cpu/intel/model_6fx/Kconfig<br>@@ -6,7 +6,7 @@<br>        select ARCH_RAMSTAGE_X86_32<br>   select SMP<br>    select SSE2<br>-  select UDELAY_LAPIC<br>+  select UDELAY_TSC<br>     select AP_IN_SIPI_WAIT<br>        select TSC_SYNC_MFENCE<br>        select SUPPORT_CPU_UCODE_IN_CBFS<br>diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc<br>index 9751cac..af131e7 100644<br>--- a/src/cpu/x86/tsc/Makefile.inc<br>+++ b/src/cpu/x86/tsc/Makefile.inc<br>@@ -1,8 +1,8 @@<br> bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c<br> ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c<br>-romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c<br>+romstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c<br> verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c<br> postcar-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c<br> ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)<br>-smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c<br>+smm-$(CONFIG_UDELAY_TSC) += delay_tsc.c<br> endif<br>diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c<br>index ec2f1d7..bb2c58d 100644<br>--- a/src/cpu/x86/tsc/delay_tsc.c<br>+++ b/src/cpu/x86/tsc/delay_tsc.c<br>@@ -97,12 +97,16 @@<br>  return 0;<br> }<br> <br>+#if !IS_ENABLED(CONFIG_TSC_CONSTANT_RATE)<br>+unsigned long tsc_freq_mhz(void)<br>+{<br>+  return calibrate_tsc_with_pit();<br>+}<br>+#endif<br>+<br> static unsigned long calibrate_tsc(void)<br> {<br>-      if (IS_ENABLED(CONFIG_TSC_CONSTANT_RATE))<br>-            return tsc_freq_mhz();<br>-       else<br>-         return calibrate_tsc_with_pit();<br>+     return tsc_freq_mhz();<br> }<br> <br> void init_timer(void)<br>diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc<br>index fdf0012..535a975 100644<br>--- a/src/northbridge/intel/gm45/Makefile.inc<br>+++ b/src/northbridge/intel/gm45/Makefile.inc<br>@@ -34,6 +34,6 @@<br> ramstage-y += northbridge.c<br> ramstage-y += gma.c<br> <br>-smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c<br>+#smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c<br> <br> endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22101">change 22101</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22101"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I405eae497ffd7a3c1854f98f5b592e4f00d70a97 </div>
<div style="display:none"> Gerrit-Change-Number: 22101 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>