[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use newly added pmc_read_pm1_control

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22083


Change subject: soc/intel/skylake: Use newly added pmc_read_pm1_control
......................................................................

soc/intel/skylake: Use newly added pmc_read_pm1_control

BUG=b:67874513

Change-Id: I298065f30647ae9bba8f6a8481bd34eec64f1d8e
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
---
M src/soc/intel/skylake/smihandler.c
1 file changed, 2 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/22083/1

diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c
index daf8e0e..20c4109 100644
--- a/src/soc/intel/skylake/smihandler.c
+++ b/src/soc/intel/skylake/smihandler.c
@@ -140,7 +140,7 @@
 	pmc_disable_smi(SLP_SMI_EN);
 
 	/* Figure out SLP_TYP */
-	reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+	reg32 = pmc_read_pm1_control();
 	printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
 	slp_typ = acpi_sleep_from_pm1(reg32);
 
@@ -213,8 +213,7 @@
 	 * the line above. However, if we entered sleep state S1 and wake
 	 * up again, we will continue to execute code in this function.
 	 */
-	reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT);
-	if (reg32 & SCI_EN) {
+	if (pmc_read_pm1_control() & SCI_EN) {
 		/* The OS is not an ACPI OS, so we set the state to S0 */
 		pmc_disable_pm1_control(SLP_EN | SLP_TYP);
 	}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I298065f30647ae9bba8f6a8481bd34eec64f1d8e
Gerrit-Change-Number: 22083
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan at google.com>
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