[coreboot-gerrit] Change in coreboot[master]: [WIP]sb/intel/i82801ix: fetch initial timestamp in bootblock

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22077


Change subject: [WIP]sb/intel/i82801ix: fetch initial timestamp in bootblock
......................................................................

[WIP]sb/intel/i82801ix: fetch initial timestamp in bootblock

Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/lenovo/t400/romstage.c
M src/mainboard/lenovo/x200/romstage.c
M src/mainboard/roda/rk9/romstage.c
M src/southbridge/intel/i82801ix/bootblock.c
M src/southbridge/intel/i82801ix/early_init.c
5 files changed, 26 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/22077/1

diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
index f5d5dd1..fd3544e 100644
--- a/src/mainboard/lenovo/t400/romstage.c
+++ b/src/mainboard/lenovo/t400/romstage.c
@@ -70,7 +70,7 @@
 	int cbmem_initted;
 	u16 reg16;
 
-	timestamp_init(timestamp_get());
+	timestamp_init(get_initial_timestamp());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* basic northbridge setup, including MMCONF BAR */
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c
index e3f4686..d8ed039 100644
--- a/src/mainboard/lenovo/x200/romstage.c
+++ b/src/mainboard/lenovo/x200/romstage.c
@@ -59,7 +59,7 @@
 	int cbmem_initted;
 	u16 reg16;
 
-	timestamp_init(timestamp_get());
+	timestamp_init(get_initial_timestamp());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* basic northbridge setup, including MMCONF BAR */
diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c
index 9a8e34b..65ff0f8 100644
--- a/src/mainboard/roda/rk9/romstage.c
+++ b/src/mainboard/roda/rk9/romstage.c
@@ -125,7 +125,7 @@
 	int cbmem_initted;
 	u16 reg16;
 
-	timestamp_init(timestamp_get());
+	timestamp_init(get_initial_timestamp());
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* basic northbridge setup, including MMCONF BAR */
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index 6252712..9623fcd 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -15,6 +15,17 @@
 
 #include <arch/io.h>
 
+static void store_initial_timestamp(void)
+{
+	/* We have two 32bit scratchpad registers available:
+	 * D0:F0  0xdc (SKPAD)
+	 * D31:F2 0xd0 (SATA SP)
+	 */
+	tsc_t tsc = rdtsc();
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
+	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
+}
+
 static void enable_spi_prefetch(void)
 {
 	u8 reg8;
@@ -30,5 +41,6 @@
 
 static void bootblock_southbridge_init(void)
 {
+	store_initial_timestamp();
 	enable_spi_prefetch();
 }
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index c40f9b7..7c4dafa 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -15,8 +15,19 @@
  */
 
 #include <arch/io.h>
+#include <timestamp.h>
+#include <cpu/x86/tsc.h>
 #include "i82801ix.h"
 
+uint64_t get_initial_timestamp(void)
+{
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+	return tsc_to_uint64(base_time);
+}
+
 void i82801ix_early_init(void)
 {
 	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b
Gerrit-Change-Number: 22077
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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