<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22077">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]sb/intel/i82801ix: fetch initial timestamp in bootblock<br><br>Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/lenovo/t400/romstage.c<br>M src/mainboard/lenovo/x200/romstage.c<br>M src/mainboard/roda/rk9/romstage.c<br>M src/southbridge/intel/i82801ix/bootblock.c<br>M src/southbridge/intel/i82801ix/early_init.c<br>5 files changed, 26 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/22077/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c<br>index f5d5dd1..fd3544e 100644<br>--- a/src/mainboard/lenovo/t400/romstage.c<br>+++ b/src/mainboard/lenovo/t400/romstage.c<br>@@ -70,7 +70,7 @@<br>     int cbmem_initted;<br>    u16 reg16;<br> <br>-        timestamp_init(timestamp_get());<br>+     timestamp_init(get_initial_timestamp());<br>      timestamp_add_now(TS_START_ROMSTAGE);<br> <br>      /* basic northbridge setup, including MMCONF BAR */<br>diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c<br>index e3f4686..d8ed039 100644<br>--- a/src/mainboard/lenovo/x200/romstage.c<br>+++ b/src/mainboard/lenovo/x200/romstage.c<br>@@ -59,7 +59,7 @@<br>       int cbmem_initted;<br>    u16 reg16;<br> <br>-        timestamp_init(timestamp_get());<br>+     timestamp_init(get_initial_timestamp());<br>      timestamp_add_now(TS_START_ROMSTAGE);<br> <br>      /* basic northbridge setup, including MMCONF BAR */<br>diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c<br>index 9a8e34b..65ff0f8 100644<br>--- a/src/mainboard/roda/rk9/romstage.c<br>+++ b/src/mainboard/roda/rk9/romstage.c<br>@@ -125,7 +125,7 @@<br>         int cbmem_initted;<br>    u16 reg16;<br> <br>-        timestamp_init(timestamp_get());<br>+     timestamp_init(get_initial_timestamp());<br>      timestamp_add_now(TS_START_ROMSTAGE);<br> <br>      /* basic northbridge setup, including MMCONF BAR */<br>diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c<br>index 6252712..9623fcd 100644<br>--- a/src/southbridge/intel/i82801ix/bootblock.c<br>+++ b/src/southbridge/intel/i82801ix/bootblock.c<br>@@ -15,6 +15,17 @@<br> <br> #include <arch/io.h><br> <br>+static void store_initial_timestamp(void)<br>+{<br>+  /* We have two 32bit scratchpad registers available:<br>+  * D0:F0  0xdc (SKPAD)<br>+        * D31:F2 0xd0 (SATA SP)<br>+      */<br>+  tsc_t tsc = rdtsc();<br>+ pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);<br>+       pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);<br>+}<br>+<br> static void enable_spi_prefetch(void)<br> {<br>     u8 reg8;<br>@@ -30,5 +41,6 @@<br> <br> static void bootblock_southbridge_init(void)<br> {<br>+    store_initial_timestamp();<br>    enable_spi_prefetch();<br> }<br>diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c<br>index c40f9b7..7c4dafa 100644<br>--- a/src/southbridge/intel/i82801ix/early_init.c<br>+++ b/src/southbridge/intel/i82801ix/early_init.c<br>@@ -15,8 +15,19 @@<br>  */<br> <br> #include <arch/io.h><br>+#include <timestamp.h><br>+#include <cpu/x86/tsc.h><br> #include "i82801ix.h"<br> <br>+uint64_t get_initial_timestamp(void)<br>+{<br>+    tsc_t base_time = {<br>+          .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),<br>+          .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)<br>+   };<br>+   return tsc_to_uint64(base_time);<br>+}<br>+<br> void i82801ix_early_init(void)<br> {<br>  const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);<br></pre><p>To view, visit <a href="https://review.coreboot.org/22077">change 22077</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22077"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b </div>
<div style="display:none"> Gerrit-Change-Number: 22077 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>