[coreboot-gerrit] Change in coreboot[master]: security/vboot: Fix vboot2 headers

Philipp Deppenwiese (Code Review) gerrit at coreboot.org
Tue Oct 17 19:35:26 CEST 2017 

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/22075


Change subject: security/vboot: Fix vboot2 headers
......................................................................

security/vboot: Fix vboot2 headers

Change-Id: Ic230f6a96e432d45ff5946fed02f84fbbfcf63ed
Signed-off-by: Philipp Deppenwiese <zaolin at das-labor.org>
---
M src/device/pci_device.c
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/pc80/rtc/mc146818rtc.c
M src/ec/google/chromeec/ec.c
M src/lib/coreboot_table.c
M src/mainboard/google/veyron_rialto/mainboard.c
M src/mainboard/intel/galileo/vboot.c
M src/northbridge/intel/haswell/raminit.c
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/soc/amd/stoneyridge/pmutil.c
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/baytrail/pmutil.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/braswell/pmutil.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/pmutil.c
M src/soc/intel/cannonlake/pmc.c
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/common/block/pmc/pmclib.c
M src/soc/intel/common/mrc_cache.c
M src/soc/intel/skylake/igd.c
M src/soc/intel/skylake/pmutil.c
M src/soc/intel/skylake/romstage/power_state.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/southbridge/intel/bd82x6x/early_pch_common.c
M src/southbridge/intel/lynxpoint/pmutil.c
M src/vendorcode/google/chromeos/acpi/chromeos.asl
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/cr50_enable_update.c
M src/vendorcode/google/chromeos/elog.c
M src/vendorcode/google/chromeos/gnvs.c
32 files changed, 37 insertions(+), 37 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/22075/1

diff --git a/src/device/pci_device.c b/src/device/pci_device.c
index f43de45..3d23671 100644
--- a/src/device/pci_device.c
+++ b/src/device/pci_device.c
@@ -47,7 +47,7 @@
 #include <device/pciexp.h>
 #include <device/hypertransport.h>
 #include <pc80/i8259.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 
 u8 pci_moving_config8(struct device *dev, unsigned int reg)
 {
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 5b6ec9e..2bdac0a 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -23,7 +23,7 @@
 #include <reset.h>
 #include <string.h>
 #include <timestamp.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 
 void raminit(struct romstage_params *params)
 {
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index b08ee1e..0aea1ad 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -32,7 +32,7 @@
 #include <symbols.h>
 #include <timestamp.h>
 #include <tpm_lite/tlcl.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 #include <vb2_api.h>
 
 static void mrc_cache_update_tpm_hash(const uint8_t *data, size_t size)
diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c
index 830ff09..928b403 100644
--- a/src/drivers/pc80/rtc/mc146818rtc.c
+++ b/src/drivers/pc80/rtc/mc146818rtc.c
@@ -26,8 +26,8 @@
 #include <rtc.h>
 #include <string.h>
 #include <cbfs.h>
-#include <vboot/vbnv.h>
-#include <vboot/vbnv_layout.h>
+#include <security/vboot/vbnv.h>
+#include <security/vboot/vbnv_layout.h>
 
 /* There's no way around this include guard. option_table.h is autogenerated */
 #if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index 639719a..f8fe7ba 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -26,7 +26,7 @@
 #include <reset.h>
 #include <rtc.h>
 #include <stdlib.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 
 #include "chip.h"
 #include "ec.h"
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 131dde8..f152f34 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -32,7 +32,7 @@
 #include <cbmem.h>
 #include <bootmem.h>
 #include <spi_flash.h>
-#include <vboot/vbnv_layout.h>
+#include <security/vboot/vbnv_layout.h>
 #if IS_ENABLED(CONFIG_USE_OPTION_TABLE)
 #include <option_table.h>
 #endif
diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c
index 91bf46a..b6b25be 100644
--- a/src/mainboard/google/veyron_rialto/mainboard.c
+++ b/src/mainboard/google/veyron_rialto/mainboard.c
@@ -34,7 +34,7 @@
 #include <symbols.h>
 #include <vbe.h>
 #include <vendorcode/google/chromeos/chromeos.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 
 #include "board.h"
 
diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c
index b0fa2f2..469ec4e 100644
--- a/src/mainboard/intel/galileo/vboot.c
+++ b/src/mainboard/intel/galileo/vboot.c
@@ -24,8 +24,8 @@
 #include "gen1.h"
 #include "gen2.h"
 #include <spi_flash.h>
-#include <vboot/vboot_common.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vboot_common.h>
+#include <security/vboot/vbnv.h>
 
 int clear_recovery_mode_switch(void)
 {
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index e48cca9..f17a374 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -28,7 +28,7 @@
 #include <device/dram/ddr3.h>
 #include <smbios.h>
 #include <spd.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 #include "raminit.h"
 #include "pei_data.h"
 #include "haswell.h"
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 7145841..901a083 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -31,7 +31,7 @@
 #include "raminit.h"
 #include "pei_data.h"
 #include "sandybridge.h"
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 
 /* Management Engine is in the southbridge */
 #include "southbridge/intel/bd82x6x/me.h"
diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c
index 5bbea2a..89d3640 100644
--- a/src/soc/amd/stoneyridge/pmutil.c
+++ b/src/soc/amd/stoneyridge/pmutil.c
@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 
 int vbnv_cmos_failed(void)
 {
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index b9ed5b4..94ebfc4 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -34,7 +34,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <timer.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 #include "chip.h"
 
 static uintptr_t read_pmc_mmio_bar(void)
diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c
index fbdea8f..ee99917 100644
--- a/src/soc/intel/baytrail/pmutil.c
+++ b/src/soc/intel/baytrail/pmutil.c
@@ -22,7 +22,7 @@
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/pmc.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 
 #if defined(__SIMPLE_DEVICE__)
 
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 44e0923..b577a35 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -30,7 +30,7 @@
 #include <soc/romstage.h>
 #include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 
 static void reset_system(void)
 {
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index b5f284f..18e655c 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -23,7 +23,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <stdint.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 
 #if defined(__SIMPLE_DEVICE__)
 
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index fa1340f..0b6e416 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -30,7 +30,7 @@
 #include <soc/ramstage.h>
 #include <soc/systemagent.h>
 #include <soc/intel/broadwell/chip.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 #include <soc/igd.h>
 
 #define GT_RETRY		1000
diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c
index 0edcd8c..25624cc 100644
--- a/src/soc/intel/broadwell/pmutil.c
+++ b/src/soc/intel/broadwell/pmutil.c
@@ -28,7 +28,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/gpio.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 
 /* Print status bits with descriptive names */
 static void print_status_bits(u32 status, const char *bit_names[])
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c
index e9972a6..a0d816e 100644
--- a/src/soc/intel/cannonlake/pmc.c
+++ b/src/soc/intel/cannonlake/pmc.c
@@ -36,8 +36,8 @@
 #include <cpu/x86/smm.h>
 #include <soc/pcr_ids.h>
 #include <soc/ramstage.h>
-#include <vboot/vbnv.h>
-#include <vboot/vbnv_layout.h>
+#include <security/vboot/vbnv.h>
+#include <security/vboot/vbnv_layout.h>
 
 static void pch_pmc_add_mmio_resources(device_t dev)
 {
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index ed2e3b0..b3fad88 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -40,7 +40,7 @@
 #include <soc/pm.h>
 #include <soc/smbus.h>
 #include <timer.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 #include "chip.h"
 
 /*
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index b8ec17d..cbe7572 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -23,7 +23,7 @@
 #include <soc/pm.h>
 #include <string.h>
 #include <timer.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 
 static struct chipset_power_state power_state CAR_GLOBAL;
 
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index a4f3d32..8720c9d 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -23,7 +23,7 @@
 #include <fmap.h>
 #include <ip_checksum.h>
 #include <region_file.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 
 #include "mrc_cache.h"
 #include "nvm.h"
diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c
index e1d5bff..545030f 100644
--- a/src/soc/intel/skylake/igd.c
+++ b/src/soc/intel/skylake/igd.c
@@ -32,7 +32,7 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 #include <string.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 
 uintptr_t fsp_soc_get_igd_bar(void)
 {
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 19370e1..494850c 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -39,7 +39,7 @@
 #include <soc/pmc.h>
 #include <soc/smbus.h>
 #include <timer.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 #include "chip.h"
 
 /*
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index 3eae936..f816bf6 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -31,7 +31,7 @@
 #include <soc/pm.h>
 #include <soc/pmc.h>
 #include <soc/romstage.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 #include <intelblocks/pmclib.h>
 
 /* Return 0, 3, or 5 to indicate the previous sleep state. */
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index d4a5e34..d6ec41f 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -35,7 +35,7 @@
 #include <soc/romstage.h>
 #include <string.h>
 #include <timestamp.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 
 #define FSP_SMBIOS_MEMORY_INFO_GUID	\
 {	\
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c
index f812247..a41c2f3 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_common.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_common.c
@@ -22,7 +22,7 @@
 #include <arch/acpi.h>
 #include <console/console.h>
 #include <rules.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 
 #if ENV_ROMSTAGE
 uint64_t get_initial_timestamp(void)
diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c
index 55fe403..00a6e65 100644
--- a/src/southbridge/intel/lynxpoint/pmutil.c
+++ b/src/southbridge/intel/lynxpoint/pmutil.c
@@ -24,7 +24,7 @@
 #include <device/pci.h>
 #include <device/pci_def.h>
 #include <console/console.h>
-#include <vboot/vbnv.h>
+#include <security/vboot/vbnv.h>
 #include "pch.h"
 
 #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)
diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl
index 44d9d15..d813b22 100644
--- a/src/vendorcode/google/chromeos/acpi/chromeos.asl
+++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl
@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <vboot/vbnv_layout.h>
+#include <security/vboot/vbnv_layout.h>
 
 #if IS_ENABLED(CONFIG_CHROMEOS)
 
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index a739ab7..df61596 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -21,8 +21,8 @@
 #include <bootmode.h>
 #include <device/device.h>
 #include <rules.h>
-#include <vboot/misc.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/misc.h>
+#include <security/vboot/vboot_common.h>
 
 #if IS_ENABLED(CONFIG_CHROMEOS)
 /* functions implemented in watchdog.c */
diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c
index e962f19..bad3513 100644
--- a/src/vendorcode/google/chromeos/cr50_enable_update.c
+++ b/src/vendorcode/google/chromeos/cr50_enable_update.c
@@ -20,7 +20,7 @@
 #include <halt.h>
 #include <tpm_lite/tlcl.h>
 #include <vb2_api.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 
 static void enable_update(void *unused)
 {
diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c
index f16f0ad..fbbfd16 100644
--- a/src/vendorcode/google/chromeos/elog.c
+++ b/src/vendorcode/google/chromeos/elog.c
@@ -16,7 +16,7 @@
 #include <bootstate.h>
 #include <console/console.h>
 #include <elog.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vboot_common.h>
 
 #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
 #include <arch/acpi.h>
diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c
index 8a5cc64..a278b41 100644
--- a/src/vendorcode/google/chromeos/gnvs.c
+++ b/src/vendorcode/google/chromeos/gnvs.c
@@ -20,8 +20,8 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <elog.h>
-#include <vboot/vbnv.h>
-#include <vboot/vboot_common.h>
+#include <security/vboot/vbnv.h>
+#include <security/vboot/vboot_common.h>
 #include <vboot_struct.h>
 
 #include "chromeos.h"

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic230f6a96e432d45ff5946fed02f84fbbfcf63ed
Gerrit-Change-Number: 22075
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
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