<p>Philipp Deppenwiese has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22075">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">security/vboot: Fix vboot2 headers<br><br>Change-Id: Ic230f6a96e432d45ff5946fed02f84fbbfcf63ed<br>Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org><br>---<br>M src/device/pci_device.c<br>M src/drivers/intel/fsp1_1/raminit.c<br>M src/drivers/intel/fsp2_0/memory_init.c<br>M src/drivers/pc80/rtc/mc146818rtc.c<br>M src/ec/google/chromeec/ec.c<br>M src/lib/coreboot_table.c<br>M src/mainboard/google/veyron_rialto/mainboard.c<br>M src/mainboard/intel/galileo/vboot.c<br>M src/northbridge/intel/haswell/raminit.c<br>M src/northbridge/intel/sandybridge/raminit_mrc.c<br>M src/soc/amd/stoneyridge/pmutil.c<br>M src/soc/intel/apollolake/pmutil.c<br>M src/soc/intel/baytrail/pmutil.c<br>M src/soc/intel/baytrail/romstage/raminit.c<br>M src/soc/intel/braswell/pmutil.c<br>M src/soc/intel/broadwell/igd.c<br>M src/soc/intel/broadwell/pmutil.c<br>M src/soc/intel/cannonlake/pmc.c<br>M src/soc/intel/cannonlake/pmutil.c<br>M src/soc/intel/common/block/pmc/pmclib.c<br>M src/soc/intel/common/mrc_cache.c<br>M src/soc/intel/skylake/igd.c<br>M src/soc/intel/skylake/pmutil.c<br>M src/soc/intel/skylake/romstage/power_state.c<br>M src/soc/intel/skylake/romstage/romstage_fsp20.c<br>M src/southbridge/intel/bd82x6x/early_pch_common.c<br>M src/southbridge/intel/lynxpoint/pmutil.c<br>M src/vendorcode/google/chromeos/acpi/chromeos.asl<br>M src/vendorcode/google/chromeos/chromeos.h<br>M src/vendorcode/google/chromeos/cr50_enable_update.c<br>M src/vendorcode/google/chromeos/elog.c<br>M src/vendorcode/google/chromeos/gnvs.c<br>32 files changed, 37 insertions(+), 37 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/22075/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/device/pci_device.c b/src/device/pci_device.c<br>index f43de45..3d23671 100644<br>--- a/src/device/pci_device.c<br>+++ b/src/device/pci_device.c<br>@@ -47,7 +47,7 @@<br> #include <device/pciexp.h><br> #include <device/hypertransport.h><br> #include <pc80/i8259.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> <br> u8 pci_moving_config8(struct device *dev, unsigned int reg)<br> {<br>diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c<br>index 5b6ec9e..2bdac0a 100644<br>--- a/src/drivers/intel/fsp1_1/raminit.c<br>+++ b/src/drivers/intel/fsp1_1/raminit.c<br>@@ -23,7 +23,7 @@<br> #include <reset.h><br> #include <string.h><br> #include <timestamp.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> <br> void raminit(struct romstage_params *params)<br> {<br>diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c<br>index b08ee1e..0aea1ad 100644<br>--- a/src/drivers/intel/fsp2_0/memory_init.c<br>+++ b/src/drivers/intel/fsp2_0/memory_init.c<br>@@ -32,7 +32,7 @@<br> #include <symbols.h><br> #include <timestamp.h><br> #include <tpm_lite/tlcl.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> #include <vb2_api.h><br> <br> static void mrc_cache_update_tpm_hash(const uint8_t *data, size_t size)<br>diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c<br>index 830ff09..928b403 100644<br>--- a/src/drivers/pc80/rtc/mc146818rtc.c<br>+++ b/src/drivers/pc80/rtc/mc146818rtc.c<br>@@ -26,8 +26,8 @@<br> #include <rtc.h><br> #include <string.h><br> #include <cbfs.h><br>-#include <vboot/vbnv.h><br>-#include <vboot/vbnv_layout.h><br>+#include <security/vboot/vbnv.h><br>+#include <security/vboot/vbnv_layout.h><br> <br> /* There's no way around this include guard. option_table.h is autogenerated */<br> #if IS_ENABLED(CONFIG_USE_OPTION_TABLE)<br>diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c<br>index 639719a..f8fe7ba 100644<br>--- a/src/ec/google/chromeec/ec.c<br>+++ b/src/ec/google/chromeec/ec.c<br>@@ -26,7 +26,7 @@<br> #include <reset.h><br> #include <rtc.h><br> #include <stdlib.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> <br> #include "chip.h"<br> #include "ec.h"<br>diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c<br>index 131dde8..f152f34 100644<br>--- a/src/lib/coreboot_table.c<br>+++ b/src/lib/coreboot_table.c<br>@@ -32,7 +32,7 @@<br> #include <cbmem.h><br> #include <bootmem.h><br> #include <spi_flash.h><br>-#include <vboot/vbnv_layout.h><br>+#include <security/vboot/vbnv_layout.h><br> #if IS_ENABLED(CONFIG_USE_OPTION_TABLE)<br> #include <option_table.h><br> #endif<br>diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c<br>index 91bf46a..b6b25be 100644<br>--- a/src/mainboard/google/veyron_rialto/mainboard.c<br>+++ b/src/mainboard/google/veyron_rialto/mainboard.c<br>@@ -34,7 +34,7 @@<br> #include <symbols.h><br> #include <vbe.h><br> #include <vendorcode/google/chromeos/chromeos.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> <br> #include "board.h"<br> <br>diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c<br>index b0fa2f2..469ec4e 100644<br>--- a/src/mainboard/intel/galileo/vboot.c<br>+++ b/src/mainboard/intel/galileo/vboot.c<br>@@ -24,8 +24,8 @@<br> #include "gen1.h"<br> #include "gen2.h"<br> #include <spi_flash.h><br>-#include <vboot/vboot_common.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vboot_common.h><br>+#include <security/vboot/vbnv.h><br> <br> int clear_recovery_mode_switch(void)<br> {<br>diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c<br>index e48cca9..f17a374 100644<br>--- a/src/northbridge/intel/haswell/raminit.c<br>+++ b/src/northbridge/intel/haswell/raminit.c<br>@@ -28,7 +28,7 @@<br> #include <device/dram/ddr3.h><br> #include <smbios.h><br> #include <spd.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> #include "raminit.h"<br> #include "pei_data.h"<br> #include "haswell.h"<br>diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c<br>index 7145841..901a083 100644<br>--- a/src/northbridge/intel/sandybridge/raminit_mrc.c<br>+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c<br>@@ -31,7 +31,7 @@<br> #include "raminit.h"<br> #include "pei_data.h"<br> #include "sandybridge.h"<br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> <br> /* Management Engine is in the southbridge */<br> #include "southbridge/intel/bd82x6x/me.h"<br>diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c<br>index 5bbea2a..89d3640 100644<br>--- a/src/soc/amd/stoneyridge/pmutil.c<br>+++ b/src/soc/amd/stoneyridge/pmutil.c<br>@@ -13,7 +13,7 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> <br> int vbnv_cmos_failed(void)<br> {<br>diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c<br>index b9ed5b4..94ebfc4 100644<br>--- a/src/soc/intel/apollolake/pmutil.c<br>+++ b/src/soc/intel/apollolake/pmutil.c<br>@@ -34,7 +34,7 @@<br> #include <soc/pci_devs.h><br> #include <soc/pm.h><br> #include <timer.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> #include "chip.h"<br> <br> static uintptr_t read_pmc_mmio_bar(void)<br>diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c<br>index fbdea8f..ee99917 100644<br>--- a/src/soc/intel/baytrail/pmutil.c<br>+++ b/src/soc/intel/baytrail/pmutil.c<br>@@ -22,7 +22,7 @@<br> #include <soc/lpc.h><br> #include <soc/pci_devs.h><br> #include <soc/pmc.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> <br> #if defined(__SIMPLE_DEVICE__)<br> <br>diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c<br>index 44e0923..b577a35 100644<br>--- a/src/soc/intel/baytrail/romstage/raminit.c<br>+++ b/src/soc/intel/baytrail/romstage/raminit.c<br>@@ -30,7 +30,7 @@<br> #include <soc/romstage.h><br> #include <ec/google/chromeec/ec.h><br> #include <ec/google/chromeec/ec_commands.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> <br> static void reset_system(void)<br> {<br>diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c<br>index b5f284f..18e655c 100644<br>--- a/src/soc/intel/braswell/pmutil.c<br>+++ b/src/soc/intel/braswell/pmutil.c<br>@@ -23,7 +23,7 @@<br> #include <soc/pci_devs.h><br> #include <soc/pm.h><br> #include <stdint.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> <br> #if defined(__SIMPLE_DEVICE__)<br> <br>diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c<br>index fa1340f..0b6e416 100644<br>--- a/src/soc/intel/broadwell/igd.c<br>+++ b/src/soc/intel/broadwell/igd.c<br>@@ -30,7 +30,7 @@<br> #include <soc/ramstage.h><br> #include <soc/systemagent.h><br> #include <soc/intel/broadwell/chip.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> #include <soc/igd.h><br> <br> #define GT_RETRY           1000<br>diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c<br>index 0edcd8c..25624cc 100644<br>--- a/src/soc/intel/broadwell/pmutil.c<br>+++ b/src/soc/intel/broadwell/pmutil.c<br>@@ -28,7 +28,7 @@<br> #include <soc/pci_devs.h><br> #include <soc/pm.h><br> #include <soc/gpio.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> <br> /* Print status bits with descriptive names */<br> static void print_status_bits(u32 status, const char *bit_names[])<br>diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c<br>index e9972a6..a0d816e 100644<br>--- a/src/soc/intel/cannonlake/pmc.c<br>+++ b/src/soc/intel/cannonlake/pmc.c<br>@@ -36,8 +36,8 @@<br> #include <cpu/x86/smm.h><br> #include <soc/pcr_ids.h><br> #include <soc/ramstage.h><br>-#include <vboot/vbnv.h><br>-#include <vboot/vbnv_layout.h><br>+#include <security/vboot/vbnv.h><br>+#include <security/vboot/vbnv_layout.h><br> <br> static void pch_pmc_add_mmio_resources(device_t dev)<br> {<br>diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c<br>index ed2e3b0..b3fad88 100644<br>--- a/src/soc/intel/cannonlake/pmutil.c<br>+++ b/src/soc/intel/cannonlake/pmutil.c<br>@@ -40,7 +40,7 @@<br> #include <soc/pm.h><br> #include <soc/smbus.h><br> #include <timer.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> #include "chip.h"<br> <br> /*<br>diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c<br>index b8ec17d..cbe7572 100644<br>--- a/src/soc/intel/common/block/pmc/pmclib.c<br>+++ b/src/soc/intel/common/block/pmc/pmclib.c<br>@@ -23,7 +23,7 @@<br> #include <soc/pm.h><br> #include <string.h><br> #include <timer.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> <br> static struct chipset_power_state power_state CAR_GLOBAL;<br> <br>diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c<br>index a4f3d32..8720c9d 100644<br>--- a/src/soc/intel/common/mrc_cache.c<br>+++ b/src/soc/intel/common/mrc_cache.c<br>@@ -23,7 +23,7 @@<br> #include <fmap.h><br> #include <ip_checksum.h><br> #include <region_file.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> <br> #include "mrc_cache.h"<br> #include "nvm.h"<br>diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c<br>index e1d5bff..545030f 100644<br>--- a/src/soc/intel/skylake/igd.c<br>+++ b/src/soc/intel/skylake/igd.c<br>@@ -32,7 +32,7 @@<br> #include <soc/systemagent.h><br> #include <stdlib.h><br> #include <string.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> <br> uintptr_t fsp_soc_get_igd_bar(void)<br> {<br>diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c<br>index 19370e1..494850c 100644<br>--- a/src/soc/intel/skylake/pmutil.c<br>+++ b/src/soc/intel/skylake/pmutil.c<br>@@ -39,7 +39,7 @@<br> #include <soc/pmc.h><br> #include <soc/smbus.h><br> #include <timer.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> #include "chip.h"<br> <br> /*<br>diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c<br>index 3eae936..f816bf6 100644<br>--- a/src/soc/intel/skylake/romstage/power_state.c<br>+++ b/src/soc/intel/skylake/romstage/power_state.c<br>@@ -31,7 +31,7 @@<br> #include <soc/pm.h><br> #include <soc/pmc.h><br> #include <soc/romstage.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> #include <intelblocks/pmclib.h><br> <br> /* Return 0, 3, or 5 to indicate the previous sleep state. */<br>diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c<br>index d4a5e34..d6ec41f 100644<br>--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c<br>+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c<br>@@ -35,7 +35,7 @@<br> #include <soc/romstage.h><br> #include <string.h><br> #include <timestamp.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> <br> #define FSP_SMBIOS_MEMORY_INFO_GUID      \<br> {   \<br>diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c<br>index f812247..a41c2f3 100644<br>--- a/src/southbridge/intel/bd82x6x/early_pch_common.c<br>+++ b/src/southbridge/intel/bd82x6x/early_pch_common.c<br>@@ -22,7 +22,7 @@<br> #include <arch/acpi.h><br> #include <console/console.h><br> #include <rules.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> <br> #if ENV_ROMSTAGE<br> uint64_t get_initial_timestamp(void)<br>diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c<br>index 55fe403..00a6e65 100644<br>--- a/src/southbridge/intel/lynxpoint/pmutil.c<br>+++ b/src/southbridge/intel/lynxpoint/pmutil.c<br>@@ -24,7 +24,7 @@<br> #include <device/pci.h><br> #include <device/pci_def.h><br> #include <console/console.h><br>-#include <vboot/vbnv.h><br>+#include <security/vboot/vbnv.h><br> #include "pch.h"<br> <br> #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP)<br>diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl<br>index 44d9d15..d813b22 100644<br>--- a/src/vendorcode/google/chromeos/acpi/chromeos.asl<br>+++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl<br>@@ -13,7 +13,7 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#include <vboot/vbnv_layout.h><br>+#include <security/vboot/vbnv_layout.h><br> <br> #if IS_ENABLED(CONFIG_CHROMEOS)<br> <br>diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h<br>index a739ab7..df61596 100644<br>--- a/src/vendorcode/google/chromeos/chromeos.h<br>+++ b/src/vendorcode/google/chromeos/chromeos.h<br>@@ -21,8 +21,8 @@<br> #include <bootmode.h><br> #include <device/device.h><br> #include <rules.h><br>-#include <vboot/misc.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/misc.h><br>+#include <security/vboot/vboot_common.h><br> <br> #if IS_ENABLED(CONFIG_CHROMEOS)<br> /* functions implemented in watchdog.c */<br>diff --git a/src/vendorcode/google/chromeos/cr50_enable_update.c b/src/vendorcode/google/chromeos/cr50_enable_update.c<br>index e962f19..bad3513 100644<br>--- a/src/vendorcode/google/chromeos/cr50_enable_update.c<br>+++ b/src/vendorcode/google/chromeos/cr50_enable_update.c<br>@@ -20,7 +20,7 @@<br> #include <halt.h><br> #include <tpm_lite/tlcl.h><br> #include <vb2_api.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> <br> static void enable_update(void *unused)<br> {<br>diff --git a/src/vendorcode/google/chromeos/elog.c b/src/vendorcode/google/chromeos/elog.c<br>index f16f0ad..fbbfd16 100644<br>--- a/src/vendorcode/google/chromeos/elog.c<br>+++ b/src/vendorcode/google/chromeos/elog.c<br>@@ -16,7 +16,7 @@<br> #include <bootstate.h><br> #include <console/console.h><br> #include <elog.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vboot_common.h><br> <br> #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)<br> #include <arch/acpi.h><br>diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c<br>index 8a5cc64..a278b41 100644<br>--- a/src/vendorcode/google/chromeos/gnvs.c<br>+++ b/src/vendorcode/google/chromeos/gnvs.c<br>@@ -20,8 +20,8 @@<br> #include <cbmem.h><br> #include <console/console.h><br> #include <elog.h><br>-#include <vboot/vbnv.h><br>-#include <vboot/vboot_common.h><br>+#include <security/vboot/vbnv.h><br>+#include <security/vboot/vboot_common.h><br> #include <vboot_struct.h><br> <br> #include "chromeos.h"<br></pre><p>To view, visit <a href="https://review.coreboot.org/22075">change 22075</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22075"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic230f6a96e432d45ff5946fed02f84fbbfcf63ed </div>
<div style="display:none"> Gerrit-Change-Number: 22075 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>