[coreboot-gerrit] Change in coreboot[master]: intel/common/smbus: increase spd read performance

[Kane Chen (Code Review)]

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/22072


Change subject: intel/common/smbus: increase spd read performance
......................................................................

intel/common/smbus: increase spd read performance

This change increases the spd read performance by
using smbus word access.

BUG=b:67021853
TEST=boot to os and find 80~100 ms boot time improvement

Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14
Signed-off-by: Kane Chen <kane.chen at intel.com>
---
M src/include/device/early_smbus.h
M src/lib/spd_bin.c
M src/soc/intel/common/block/smbus/smbus_early.c
M src/soc/intel/common/block/smbus/smbuslib.c
M src/soc/intel/common/block/smbus/smbuslib.h
5 files changed, 62 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/22072/1

diff --git a/src/include/device/early_smbus.h b/src/include/device/early_smbus.h
index e3fe4fe..c907396 100644
--- a/src/include/device/early_smbus.h
+++ b/src/include/device/early_smbus.h
@@ -63,6 +63,7 @@
 int smbus_print_error(u32 smbus_dev, u8 host_status, int loops);
 int smbus_is_busy(u32 smbus_dev);
 int smbus_wait_until_ready(u32 smbus_dev);
+u16 smbus_read_word(u32 smbus_dev, u8 addr, u8 offset);
 u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset);
 u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value);
 void smbus_delay(void);
diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c
index b5ab9b7..36a8781 100644
--- a/src/lib/spd_bin.c
+++ b/src/lib/spd_bin.c
@@ -136,15 +136,18 @@
 		return;
 	}
 
-	for (i = 0; i < SPD_PAGE_LEN; i++)
-		spd[i] = smbus_read_byte(0, addr, i);
+	for (i = 0; i < SPD_PAGE_LEN; i += 2)
+		((u16*)spd)[i / 2] = smbus_read_word(0, addr, i);
+
 	/* Check if module is DDR4, DDR4 spd is 512 byte. */
 	if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 &&
 		CONFIG_DIMM_SPD_SIZE >= SPD_DRAM_DDR4) {
 		/* Switch to page 1 */
 		smbus_write_byte(0, SPD_PAGE_1, 0, 0);
-		for (i = 0; i < SPD_PAGE_LEN; i++)
-			spd[i+SPD_PAGE_LEN] = smbus_read_byte(0, addr, i);
+		for (i = 0; i < SPD_PAGE_LEN; i += 2) {
+			((u16*)spd)[(i + SPD_PAGE_LEN) / 2] = \
+					smbus_read_word(0, addr, i);
+		}
 		/* Restore to page 0 */
 		smbus_write_byte(0, SPD_PAGE_0, 0, 0);
 	}
diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c
index e0c4d9c..9e6afc4 100644
--- a/src/soc/intel/common/block/smbus/smbus_early.c
+++ b/src/soc/intel/common/block/smbus/smbus_early.c
@@ -36,6 +36,11 @@
 	REG_SCRIPT_END,
 };
 
+u16 smbus_read_word(u32 smbus_dev, u8 addr, u8 offset)
+{
+	return smbus_read16(SMBUS_IO_BASE, addr, offset);
+}
+
 u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)
 {
 	return smbus_read8(SMBUS_IO_BASE, addr, offset);
diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c
index 27b4ad5..8567a27 100644
--- a/src/soc/intel/common/block/smbus/smbuslib.c
+++ b/src/soc/intel/common/block/smbus/smbuslib.c
@@ -135,3 +135,50 @@
 
 	return 0;
 }
+
+int smbus_read16(unsigned int smbus_base, unsigned int device,
+	unsigned int address)
+{
+	unsigned char global_status_register;
+	unsigned short data;
+
+	if (smbus_wait_till_ready(smbus_base) < 0)
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+
+	/* Setup transaction */
+	/* Disable interrupts */
+	outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+	/* Set the device I'm talking to */
+	outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(address & 0xff, smbus_base + SMBHSTCMD);
+	/* Set up for a byte data read */
+	outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x3 << 2),
+		(smbus_base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+	/* Clear the data byte... */
+	outb(0, smbus_base + SMBHSTDAT0);
+
+	/* Start the command */
+	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+	     smbus_base + SMBHSTCTL);
+
+	/* Poll for transaction completion */
+	if (smbus_wait_till_done(smbus_base) < 0)
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+
+	global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+	/* Ignore the "In Use" status... */
+	global_status_register &= ~(3 << 5);
+
+	/* Read results of transaction */
+	data = inw(smbus_base + SMBHSTDAT0);
+
+	if (global_status_register != (1 << 1))
+		return SMBUS_ERROR;
+
+	return data;
+}
diff --git a/src/soc/intel/common/block/smbus/smbuslib.h b/src/soc/intel/common/block/smbus/smbuslib.h
index b5be6ca..05dafe9 100644
--- a/src/soc/intel/common/block/smbus/smbuslib.h
+++ b/src/soc/intel/common/block/smbus/smbuslib.h
@@ -34,5 +34,7 @@
 		unsigned int address);
 int smbus_write8(unsigned int smbus_base, unsigned int device,
 		unsigned int address, unsigned int data);
+int smbus_read16(unsigned int smbus_base, unsigned int device,
+		unsigned int address);
 
 #endif	/* SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H */

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14
Gerrit-Change-Number: 22072
Gerrit-PatchSet: 1
Gerrit-Owner: Kane Chen <kane.chen at intel.com>
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