<p>Kane Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22072">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/common/smbus: increase spd read performance<br><br>This change increases the spd read performance by<br>using smbus word access.<br><br>BUG=b:67021853<br>TEST=boot to os and find 80~100 ms boot time improvement<br><br>Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14<br>Signed-off-by: Kane Chen <kane.chen@intel.com><br>---<br>M src/include/device/early_smbus.h<br>M src/lib/spd_bin.c<br>M src/soc/intel/common/block/smbus/smbus_early.c<br>M src/soc/intel/common/block/smbus/smbuslib.c<br>M src/soc/intel/common/block/smbus/smbuslib.h<br>5 files changed, 62 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/22072/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/include/device/early_smbus.h b/src/include/device/early_smbus.h<br>index e3fe4fe..c907396 100644<br>--- a/src/include/device/early_smbus.h<br>+++ b/src/include/device/early_smbus.h<br>@@ -63,6 +63,7 @@<br> int smbus_print_error(u32 smbus_dev, u8 host_status, int loops);<br> int smbus_is_busy(u32 smbus_dev);<br> int smbus_wait_until_ready(u32 smbus_dev);<br>+u16 smbus_read_word(u32 smbus_dev, u8 addr, u8 offset);<br> u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset);<br> u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value);<br> void smbus_delay(void);<br>diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c<br>index b5ab9b7..36a8781 100644<br>--- a/src/lib/spd_bin.c<br>+++ b/src/lib/spd_bin.c<br>@@ -136,15 +136,18 @@<br> return;<br> }<br> <br>- for (i = 0; i < SPD_PAGE_LEN; i++)<br>- spd[i] = smbus_read_byte(0, addr, i);<br>+ for (i = 0; i < SPD_PAGE_LEN; i += 2)<br>+ ((u16*)spd)[i / 2] = smbus_read_word(0, addr, i);<br>+<br> /* Check if module is DDR4, DDR4 spd is 512 byte. */<br> if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 &&<br> CONFIG_DIMM_SPD_SIZE >= SPD_DRAM_DDR4) {<br> /* Switch to page 1 */<br> smbus_write_byte(0, SPD_PAGE_1, 0, 0);<br>- for (i = 0; i < SPD_PAGE_LEN; i++)<br>- spd[i+SPD_PAGE_LEN] = smbus_read_byte(0, addr, i);<br>+ for (i = 0; i < SPD_PAGE_LEN; i += 2) {<br>+ ((u16*)spd)[(i + SPD_PAGE_LEN) / 2] = \<br>+ smbus_read_word(0, addr, i);<br>+ }<br> /* Restore to page 0 */<br> smbus_write_byte(0, SPD_PAGE_0, 0, 0);<br> }<br>diff --git a/src/soc/intel/common/block/smbus/smbus_early.c b/src/soc/intel/common/block/smbus/smbus_early.c<br>index e0c4d9c..9e6afc4 100644<br>--- a/src/soc/intel/common/block/smbus/smbus_early.c<br>+++ b/src/soc/intel/common/block/smbus/smbus_early.c<br>@@ -36,6 +36,11 @@<br> REG_SCRIPT_END,<br> };<br> <br>+u16 smbus_read_word(u32 smbus_dev, u8 addr, u8 offset)<br>+{<br>+ return smbus_read16(SMBUS_IO_BASE, addr, offset);<br>+}<br>+<br> u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset)<br> {<br> return smbus_read8(SMBUS_IO_BASE, addr, offset);<br>diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c<br>index 27b4ad5..8567a27 100644<br>--- a/src/soc/intel/common/block/smbus/smbuslib.c<br>+++ b/src/soc/intel/common/block/smbus/smbuslib.c<br>@@ -135,3 +135,50 @@<br> <br> return 0;<br> }<br>+<br>+int smbus_read16(unsigned int smbus_base, unsigned int device,<br>+ unsigned int address)<br>+{<br>+ unsigned char global_status_register;<br>+ unsigned short data;<br>+<br>+ if (smbus_wait_till_ready(smbus_base) < 0)<br>+ return SMBUS_WAIT_UNTIL_READY_TIMEOUT;<br>+<br>+ /* Setup transaction */<br>+ /* Disable interrupts */<br>+ outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);<br>+ /* Set the device I'm talking to */<br>+ outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);<br>+ /* Set the command/address... */<br>+ outb(address & 0xff, smbus_base + SMBHSTCMD);<br>+ /* Set up for a byte data read */<br>+ outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x3 << 2),<br>+ (smbus_base + SMBHSTCTL));<br>+ /* Clear any lingering errors, so the transaction will run */<br>+ outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);<br>+<br>+ /* Clear the data byte... */<br>+ outb(0, smbus_base + SMBHSTDAT0);<br>+<br>+ /* Start the command */<br>+ outb((inb(smbus_base + SMBHSTCTL) | 0x40),<br>+ smbus_base + SMBHSTCTL);<br>+<br>+ /* Poll for transaction completion */<br>+ if (smbus_wait_till_done(smbus_base) < 0)<br>+ return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;<br>+<br>+ global_status_register = inb(smbus_base + SMBHSTSTAT);<br>+<br>+ /* Ignore the "In Use" status... */<br>+ global_status_register &= ~(3 << 5);<br>+<br>+ /* Read results of transaction */<br>+ data = inw(smbus_base + SMBHSTDAT0);<br>+<br>+ if (global_status_register != (1 << 1))<br>+ return SMBUS_ERROR;<br>+<br>+ return data;<br>+}<br>diff --git a/src/soc/intel/common/block/smbus/smbuslib.h b/src/soc/intel/common/block/smbus/smbuslib.h<br>index b5be6ca..05dafe9 100644<br>--- a/src/soc/intel/common/block/smbus/smbuslib.h<br>+++ b/src/soc/intel/common/block/smbus/smbuslib.h<br>@@ -34,5 +34,7 @@<br> unsigned int address);<br> int smbus_write8(unsigned int smbus_base, unsigned int device,<br> unsigned int address, unsigned int data);<br>+int smbus_read16(unsigned int smbus_base, unsigned int device,<br>+ unsigned int address);<br> <br> #endif /* SOC_INTEL_COMMON_BLOCK_SMBUS__LIB_H */<br></pre><p>To view, visit <a href="https://review.coreboot.org/22072">change 22072</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22072"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14 </div>
<div style="display:none"> Gerrit-Change-Number: 22072 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kane Chen <kane.chen@intel.com> </div>