[coreboot-gerrit] Change in coreboot[master]: asus/p2b[-ls], sb/intel/i82371eb: Add ACPI tables
Keith Hui (Code Review)
gerrit at coreboot.org
Tue Oct 17 04:38:50 CEST 2017
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/22067
Change subject: asus/p2b[-ls], sb/intel/i82371eb: Add ACPI tables
......................................................................
asus/p2b[-ls], sb/intel/i82371eb: Add ACPI tables
Add ACPI tables to p2b-ls that will be needed for soft-off and S3 resume.
Right now only have DSDT and what was done for asus/p2b.
Complete ACPI tables for p2b.
Enter a major ACPI table rework for sb/intel/i82371eb based on a
mix of previous work on p2b, other boards in tree with better ACPI
support, and OEM BIOS. Pulls in DSDT table for superios if one is defined
(only winbond/w83977tf in this group of patches). To be pulled in
by DSDTs of mainboards using this southbridge.
These parts have to be submitted in one patch to pass build.
This has not yet been boot tested and so is not for merging yet.
All feedbacks appreciated.
Change-Id: Ibcbdfcc1415280ba7e756574cb4d9364f9ee0e48
Signed-off-by: Keith Hui <buurin at gmail.com>
---
M src/mainboard/asus/p2b-ls/Kconfig
A src/mainboard/asus/p2b-ls/acpi_tables.c
A src/mainboard/asus/p2b-ls/dsdt.asl
M src/mainboard/asus/p2b/dsdt.asl
A src/southbridge/intel/i82371eb/acpi/i82371eb.asl
M src/southbridge/intel/i82371eb/acpi/pirq.asl
6 files changed, 516 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/22067/1
diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig
index 967ebd9..2bb9369 100644
--- a/src/mainboard/asus/p2b-ls/Kconfig
+++ b/src/mainboard/asus/p2b-ls/Kconfig
@@ -23,6 +23,7 @@
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select SDRAMPWR_4DIMM
+ select HAVE_ACPI_TABLES
config MAINBOARD_DIR
string
diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c
new file mode 100644
index 0000000..d740ee1
--- /dev/null
+++ b/src/mainboard/asus/p2b-ls/acpi_tables.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot at tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* mainboard has no ioapic */
+ return current;
+}
diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl
new file mode 100644
index 0000000..c5073b5
--- /dev/null
+++ b/src/mainboard/asus/p2b-ls/dsdt.asl
@@ -0,0 +1,187 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Keith Hui <buurin at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+/*
+ * Mapping of factory BIOS and coreboot ACPI names
+ * Factory coreboot
+ * DBG1 P80
+ *
+ * PX40 LPCB
+ * PIRx PRTx (x=A|B|C|D)
+ * PIRQ PCIC
+ * SYSR MBRS (Hardcoded in acpi_tables.c)
+ *
+ * PS2K KBD
+ * PS2M MOU
+ * ENFG ENCM (ENTER_CONFIG_MODE)
+ * EXFG EXCM (EXIT_CONFIG_MODE)
+ * NIDX ADDR
+ * NDAT DATA
+ * LDNM LDN (PNP_LOGICAL_DEVICE)
+ *
+ */
+#include "southbridge/intel/i82371eb/i82371eb.h"
+
+#define SUPERIO_PNP_BASE 0x3F0
+#define SUPERIO_DEV W977
+#define WINBOND_SHOW_UARTA
+#define WINBOND_SHOW_UARTB
+#define WINBOND_SHOW_FDC
+#define WINBOND_SHOW_LPT
+
+DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
+{
+ OperationRegion(X80, SystemIO, 0x80, 1)
+ Field(X80, ByteAcc, NoLock, Preserve)
+ {
+ P80, 8
+ }
+ /* Define the main processor. */
+ Scope (\_PR)
+ {
+ /* Looks like the P_CNT field can't be a method or name
+ * and has to be hardcoded to 0xe410 or generated in SSDT */
+ Processor (CPU0, 0x01, 0xe410, 0x06) {}
+ }
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ */
+
+ /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */
+ /*
+ 000b / 0x0: soft off/suspend to disk (soff/std) s5
+ 001b / 0x1: suspend to ram (str) s3
+ 010b / 0x2: powered on suspend, context lost (poscl) s1
+ 011b / 0x3: powered on suspend, cpu context lost (posccl) s2
+ 100b / 0x4: powered on suspend, context maintained (pos) s4
+ 101b / 0x5: working (clock control) s0
+ 110b / 0x6: reserved
+ 111b / 0x7: reserved
+ */
+ Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
+ /*Name (\_S1, Package () { 0x04, 0x07, 0x00, 0x00 })*/
+ Name (\_S5, Package () { 0x00, 0x06, 0x00, 0x00 })
+
+ /* Root of the bus hierarchy */
+ Scope (\_SB)
+ {
+#include "southbridge/intel/i82371eb/acpi/pirq.asl"
+ /* Top PCI device */
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ /* PCI Routing Table */
+ Name (_PRT, Package () {
+ Package (0x04) { 0x0001FFFF, 0, LNKA, 0 },
+ Package (0x04) { 0x0001FFFF, 1, LNKB, 0 },
+ Package (0x04) { 0x0001FFFF, 2, LNKC, 0 },
+ Package (0x04) { 0x0001FFFF, 3, LNKD, 0 },
+
+ Package (0x04) { 0x0004FFFF, 0, LNKA, 0 },
+ Package (0x04) { 0x0004FFFF, 1, LNKB, 0 },
+ Package (0x04) { 0x0004FFFF, 2, LNKC, 0 },
+ Package (0x04) { 0x0004FFFF, 3, LNKD, 0 },
+
+ Package (0x04) { 0x0006FFFF, 0, LNKD, 0 },
+ Package (0x04) { 0x0006FFFF, 1, LNKA, 0 },
+ Package (0x04) { 0x0006FFFF, 2, LNKB, 0 },
+ Package (0x04) { 0x0006FFFF, 3, LNKC, 0 },
+
+ Package (0x04) { 0x0009FFFF, 0, LNKD, 0 },
+ Package (0x04) { 0x0009FFFF, 1, LNKA, 0 },
+ Package (0x04) { 0x0009FFFF, 2, LNKB, 0 },
+ Package (0x04) { 0x0009FFFF, 3, LNKC, 0 },
+
+ Package (0x04) { 0x000AFFFF, 0, LNKC, 0 },
+ Package (0x04) { 0x000AFFFF, 1, LNKD, 0 },
+ Package (0x04) { 0x000AFFFF, 2, LNKA, 0 },
+ Package (0x04) { 0x000AFFFF, 3, LNKB, 0 },
+
+ Package (0x04) { 0x0007FFFF, 0, LNKC, 0 },
+ Package (0x04) { 0x0007FFFF, 1, LNKD, 0 },
+ Package (0x04) { 0x0007FFFF, 2, LNKA, 0 },
+ Package (0x04) { 0x0007FFFF, 3, LNKB, 0 },
+
+ Package (0x04) { 0x000BFFFF, 0, LNKB, 0 },
+ Package (0x04) { 0x000BFFFF, 1, LNKC, 0 },
+ Package (0x04) { 0x000BFFFF, 2, LNKD, 0 },
+ Package (0x04) { 0x000BFFFF, 3, LNKA, 0 },
+
+ Package (0x04) { 0x000CFFFF, 0, LNKA, 0 },
+ Package (0x04) { 0x000CFFFF, 1, LNKB, 0 },
+ Package (0x04) { 0x000CFFFF, 2, LNKC, 0 },
+ Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },
+
+ })
+ /* Begin PX40 southbridge block */
+#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"
+#include "southbridge/intel/i82371eb/acpi/i82371eb.asl"
+ }
+ }
+ OperationRegion (GPOB, SystemIO, 0xE42C, 0x10)
+ Field (GPOB, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x03),
+ TO12, 1, /* Device trap 12 */
+ Offset (0x08),
+ FANM, 1, /* GPO0, meant for fan */
+ Offset (0x09),
+ PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet this goes low when power is cut from its core. */
+ , 3,
+ , 2,
+ , 16,
+ MSG0, 1 /* GPO30, message LED */
+ }
+
+ Method (\_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep, Arg0 is target S-state
+ {
+ If (LNotEqual (Arg0, 0x05)) /* Off */
+ {
+ Store (0x00, FANM) /* \FANM */
+ Store (0x00, PLED) /* \PLED */
+ }
+
+ If (LEqual (Arg0, 0x01))
+ {
+ Store (One, TO12) /* \TO12, arms SMI for device 12 */
+ }
+
+ Store (One, TO12) /* \TO12 */
+ Or (Arg0, 0xF0, Local2)
+ Store (Local2, P80) /* Put out a POST code. */
+ }
+
+ /* ACPI Message */
+ Scope (\_SI)
+ {
+ Method (_MSG, 1, NotSerialized)
+ {
+ If (LEqual (Arg0, Zero))
+ {
+ Store (One, MSG0)
+ }
+ Else
+ {
+ Store (Zero, MSG0)
+ }
+ }
+ }
+}
diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl
index 00bea29..a1ed161 100644
--- a/src/mainboard/asus/p2b/dsdt.asl
+++ b/src/mainboard/asus/p2b/dsdt.asl
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Tobias Diedrich <ranma+coreboot at tdiedrich.de>
+ * Copyright (C) 2017 Keith Hui <buurin at gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,35 +16,59 @@
#include "southbridge/intel/i82371eb/i82371eb.h"
+#define SUPERIO_PNP_BASE 0x3F0
+#define SUPERIO_DEV W977
+#define WINBOND_SHOW_UARTA
+#define WINBOND_SHOW_UARTB
+#define WINBOND_SHOW_FDC
+#define WINBOND_SHOW_LPT
+
DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)
{
- /*
- * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142
- *
- * 0: soft off/suspend to disk S5
- * 1: suspend to ram S3
- * 2: powered on suspend, context lost S2
- * Note: 'context lost' means the CPU restarts at the reset
- * vector
- * 3: powered on suspend, CPU context lost S1
- * Note: Looks like 'CPU context lost' does _not_ mean the
- * CPU restarts at the reset vector. Most likely only
- * caches are lost, so both 0x3 and 0x4 map to ACPI S1
- * 4: powered on suspend, context maintained S1
- * 5: working (clock control) S0
- * 6: reserved
- * 7: reserved
+ OperationRegion(X80, SystemIO, 0x80, 1)
+ Field(X80, ByteAcc, NoLock, Preserve)
+ {
+ P80, 8
+ }
+ /* Define the main processor. */
+ Scope (\_PR)
+ {
+ /* Looks like the P_CNT field can't be a method or name
+ * and has to be hardcoded to 0xe410 or generated in SSDT */
+ Processor (CPU0, 0x01, 0xe410, 0x06) {}
+ }
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
*/
+
+ /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */
+ /*
+ 000b / 0x0: soft off/suspend to disk (soff/std) s5
+ 001b / 0x1: suspend to ram (str) s3
+ 010b / 0x2: powered on suspend, context lost (poscl) s1
+ 011b / 0x3: powered on suspend, cpu context lost (posccl) s2
+ 100b / 0x4: powered on suspend, context maintained (pos) s4
+ 101b / 0x5: working (clock control) s0
+ 110b / 0x6: reserved
+ 111b / 0x7: reserved
+ */
Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })
Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 })
Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })
- OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2)
+ OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 8)
Field (SIO1, ByteAcc, NoLock, Preserve)
{
FANP, 1, /* CPU/case fan power */
Offset (0x01),
PLED, 1,
+ , 3,
+ , 2,
+ , 16,
+ MSG0, 1 /* GPO30, message LED */
}
Method (\_PTS, 1, NotSerialized)
@@ -65,6 +90,7 @@
/* Root of the bus hierarchy */
Scope (\_SB)
{
+#include "southbridge/intel/i82371eb/acpi/pirq.asl"
/* Top PCI device */
Device (PCI0)
{
@@ -106,10 +132,25 @@
Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },
})
-
+ /* Begin PX40 southbridge block */
#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"
-#include "southbridge/intel/i82371eb/acpi/isabridge.asl"
+#include "southbridge/intel/i82371eb/acpi/i82371eb.asl"
}
-#include "southbridge/intel/i82371eb/acpi/pirq.asl"
+ }
+
+ /* ACPI Message */
+ Scope (\_SI)
+ {
+ Method (_MSG, 1, NotSerialized)
+ {
+ If (LEqual (Arg0, Zero))
+ {
+ Store (One, MSG0)
+ }
+ Else
+ {
+ Store (Zero, MSG0)
+ }
+ }
}
}
diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
new file mode 100644
index 0000000..9f3916c
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker <Nick.Barker9 at btinternet.com>
+ * Copyright (C) 2007 Rudolf Marek <r.marek at assembler.cz>
+ * Copyright (C) 2017 Keith Hui <buurin at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ */
+#include "southbridge/intel/i82371eb/i82371eb.h"
+
+// Intel LPC Bus Device - 0:4.0
+Device (PX40)
+{
+ Name(_ADR, 0x00040000)
+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)
+ Field (PIRQ, ByteAcc, NoLock, Preserve)
+ {
+ PIRA, 8,
+ PIRB, 8,
+ PIRC, 8,
+ PIRD, 8
+ }
+/*
+ * OEM BIOS for asus/p2b-ls reports mainboard resources here whereas
+ * ACPI programming of asus/p2b fills this in at runtime.
+ */
+#if 0
+ Device (SYSR)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF1, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06)
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07)
+ IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, )
+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, )
+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, )
+ IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C, )
+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, )
+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, )
+ IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, )
+ IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, )
+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, )
+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, )
+ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, )
+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, )
+ })
+ CreateByteField (BUF1, _Y06._MIN, PMLO) // _MIN: Minimum Base Address
+ CreateByteField (BUF1, 0x03, PMHI)
+ CreateByteField (BUF1, _Y06._MAX, PMRL) // _MAX: Maximum Base Address
+ CreateByteField (BUF1, 0x05, PMRH)
+ CreateByteField (BUF1, _Y07._MIN, SBLO) // _MIN: Minimum Base Address
+ CreateByteField (BUF1, 0x0B, SBHI)
+ CreateByteField (BUF1, _Y07._MAX, SBRL) // _MAX: Maximum Base Address
+ CreateByteField (BUF1, 0x0D, SBRH)
+ Store (\_SB.PCI0.PX43.PM00, Local0)
+ And (Local0, 0xFE, PMLO) /* \_SB_.PCI0.PX40.SYSR._CRS.PMLO */
+ Store (\_SB.PCI0.PX43.PM01, PMHI) /* \_SB_.PCI0.PX40.SYSR._CRS.PMHI */
+ Store (\_SB.PCI0.PX43.SB00, Local0)
+ And (Local0, 0xFE, SBLO) /* \_SB_.PCI0.PX40.SYSR._CRS.SBLO */
+ Store (\_SB.PCI0.PX43.SB01, SBHI) /* \_SB_.PCI0.PX40.SYSR._CRS.SBHI */
+ Store (PMLO, PMRL) /* \_SB_.PCI0.PX40.SYSR._CRS.PMRL */
+ Store (PMHI, PMRH) /* \_SB_.PCI0.PX40.SYSR._CRS.PMRH */
+ Store (SBLO, SBRL) /* \_SB_.PCI0.PX40.SYSR._CRS.SBRL */
+ Store (SBHI, SBRH) /* \_SB_.PCI0.PX40.SYSR._CRS.SBRH */
+ Return (BUF1) /* \_SB_.PCI0.PX40.SYSR._CRS.BUF1 */
+ }
+ }
+#endif
+/* If a superio (with DSDT table) is selected in mainboard Kconfig,
+ * include its ASL code here, otherwise declare a few basic devices
+ * that seems to be important for WinXP install. */
+#ifdef CONFIG_SUPERIO_WINBOND_W83977TF
+#include "superio/winbond/w83977tf/acpi/superio.asl"
+#else
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 floppy controller */
+ Device (FDC0)
+ {
+ Name (_HID, EisaId ("PNP0700"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () {
+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+ IRQNoFlags () {6}
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}
+ })
+ Return (BUF0)
+ }
+ }
+#endif
+ /* PNP Motherboard Resources */
+ Device(MBRS) {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x01)
+
+ External(_CRS) /* Resource Template in SSDT */
+ }
+
+ /* 8259-compatible Programmable Interrupt Controller */
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000") )
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0020, 0x0020, 0x01, 0x02, )
+ IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02, )
+ IRQNoFlags () {2}
+ })
+ }
+
+ /* PC-class DMA Controller */
+ Device (DMA1)
+ {
+ Name (_HID, EisaId ("PNP0200") )
+ Name (_CRS, ResourceTemplate ()
+ {
+ DMA (Compatibility, BusMaster, Transfer8, ) {4}
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10,)
+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x11,)
+ IO (Decode16, 0x0094, 0x0094, 0x01, 0x0C,)
+ IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20,)
+ })
+ }
+
+ /* PC-class System Timer */
+ Device (TMR)
+ {
+ Name (_HID, EisaId ("PNP0100"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,0x0040,0x0040,0x01,0x04,)
+ IRQNoFlags () {0}
+ })
+ }
+
+ /* AT Real-Time Clock */
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00") )
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,0x0070,0x0070,0x01,0x04,)
+ IRQNoFlags () {8}
+ })
+ }
+
+ Device (SPKR)
+ {
+ Name (_HID, EisaId ("PNP0800"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,0x0061,0x0061,0x01,0x01,)
+ })
+ }
+
+ /* x87-compatible Floating Point Processing Unit */
+ Device (COPR)
+ {
+ Name (_HID, EisaId ("PNP0C04") )
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,0x00F0,0x00F0,0x01,0x10,)
+ IRQNoFlags () {13}
+ })
+ }
+
+}
+/* Power management functions to allow ACPI reporting of
+ * PM and SMBus base port resources */
+Device (PX43)
+{
+ Name (_ADR, 0x00040003) // _ADR: Address
+ OperationRegion (IPMU, PCI_Config, PMBA, 0x02)
+ Field (IPMU, ByteAcc, NoLock, Preserve)
+ {
+ PM00, 8,
+ PM01, 8
+ }
+
+ OperationRegion (ISMB, PCI_Config, SMBBA, 0x02)
+ Field (ISMB, ByteAcc, NoLock, Preserve)
+ {
+ SB00, 8,
+ SB01, 8
+ }
+}
diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl
index 6525e1e..e36a0ec 100644
--- a/src/southbridge/intel/i82371eb/acpi/pirq.asl
+++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl
@@ -12,16 +12,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
-Field (\_SB.PCI0.LPCB.PCIC, AnyAcc, NoLock, Preserve)
-{
- Offset (0x60), // Interrupt Routing Registers
- PRTA, 8,
- PRTB, 8,
- PRTC, 8,
- PRTD, 8,
-}
-
Name(IRQB, ResourceTemplate(){
IRQ(Level,ActiveLow,Shared){15}
})
@@ -69,7 +59,7 @@
} \
} \
-PCI_INTX_DEV(LNKA, PRTA, 1)
-PCI_INTX_DEV(LNKB, PRTB, 2)
-PCI_INTX_DEV(LNKC, PRTC, 3)
-PCI_INTX_DEV(LNKD, PRTD, 4)
+PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1)
+PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2)
+PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3)
+PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibcbdfcc1415280ba7e756574cb4d9364f9ee0e48
Gerrit-Change-Number: 22067
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin at gmail.com>
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