<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22067">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">asus/p2b[-ls], sb/intel/i82371eb: Add ACPI tables<br><br>Add ACPI tables to p2b-ls that will be needed for soft-off and S3 resume.<br>Right now only have DSDT and what was done for asus/p2b.<br><br>Complete ACPI tables for p2b.<br><br>Enter a major ACPI table rework for sb/intel/i82371eb based on a<br>mix of previous work on p2b, other boards in tree with better ACPI<br>support, and OEM BIOS. Pulls in DSDT table for superios if one is defined<br>(only winbond/w83977tf in this group of patches). To be pulled in<br>by DSDTs of mainboards using this southbridge.<br><br>These parts have to be submitted in one patch to pass build.<br><br>This has not yet been boot tested and so is not for merging yet.<br><br>All feedbacks appreciated.<br><br>Change-Id: Ibcbdfcc1415280ba7e756574cb4d9364f9ee0e48<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>M src/mainboard/asus/p2b-ls/Kconfig<br>A src/mainboard/asus/p2b-ls/acpi_tables.c<br>A src/mainboard/asus/p2b-ls/dsdt.asl<br>M src/mainboard/asus/p2b/dsdt.asl<br>A src/southbridge/intel/i82371eb/acpi/i82371eb.asl<br>M src/southbridge/intel/i82371eb/acpi/pirq.asl<br>6 files changed, 516 insertions(+), 34 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/22067/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig<br>index 967ebd9..2bb9369 100644<br>--- a/src/mainboard/asus/p2b-ls/Kconfig<br>+++ b/src/mainboard/asus/p2b-ls/Kconfig<br>@@ -23,6 +23,7 @@<br> select HAVE_PIRQ_TABLE<br> select BOARD_ROMSIZE_KB_256<br> select SDRAMPWR_4DIMM<br>+ select HAVE_ACPI_TABLES<br> <br> config MAINBOARD_DIR<br> string<br>diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c<br>new file mode 100644<br>index 0000000..d740ee1<br>--- /dev/null<br>+++ b/src/mainboard/asus/p2b-ls/acpi_tables.c<br>@@ -0,0 +1,22 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/acpi.h><br>+<br>+unsigned long acpi_fill_madt(unsigned long current)<br>+{<br>+ /* mainboard has no ioapic */<br>+ return current;<br>+}<br>diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl<br>new file mode 100644<br>index 0000000..c5073b5<br>--- /dev/null<br>+++ b/src/mainboard/asus/p2b-ls/dsdt.asl<br>@@ -0,0 +1,187 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Keith Hui <buurin@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+/*<br>+ * Mapping of factory BIOS and coreboot ACPI names<br>+ * Factory coreboot<br>+ * DBG1 P80<br>+ *<br>+ * PX40 LPCB<br>+ * PIRx PRTx (x=A|B|C|D)<br>+ * PIRQ PCIC<br>+ * SYSR MBRS (Hardcoded in acpi_tables.c)<br>+ *<br>+ * PS2K KBD<br>+ * PS2M MOU<br>+ * ENFG ENCM (ENTER_CONFIG_MODE)<br>+ * EXFG EXCM (EXIT_CONFIG_MODE)<br>+ * NIDX ADDR<br>+ * NDAT DATA<br>+ * LDNM LDN (PNP_LOGICAL_DEVICE)<br>+ *<br>+ */<br>+#include "southbridge/intel/i82371eb/i82371eb.h"<br>+<br>+#define SUPERIO_PNP_BASE 0x3F0<br>+#define SUPERIO_DEV W977<br>+#define WINBOND_SHOW_UARTA<br>+#define WINBOND_SHOW_UARTB<br>+#define WINBOND_SHOW_FDC<br>+#define WINBOND_SHOW_LPT<br>+<br>+DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)<br>+{<br>+ OperationRegion(X80, SystemIO, 0x80, 1)<br>+ Field(X80, ByteAcc, NoLock, Preserve)<br>+ {<br>+ P80, 8<br>+ }<br>+ /* Define the main processor. */<br>+ Scope (\_PR)<br>+ {<br>+ /* Looks like the P_CNT field can't be a method or name<br>+ * and has to be hardcoded to 0xe410 or generated in SSDT */<br>+ Processor (CPU0, 0x01, 0xe410, 0x06) {}<br>+ }<br>+<br>+ /* For now only define 2 power states:<br>+ * - S0 which is fully on<br>+ * - S5 which is soft off<br>+ * Any others would involve declaring the wake up methods.<br>+ */<br>+<br>+ /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */<br>+ /*<br>+ 000b / 0x0: soft off/suspend to disk (soff/std) s5<br>+ 001b / 0x1: suspend to ram (str) s3<br>+ 010b / 0x2: powered on suspend, context lost (poscl) s1<br>+ 011b / 0x3: powered on suspend, cpu context lost (posccl) s2<br>+ 100b / 0x4: powered on suspend, context maintained (pos) s4<br>+ 101b / 0x5: working (clock control) s0<br>+ 110b / 0x6: reserved<br>+ 111b / 0x7: reserved<br>+ */<br>+ Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })<br>+ /*Name (\_S1, Package () { 0x04, 0x07, 0x00, 0x00 })*/<br>+ Name (\_S5, Package () { 0x00, 0x06, 0x00, 0x00 })<br>+<br>+ /* Root of the bus hierarchy */<br>+ Scope (\_SB)<br>+ {<br>+#include "southbridge/intel/i82371eb/acpi/pirq.asl"<br>+ /* Top PCI device */<br>+ Device (PCI0)<br>+ {<br>+ Name (_HID, EisaId ("PNP0A03"))<br>+ Name (_ADR, 0x00)<br>+ Name (_UID, 0x00)<br>+ Name (_BBN, 0x00)<br>+<br>+ /* PCI Routing Table */<br>+ Name (_PRT, Package () {<br>+ Package (0x04) { 0x0001FFFF, 0, LNKA, 0 },<br>+ Package (0x04) { 0x0001FFFF, 1, LNKB, 0 },<br>+ Package (0x04) { 0x0001FFFF, 2, LNKC, 0 },<br>+ Package (0x04) { 0x0001FFFF, 3, LNKD, 0 },<br>+<br>+ Package (0x04) { 0x0004FFFF, 0, LNKA, 0 },<br>+ Package (0x04) { 0x0004FFFF, 1, LNKB, 0 },<br>+ Package (0x04) { 0x0004FFFF, 2, LNKC, 0 },<br>+ Package (0x04) { 0x0004FFFF, 3, LNKD, 0 },<br>+<br>+ Package (0x04) { 0x0006FFFF, 0, LNKD, 0 },<br>+ Package (0x04) { 0x0006FFFF, 1, LNKA, 0 },<br>+ Package (0x04) { 0x0006FFFF, 2, LNKB, 0 },<br>+ Package (0x04) { 0x0006FFFF, 3, LNKC, 0 },<br>+<br>+ Package (0x04) { 0x0009FFFF, 0, LNKD, 0 },<br>+ Package (0x04) { 0x0009FFFF, 1, LNKA, 0 },<br>+ Package (0x04) { 0x0009FFFF, 2, LNKB, 0 },<br>+ Package (0x04) { 0x0009FFFF, 3, LNKC, 0 },<br>+<br>+ Package (0x04) { 0x000AFFFF, 0, LNKC, 0 },<br>+ Package (0x04) { 0x000AFFFF, 1, LNKD, 0 },<br>+ Package (0x04) { 0x000AFFFF, 2, LNKA, 0 },<br>+ Package (0x04) { 0x000AFFFF, 3, LNKB, 0 },<br>+<br>+ Package (0x04) { 0x0007FFFF, 0, LNKC, 0 },<br>+ Package (0x04) { 0x0007FFFF, 1, LNKD, 0 },<br>+ Package (0x04) { 0x0007FFFF, 2, LNKA, 0 },<br>+ Package (0x04) { 0x0007FFFF, 3, LNKB, 0 },<br>+<br>+ Package (0x04) { 0x000BFFFF, 0, LNKB, 0 },<br>+ Package (0x04) { 0x000BFFFF, 1, LNKC, 0 },<br>+ Package (0x04) { 0x000BFFFF, 2, LNKD, 0 },<br>+ Package (0x04) { 0x000BFFFF, 3, LNKA, 0 },<br>+<br>+ Package (0x04) { 0x000CFFFF, 0, LNKA, 0 },<br>+ Package (0x04) { 0x000CFFFF, 1, LNKB, 0 },<br>+ Package (0x04) { 0x000CFFFF, 2, LNKC, 0 },<br>+ Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },<br>+<br>+ })<br>+ /* Begin PX40 southbridge block */<br>+#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"<br>+#include "southbridge/intel/i82371eb/acpi/i82371eb.asl"<br>+ }<br>+ }<br>+ OperationRegion (GPOB, SystemIO, 0xE42C, 0x10)<br>+ Field (GPOB, ByteAcc, NoLock, Preserve)<br>+ {<br>+ Offset (0x03),<br>+ TO12, 1, /* Device trap 12 */<br>+ Offset (0x08),<br>+ FANM, 1, /* GPO0, meant for fan */<br>+ Offset (0x09),<br>+ PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet this goes low when power is cut from its core. */<br>+ , 3,<br>+ , 2,<br>+ , 16,<br>+ MSG0, 1 /* GPO30, message LED */<br>+ }<br>+<br>+ Method (\_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep, Arg0 is target S-state<br>+ {<br>+ If (LNotEqual (Arg0, 0x05)) /* Off */<br>+ {<br>+ Store (0x00, FANM) /* \FANM */<br>+ Store (0x00, PLED) /* \PLED */<br>+ }<br>+<br>+ If (LEqual (Arg0, 0x01))<br>+ {<br>+ Store (One, TO12) /* \TO12, arms SMI for device 12 */<br>+ }<br>+<br>+ Store (One, TO12) /* \TO12 */<br>+ Or (Arg0, 0xF0, Local2)<br>+ Store (Local2, P80) /* Put out a POST code. */<br>+ }<br>+<br>+ /* ACPI Message */<br>+ Scope (\_SI)<br>+ {<br>+ Method (_MSG, 1, NotSerialized)<br>+ {<br>+ If (LEqual (Arg0, Zero))<br>+ {<br>+ Store (One, MSG0)<br>+ }<br>+ Else<br>+ {<br>+ Store (Zero, MSG0)<br>+ }<br>+ }<br>+ }<br>+}<br>diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl<br>index 00bea29..a1ed161 100644<br>--- a/src/mainboard/asus/p2b/dsdt.asl<br>+++ b/src/mainboard/asus/p2b/dsdt.asl<br>@@ -2,6 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ * Copyright (C) 2017 Keith Hui <buurin@gmail.com><br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -15,35 +16,59 @@<br> <br> #include "southbridge/intel/i82371eb/i82371eb.h"<br> <br>+#define SUPERIO_PNP_BASE 0x3F0<br>+#define SUPERIO_DEV W977<br>+#define WINBOND_SHOW_UARTA<br>+#define WINBOND_SHOW_UARTB<br>+#define WINBOND_SHOW_FDC<br>+#define WINBOND_SHOW_LPT<br>+<br> DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)<br> {<br>- /*<br>- * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142<br>- *<br>- * 0: soft off/suspend to disk S5<br>- * 1: suspend to ram S3<br>- * 2: powered on suspend, context lost S2<br>- * Note: 'context lost' means the CPU restarts at the reset<br>- * vector<br>- * 3: powered on suspend, CPU context lost S1<br>- * Note: Looks like 'CPU context lost' does _not_ mean the<br>- * CPU restarts at the reset vector. Most likely only<br>- * caches are lost, so both 0x3 and 0x4 map to ACPI S1<br>- * 4: powered on suspend, context maintained S1<br>- * 5: working (clock control) S0<br>- * 6: reserved<br>- * 7: reserved<br>+ OperationRegion(X80, SystemIO, 0x80, 1)<br>+ Field(X80, ByteAcc, NoLock, Preserve)<br>+ {<br>+ P80, 8<br>+ }<br>+ /* Define the main processor. */<br>+ Scope (\_PR)<br>+ {<br>+ /* Looks like the P_CNT field can't be a method or name<br>+ * and has to be hardcoded to 0xe410 or generated in SSDT */<br>+ Processor (CPU0, 0x01, 0xe410, 0x06) {}<br>+ }<br>+<br>+ /* For now only define 2 power states:<br>+ * - S0 which is fully on<br>+ * - S5 which is soft off<br>+ * Any others would involve declaring the wake up methods.<br> */<br>+<br>+ /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */<br>+ /*<br>+ 000b / 0x0: soft off/suspend to disk (soff/std) s5<br>+ 001b / 0x1: suspend to ram (str) s3<br>+ 010b / 0x2: powered on suspend, context lost (poscl) s1<br>+ 011b / 0x3: powered on suspend, cpu context lost (posccl) s2<br>+ 100b / 0x4: powered on suspend, context maintained (pos) s4<br>+ 101b / 0x5: working (clock control) s0<br>+ 110b / 0x6: reserved<br>+ 111b / 0x7: reserved<br>+ */<br> Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })<br> Name (\_S1, Package () { 0x03, 0x03, 0x00, 0x00 })<br> Name (\_S5, Package () { 0x00, 0x00, 0x00, 0x00 })<br> <br>- OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 2)<br>+ OperationRegion (SIO1, SystemIO, Add(DEFAULT_PMBASE, GPO0), 8)<br> Field (SIO1, ByteAcc, NoLock, Preserve)<br> {<br> FANP, 1, /* CPU/case fan power */<br> Offset (0x01),<br> PLED, 1,<br>+ , 3,<br>+ , 2,<br>+ , 16,<br>+ MSG0, 1 /* GPO30, message LED */<br> }<br> <br> Method (\_PTS, 1, NotSerialized)<br>@@ -65,6 +90,7 @@<br> /* Root of the bus hierarchy */<br> Scope (\_SB)<br> {<br>+#include "southbridge/intel/i82371eb/acpi/pirq.asl"<br> /* Top PCI device */<br> Device (PCI0)<br> {<br>@@ -106,10 +132,25 @@<br> Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },<br> <br> })<br>-<br>+ /* Begin PX40 southbridge block */<br> #include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"<br>-#include "southbridge/intel/i82371eb/acpi/isabridge.asl"<br>+#include "southbridge/intel/i82371eb/acpi/i82371eb.asl"<br> }<br>-#include "southbridge/intel/i82371eb/acpi/pirq.asl"<br>+ }<br>+<br>+ /* ACPI Message */<br>+ Scope (\_SI)<br>+ {<br>+ Method (_MSG, 1, NotSerialized)<br>+ {<br>+ If (LEqual (Arg0, Zero))<br>+ {<br>+ Store (One, MSG0)<br>+ }<br>+ Else<br>+ {<br>+ Store (Zero, MSG0)<br>+ }<br>+ }<br> }<br> }<br>diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl<br>new file mode 100644<br>index 0000000..9f3916c<br>--- /dev/null<br>+++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl<br>@@ -0,0 +1,241 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com><br>+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz><br>+ * Copyright (C) 2017 Keith Hui <buurin@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+ * ISA portions taken from QEMU acpi-dsdt.dsl.<br>+ */<br>+#include "southbridge/intel/i82371eb/i82371eb.h"<br>+<br>+// Intel LPC Bus Device - 0:4.0<br>+Device (PX40)<br>+{<br>+ Name(_ADR, 0x00040000)<br>+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)<br>+ Field (PIRQ, ByteAcc, NoLock, Preserve)<br>+ {<br>+ PIRA, 8,<br>+ PIRB, 8,<br>+ PIRC, 8,<br>+ PIRD, 8<br>+ }<br>+/*<br>+ * OEM BIOS for asus/p2b-ls reports mainboard resources here whereas<br>+ * ACPI programming of asus/p2b fills this in at runtime.<br>+ */<br>+#if 0<br>+ Device (SYSR)<br>+ {<br>+ Name (_HID, EisaId ("PNP0C02"))<br>+ Method (_CRS, 0, NotSerialized)<br>+ {<br>+ Name (BUF1, ResourceTemplate ()<br>+ {<br>+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06)<br>+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07)<br>+ IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, )<br>+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, )<br>+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, )<br>+ IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C, )<br>+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, )<br>+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, )<br>+ IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, )<br>+ IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, )<br>+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, )<br>+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, )<br>+ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, )<br>+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, )<br>+ })<br>+ CreateByteField (BUF1, _Y06._MIN, PMLO) // _MIN: Minimum Base Address<br>+ CreateByteField (BUF1, 0x03, PMHI)<br>+ CreateByteField (BUF1, _Y06._MAX, PMRL) // _MAX: Maximum Base Address<br>+ CreateByteField (BUF1, 0x05, PMRH)<br>+ CreateByteField (BUF1, _Y07._MIN, SBLO) // _MIN: Minimum Base Address<br>+ CreateByteField (BUF1, 0x0B, SBHI)<br>+ CreateByteField (BUF1, _Y07._MAX, SBRL) // _MAX: Maximum Base Address<br>+ CreateByteField (BUF1, 0x0D, SBRH)<br>+ Store (\_SB.PCI0.PX43.PM00, Local0)<br>+ And (Local0, 0xFE, PMLO) /* \_SB_.PCI0.PX40.SYSR._CRS.PMLO */<br>+ Store (\_SB.PCI0.PX43.PM01, PMHI) /* \_SB_.PCI0.PX40.SYSR._CRS.PMHI */<br>+ Store (\_SB.PCI0.PX43.SB00, Local0)<br>+ And (Local0, 0xFE, SBLO) /* \_SB_.PCI0.PX40.SYSR._CRS.SBLO */<br>+ Store (\_SB.PCI0.PX43.SB01, SBHI) /* \_SB_.PCI0.PX40.SYSR._CRS.SBHI */<br>+ Store (PMLO, PMRL) /* \_SB_.PCI0.PX40.SYSR._CRS.PMRL */<br>+ Store (PMHI, PMRH) /* \_SB_.PCI0.PX40.SYSR._CRS.PMRH */<br>+ Store (SBLO, SBRL) /* \_SB_.PCI0.PX40.SYSR._CRS.SBRL */<br>+ Store (SBHI, SBRH) /* \_SB_.PCI0.PX40.SYSR._CRS.SBRH */<br>+ Return (BUF1) /* \_SB_.PCI0.PX40.SYSR._CRS.BUF1 */<br>+ }<br>+ }<br>+#endif<br>+/* If a superio (with DSDT table) is selected in mainboard Kconfig,<br>+ * include its ASL code here, otherwise declare a few basic devices<br>+ * that seems to be important for WinXP install. */<br>+#ifdef CONFIG_SUPERIO_WINBOND_W83977TF<br>+#include "superio/winbond/w83977tf/acpi/superio.asl"<br>+#else<br>+ /* PS/2 keyboard (seems to be important for WinXP install) */<br>+ Device (KBD)<br>+ {<br>+ Name (_HID, EisaId ("PNP0303"))<br>+ Method (_STA, 0, NotSerialized)<br>+ {<br>+ Return (0x0f)<br>+ }<br>+ Method (_CRS, 0, NotSerialized)<br>+ {<br>+ Name (TMP, ResourceTemplate () {<br>+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)<br>+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)<br>+ IRQNoFlags () {1}<br>+ })<br>+ Return (TMP)<br>+ }<br>+ }<br>+<br>+ /* PS/2 mouse */<br>+ Device (MOU)<br>+ {<br>+ Name (_HID, EisaId ("PNP0F13"))<br>+ Method (_STA, 0, NotSerialized)<br>+ {<br>+ Return (0x0f)<br>+ }<br>+ Method (_CRS, 0, NotSerialized)<br>+ {<br>+ Name (TMP, ResourceTemplate () {<br>+ IRQNoFlags () {12}<br>+ })<br>+ Return (TMP)<br>+ }<br>+ }<br>+<br>+ /* PS/2 floppy controller */<br>+ Device (FDC0)<br>+ {<br>+ Name (_HID, EisaId ("PNP0700"))<br>+ Method (_STA, 0, NotSerialized)<br>+ {<br>+ Return (0x0f)<br>+ }<br>+ Method (_CRS, 0, NotSerialized)<br>+ {<br>+ Name (BUF0, ResourceTemplate () {<br>+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)<br>+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)<br>+ IRQNoFlags () {6}<br>+ DMA (Compatibility, NotBusMaster, Transfer8) {2}<br>+ })<br>+ Return (BUF0)<br>+ }<br>+ }<br>+#endif<br>+ /* PNP Motherboard Resources */<br>+ Device(MBRS) {<br>+ Name (_HID, EisaId ("PNP0C02"))<br>+ Name (_UID, 0x01)<br>+<br>+ External(_CRS) /* Resource Template in SSDT */<br>+ }<br>+<br>+ /* 8259-compatible Programmable Interrupt Controller */<br>+ Device (PIC)<br>+ {<br>+ Name (_HID, EisaId ("PNP0000") )<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16, 0x0020, 0x0020, 0x01, 0x02, )<br>+ IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02, )<br>+ IRQNoFlags () {2}<br>+ })<br>+ }<br>+<br>+ /* PC-class DMA Controller */<br>+ Device (DMA1)<br>+ {<br>+ Name (_HID, EisaId ("PNP0200") )<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ DMA (Compatibility, BusMaster, Transfer8, ) {4}<br>+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10,)<br>+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x11,)<br>+ IO (Decode16, 0x0094, 0x0094, 0x01, 0x0C,)<br>+ IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20,)<br>+ })<br>+ }<br>+<br>+ /* PC-class System Timer */<br>+ Device (TMR)<br>+ {<br>+ Name (_HID, EisaId ("PNP0100"))<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16,0x0040,0x0040,0x01,0x04,)<br>+ IRQNoFlags () {0}<br>+ })<br>+ }<br>+<br>+ /* AT Real-Time Clock */<br>+ Device (RTC)<br>+ {<br>+ Name (_HID, EisaId ("PNP0B00") )<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16,0x0070,0x0070,0x01,0x04,)<br>+ IRQNoFlags () {8}<br>+ })<br>+ }<br>+<br>+ Device (SPKR)<br>+ {<br>+ Name (_HID, EisaId ("PNP0800"))<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16,0x0061,0x0061,0x01,0x01,)<br>+ })<br>+ }<br>+<br>+ /* x87-compatible Floating Point Processing Unit */<br>+ Device (COPR)<br>+ {<br>+ Name (_HID, EisaId ("PNP0C04") )<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16,0x00F0,0x00F0,0x01,0x10,)<br>+ IRQNoFlags () {13}<br>+ })<br>+ }<br>+<br>+}<br>+/* Power management functions to allow ACPI reporting of<br>+ * PM and SMBus base port resources */<br>+Device (PX43)<br>+{<br>+ Name (_ADR, 0x00040003) // _ADR: Address<br>+ OperationRegion (IPMU, PCI_Config, PMBA, 0x02)<br>+ Field (IPMU, ByteAcc, NoLock, Preserve)<br>+ {<br>+ PM00, 8,<br>+ PM01, 8<br>+ }<br>+<br>+ OperationRegion (ISMB, PCI_Config, SMBBA, 0x02)<br>+ Field (ISMB, ByteAcc, NoLock, Preserve)<br>+ {<br>+ SB00, 8,<br>+ SB01, 8<br>+ }<br>+}<br>diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl<br>index 6525e1e..e36a0ec 100644<br>--- a/src/southbridge/intel/i82371eb/acpi/pirq.asl<br>+++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl<br>@@ -12,16 +12,6 @@<br> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br> * GNU General Public License for more details.<br> */<br>-<br>-Field (\_SB.PCI0.LPCB.PCIC, AnyAcc, NoLock, Preserve)<br>-{<br>- Offset (0x60), // Interrupt Routing Registers<br>- PRTA, 8,<br>- PRTB, 8,<br>- PRTC, 8,<br>- PRTD, 8,<br>-}<br>-<br> Name(IRQB, ResourceTemplate(){<br> IRQ(Level,ActiveLow,Shared){15}<br> })<br>@@ -69,7 +59,7 @@<br> } \<br> } \<br> <br>-PCI_INTX_DEV(LNKA, PRTA, 1)<br>-PCI_INTX_DEV(LNKB, PRTB, 2)<br>-PCI_INTX_DEV(LNKC, PRTC, 3)<br>-PCI_INTX_DEV(LNKD, PRTD, 4)<br>+PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1)<br>+PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2)<br>+PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3)<br>+PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4)<br></pre><p>To view, visit <a href="https://review.coreboot.org/22067">change 22067</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22067"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibcbdfcc1415280ba7e756574cb4d9364f9ee0e48 </div>
<div style="display:none"> Gerrit-Change-Number: 22067 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>