[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: Cleanup files

[John E. Kabat Jr. (Code Review)]

Hello frank vibrans,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/22064

to review the following change.


Change subject: soc/amd/common: Cleanup files
......................................................................

soc/amd/common: Cleanup files

Clean up style issues and a duplicate memory write.

Change-Id: I097ed9e4a631a4cf65cbf480d152dd00f1404df9
Signed-off-by: Frank Vibrans <frank.vibrans at scarletltd.com>
---
M src/soc/amd/common/block/include/amdblocks/spi.h
M src/soc/amd/common/block/spi/spi.c
2 files changed, 4 insertions(+), 12 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/22064/1

diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h
index 4b1bb06..c06d097 100644
--- a/src/soc/amd/common/block/include/amdblocks/spi.h
+++ b/src/soc/amd/common/block/include/amdblocks/spi.h
@@ -21,6 +21,7 @@
 
 #define SPI_PCI_DEV		0x14
 #define SPI_PCI_FN		0x03
+#define SPI_ENABLES_MASK	0x3f
 
 /* SPI registers in PCI space */
 #define SPI_PCI_BASE_ADDR	0xa0
@@ -53,9 +54,6 @@
 #else
 #define AMD_SB_SPI_TX_LEN	8
 #endif
-
-/* TODO: Replace this with APM_CNT_GNVS_UPDATE */
-#define APM_CNT_SPI_SMM_INIT		0xd9
 
 /* SPI related functions called from AMD vendorcode */
 void spi_SaveS3info(uint32_t pos, size_t size, uint8_t *buf, u32 len);
diff --git a/src/soc/amd/common/block/spi/spi.c b/src/soc/amd/common/block/spi/spi.c
index d7b0784..9bff570 100644
--- a/src/soc/amd/common/block/spi/spi.c
+++ b/src/soc/amd/common/block/spi/spi.c
@@ -33,7 +33,6 @@
 	int retval = spi_flash_probe(0, 0, flash);
 	if (retval) {
 		printk(BIOS_DEBUG, "Could not find SPI device\n");
-		/* Dont make flow stop. */
 		return;
 	}
 
@@ -71,9 +70,7 @@
 
 static void execute_command(void)
 {
-	uint8_t reg8;
-
-	reg8 = spi_read(SPI_REG_CNTRL02);
+	uint8_t reg8 = spi_read(SPI_REG_CNTRL02);
 	reg8 |= CNTRL02_EXEC_OPCODE;
 	spi_write(SPI_REG_CNTRL02, reg8);
 
@@ -87,7 +84,7 @@
 	/* First byte is cmd which can not being sent through FIFO. */
 	uint8_t cmd = read8(dout);
 	uint8_t readoffby1;
-	size_t count;
+	int count;
 
 	dout += 1;	/* Advance past cmd */
 	bytesout--;
@@ -133,7 +130,6 @@
 	}
 
 	for (count = 0; count < bytesin; count++, din++) {
-		*(uint8_t *)din = spi_read(SPI_REG_FIFO);
 		write8(din, spi_read(SPI_REG_FIFO));
 	}
 
@@ -161,9 +157,7 @@
 #if !ENV_SMM
 void spi_init(void)
 {
-	device_t dev;
-
-	dev = (device_t)dev_find_slot(0, PCI_DEVFN(SPI_PCI_DEV, SPI_PCI_FN));
+	device_t dev = (device_t)dev_find_slot(0, PCI_DEVFN(SPI_PCI_DEV, SPI_PCI_FN));
 	spibar = pci_read_config32(dev, SPI_PCI_BASE_ADDR) & ~0x1F;
 }
 #endif

-- 
To view, visit https://review.coreboot.org/22064
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I097ed9e4a631a4cf65cbf480d152dd00f1404df9
Gerrit-Change-Number: 22064
Gerrit-PatchSet: 1
Gerrit-Owner: John E. Kabat Jr. <john.kabat at scarletltd.com>
Gerrit-Reviewer: frank vibrans <frank.vibrans at scarletltd.com>
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