<p>John E. Kabat Jr. would like frank vibrans to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/22064">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/common: Cleanup files<br><br>Clean up style issues and a duplicate memory write.<br><br>Change-Id: I097ed9e4a631a4cf65cbf480d152dd00f1404df9<br>Signed-off-by: Frank Vibrans <frank.vibrans@scarletltd.com><br>---<br>M src/soc/amd/common/block/include/amdblocks/spi.h<br>M src/soc/amd/common/block/spi/spi.c<br>2 files changed, 4 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/22064/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h<br>index 4b1bb06..c06d097 100644<br>--- a/src/soc/amd/common/block/include/amdblocks/spi.h<br>+++ b/src/soc/amd/common/block/include/amdblocks/spi.h<br>@@ -21,6 +21,7 @@<br> <br> #define SPI_PCI_DEV 0x14<br> #define SPI_PCI_FN 0x03<br>+#define SPI_ENABLES_MASK 0x3f<br> <br> /* SPI registers in PCI space */<br> #define SPI_PCI_BASE_ADDR 0xa0<br>@@ -53,9 +54,6 @@<br> #else<br> #define AMD_SB_SPI_TX_LEN 8<br> #endif<br>-<br>-/* TODO: Replace this with APM_CNT_GNVS_UPDATE */<br>-#define APM_CNT_SPI_SMM_INIT 0xd9<br> <br> /* SPI related functions called from AMD vendorcode */<br> void spi_SaveS3info(uint32_t pos, size_t size, uint8_t *buf, u32 len);<br>diff --git a/src/soc/amd/common/block/spi/spi.c b/src/soc/amd/common/block/spi/spi.c<br>index d7b0784..9bff570 100644<br>--- a/src/soc/amd/common/block/spi/spi.c<br>+++ b/src/soc/amd/common/block/spi/spi.c<br>@@ -33,7 +33,6 @@<br> int retval = spi_flash_probe(0, 0, flash);<br> if (retval) {<br> printk(BIOS_DEBUG, "Could not find SPI device\n");<br>- /* Dont make flow stop. */<br> return;<br> }<br> <br>@@ -71,9 +70,7 @@<br> <br> static void execute_command(void)<br> {<br>- uint8_t reg8;<br>-<br>- reg8 = spi_read(SPI_REG_CNTRL02);<br>+ uint8_t reg8 = spi_read(SPI_REG_CNTRL02);<br> reg8 |= CNTRL02_EXEC_OPCODE;<br> spi_write(SPI_REG_CNTRL02, reg8);<br> <br>@@ -87,7 +84,7 @@<br> /* First byte is cmd which can not being sent through FIFO. */<br> uint8_t cmd = read8(dout);<br> uint8_t readoffby1;<br>- size_t count;<br>+ int count;<br> <br> dout += 1; /* Advance past cmd */<br> bytesout--;<br>@@ -133,7 +130,6 @@<br> }<br> <br> for (count = 0; count < bytesin; count++, din++) {<br>- *(uint8_t *)din = spi_read(SPI_REG_FIFO);<br> write8(din, spi_read(SPI_REG_FIFO));<br> }<br> <br>@@ -161,9 +157,7 @@<br> #if !ENV_SMM<br> void spi_init(void)<br> {<br>- device_t dev;<br>-<br>- dev = (device_t)dev_find_slot(0, PCI_DEVFN(SPI_PCI_DEV, SPI_PCI_FN));<br>+ device_t dev = (device_t)dev_find_slot(0, PCI_DEVFN(SPI_PCI_DEV, SPI_PCI_FN));<br> spibar = pci_read_config32(dev, SPI_PCI_BASE_ADDR) & ~0x1F;<br> }<br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/22064">change 22064</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22064"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I097ed9e4a631a4cf65cbf480d152dd00f1404df9 </div>
<div style="display:none"> Gerrit-Change-Number: 22064 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: John E. Kabat Jr. <john.kabat@scarletltd.com> </div>
<div style="display:none"> Gerrit-Reviewer: frank vibrans <frank.vibrans@scarletltd.com> </div>