[coreboot-gerrit] Change in coreboot[master]: Stoney Ridge Platforms: cast AGESA tables to void *

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22059


Change subject: Stoney Ridge Platforms: cast AGESA tables to void *
......................................................................

Stoney Ridge Platforms: cast AGESA tables to void *

In the original AGESA headers, these tables are not defined as const.
Cast them to void * so that they'll work with either version of the
headers.

BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.

Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
M src/mainboard/amd/gardenia/bootblock/OemCustomize.c
M src/mainboard/google/kahlee/BiosCallOuts.c
M src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
M src/mainboard/google/kahlee/bootblock/OemCustomize.c
5 files changed, 9 insertions(+), 9 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/22059/1

diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
index 6aebe4f..8ab4240 100644
--- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
+++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c
@@ -47,5 +47,5 @@
 
 void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
 {
-	FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;
+	FchParams_reset->EarlyOemGpioTable = (void *)oem_gardenia_gpio;
 }
diff --git a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
index 52148fd..53b4a6c 100644
--- a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
+++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c
@@ -102,8 +102,8 @@
 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 	.Flags        = DESCRIPTOR_TERMINATE_LIST,
 	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList
+	.PciePortList = (void *)PortList,
+	.DdiLinkList  = (void *)DdiList
 };
 
 static const UINT32 AzaliaCodecAlc286Table[] = {
@@ -150,7 +150,7 @@
 /*---------------------------------------------------------------------------*/
 VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
 {
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
 	InitEarly->PlatformConfig.AzaliaCodecVerbTable =
 					(uint64_t)(uintptr_t)CodecTableList;
 }
diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c
index 82f13d6..49f7190 100644
--- a/src/mainboard/google/kahlee/BiosCallOuts.c
+++ b/src/mainboard/google/kahlee/BiosCallOuts.c
@@ -23,7 +23,7 @@
 
 void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env)
 {
-	FchParams_env->PostOemGpioTable = oem_kahlee_gpio;
+	FchParams_env->PostOemGpioTable = (void *)oem_kahlee_gpio;
 
 	/* SDHCI/MMC configuration */
 	FchParams_env->Sd.SdSlotType = 1; // EMMC
diff --git a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
index 73d1295..3ca3c6f 100644
--- a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
+++ b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c
@@ -23,5 +23,5 @@
 
 void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)
 {
-	FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio;
+	FchParams_reset->EarlyOemGpioTable = (void *)oem_kahlee_gpio;
 }
diff --git a/src/mainboard/google/kahlee/bootblock/OemCustomize.c b/src/mainboard/google/kahlee/bootblock/OemCustomize.c
index 38d08e5..9530169 100644
--- a/src/mainboard/google/kahlee/bootblock/OemCustomize.c
+++ b/src/mainboard/google/kahlee/bootblock/OemCustomize.c
@@ -101,8 +101,8 @@
 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 	.Flags        = DESCRIPTOR_TERMINATE_LIST,
 	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList
+	.PciePortList = (void *)PortList,
+	.DdiLinkList  = (void *)DdiList
 };
 
 /*---------------------------------------------------------------------------*/
@@ -123,7 +123,7 @@
 /*---------------------------------------------------------------------------*/
 VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)
 {
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
+	InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;
 	InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;
 	InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73
Gerrit-Change-Number: 22059
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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