<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22059">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Stoney Ridge Platforms: cast AGESA tables to void *<br><br>In the original AGESA headers, these tables are not defined as const.<br>Cast them to void * so that they'll work with either version of the<br>headers.<br><br>BUG=b:64766233<br>TEST=Build in cros tree and upstream coreboot, with old headers<br>and updated headers.<br><br>Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>M src/mainboard/amd/gardenia/bootblock/OemCustomize.c<br>M src/mainboard/google/kahlee/BiosCallOuts.c<br>M src/mainboard/google/kahlee/bootblock/BiosCallOuts.c<br>M src/mainboard/google/kahlee/bootblock/OemCustomize.c<br>5 files changed, 9 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/22059/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>index 6aebe4f..8ab4240 100644<br>--- a/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>+++ b/src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c<br>@@ -47,5 +47,5 @@<br> <br> void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)<br> {<br>- FchParams_reset->EarlyOemGpioTable = oem_gardenia_gpio;<br>+   FchParams_reset->EarlyOemGpioTable = (void *)oem_gardenia_gpio;<br> }<br>diff --git a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c<br>index 52148fd..53b4a6c 100644<br>--- a/src/mainboard/amd/gardenia/bootblock/OemCustomize.c<br>+++ b/src/mainboard/amd/gardenia/bootblock/OemCustomize.c<br>@@ -102,8 +102,8 @@<br> static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {<br>       .Flags        = DESCRIPTOR_TERMINATE_LIST,<br>    .SocketId     = 0,<br>-   .PciePortList = PortList,<br>-    .DdiLinkList  = DdiList<br>+      .PciePortList = (void *)PortList,<br>+    .DdiLinkList  = (void *)DdiList<br> };<br> <br> static const UINT32 AzaliaCodecAlc286Table[] = {<br>@@ -150,7 +150,7 @@<br> /*---------------------------------------------------------------------------*/<br> VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)<br> {<br>-       InitEarly->GnbConfig.PcieComplexList = &PcieComplex;<br>+  InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;<br>   InitEarly->PlatformConfig.AzaliaCodecVerbTable =<br>                                   (uint64_t)(uintptr_t)CodecTableList;<br> }<br>diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c<br>index 82f13d6..49f7190 100644<br>--- a/src/mainboard/google/kahlee/BiosCallOuts.c<br>+++ b/src/mainboard/google/kahlee/BiosCallOuts.c<br>@@ -23,7 +23,7 @@<br> <br> void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env)<br> {<br>-     FchParams_env->PostOemGpioTable = oem_kahlee_gpio;<br>+        FchParams_env->PostOemGpioTable = (void *)oem_kahlee_gpio;<br> <br>      /* SDHCI/MMC configuration */<br>         FchParams_env->Sd.SdSlotType = 1; // EMMC<br>diff --git a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c<br>index 73d1295..3ca3c6f 100644<br>--- a/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c<br>+++ b/src/mainboard/google/kahlee/bootblock/BiosCallOuts.c<br>@@ -23,5 +23,5 @@<br> <br> void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset)<br> {<br>-       FchParams_reset->EarlyOemGpioTable = oem_kahlee_gpio;<br>+     FchParams_reset->EarlyOemGpioTable = (void *)oem_kahlee_gpio;<br> }<br>diff --git a/src/mainboard/google/kahlee/bootblock/OemCustomize.c b/src/mainboard/google/kahlee/bootblock/OemCustomize.c<br>index 38d08e5..9530169 100644<br>--- a/src/mainboard/google/kahlee/bootblock/OemCustomize.c<br>+++ b/src/mainboard/google/kahlee/bootblock/OemCustomize.c<br>@@ -101,8 +101,8 @@<br> static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {<br>     .Flags        = DESCRIPTOR_TERMINATE_LIST,<br>    .SocketId     = 0,<br>-   .PciePortList = PortList,<br>-    .DdiLinkList  = DdiList<br>+      .PciePortList = (void *)PortList,<br>+    .DdiLinkList  = (void *)DdiList<br> };<br> <br> /*---------------------------------------------------------------------------*/<br>@@ -123,7 +123,7 @@<br> /*---------------------------------------------------------------------------*/<br> VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly)<br> {<br>-        InitEarly->GnbConfig.PcieComplexList = &PcieComplex;<br>+  InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex;<br>   InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus;<br>        InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth;<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/22059">change 22059</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22059"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73 </div>
<div style="display:none"> Gerrit-Change-Number: 22059 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>