[coreboot-gerrit] Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Enable hardware P state control

[Vaibhav Shankar (Code Review)]

Vaibhav Shankar has uploaded this change for review. ( https://review.coreboot.org/22049


Change subject: mainboard/intel/cannonlake_rvp: Enable hardware P state control
......................................................................

mainboard/intel/cannonlake_rvp: Enable hardware P state control

This patch provides configuration parameter to enable/disable
Intel Speed Shift Technology.

Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974
Signed-off-by: Vaibhav Shankar <vaibhav.shankar at intel.com>
---
M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
2 files changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/22049/1

diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
index 00c3e00..a8d7a53 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -32,6 +32,9 @@
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
index 086d650..8054211 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -32,6 +32,9 @@
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Integrated Graphics Device

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974
Gerrit-Change-Number: 22049
Gerrit-PatchSet: 1
Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar at intel.com>
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