<p>Vaibhav Shankar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22049">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/cannonlake_rvp: Enable hardware P state control<br><br>This patch provides configuration parameter to enable/disable<br>Intel Speed Shift Technology.<br><br>Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974<br>Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>2 files changed, 6 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/22049/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>index 00c3e00..a8d7a53 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>@@ -32,6 +32,9 @@<br>   register "SataPortsEnable[0]" = "1"<br>       register "SataPortsEnable[1]" = "1"<br> <br>+   # Enable "Intel Speed Shift Technology"<br>+    register "speed_shift_enable" = "1"<br>+<br>    device domain 0 on<br>            device pci 00.0 on  end # Host Bridge<br>                 device pci 02.0 on  end # Integrated Graphics Device<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>index 086d650..8054211 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb<br>@@ -32,6 +32,9 @@<br>  register "SataPortsEnable[0]" = "1"<br>       register "SataPortsEnable[1]" = "1"<br> <br>+   # Enable "Intel Speed Shift Technology"<br>+    register "speed_shift_enable" = "1"<br>+<br>    device domain 0 on<br>            device pci 00.0 on  end # Host Bridge<br>                 device pci 02.0 on  end # Integrated Graphics Device<br></pre><p>To view, visit <a href="https://review.coreboot.org/22049">change 22049</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22049"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974 </div>
<div style="display:none"> Gerrit-Change-Number: 22049 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Vaibhav Shankar <vaibhav.shankar@intel.com> </div>