[coreboot-gerrit] Change in coreboot[master]: purism/librem13v2: Update devicetree settings

[Youness Alaoui (Code Review)]

Hello Matt DeVillier,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/22042

to review the following change.


Change subject: purism/librem13v2: Update devicetree settings
......................................................................

purism/librem13v2: Update devicetree settings

Disable SataDevSlp and update other values to match vendor/AMI firmware.

Change-Id: I6f278be54b86450575c366d68bfa6a67575b0fdd
Signed-off-by: Youness Alaoui <youness.alaoui at puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/purism/librem13v2/devicetree.cb
1 file changed, 7 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/22042/1

diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index 29d35af..a289aea 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -3,8 +3,8 @@
 	# Enable deep Sx states
 	register "deep_s3_enable_ac" = "0"
 	register "deep_s3_enable_dc" = "0"
-	register "deep_s5_enable_ac" = "1"
-	register "deep_s5_enable_dc" = "1"
+	register "deep_s5_enable_ac" = "0"
+	register "deep_s5_enable_dc" = "0"
 	register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
 
 	# GPE configuration
@@ -32,7 +32,10 @@
 	register "SataSalpSupport" = "0"
 	register "SataMode" = "0"
 	register "SataPortsEnable[0]" = "1"
+	register "SataPortsEnable[1]" = "0"
 	register "SataPortsEnable[2]" = "1"
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[2]" = "0"
 	register "EnableAzalia" = "1"
 	register "DspEnable" = "0"
 	register "IoBufferOwnership" = "0"
@@ -55,7 +58,7 @@
 	register "SerialIrqConfigSirqEnable" = "1"
 	register "PmConfigSlpS3MinAssert" = "2"        # 50ms
 	register "PmConfigSlpS4MinAssert" = "1"        # 1s
-	register "PmConfigSlpSusMinAssert" = "1"       # 500ms
+	register "PmConfigSlpSusMinAssert" = "3"       # 500ms
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
 	register "PmTimerDisabled" = "0"
 
@@ -151,7 +154,7 @@
 	register "PcieRpEnable[4]" = "1"
 	register "PcieRpEnable[8]" = "1"
 	# Enable CLKREQ# for RP9
-	register "PcieRpClkReqSupport[8]" = "1"
+	register "PcieRpClkReqSupport[8]" = "0"
 	# ClkReq for NVMe - Bruteforced (no other value works)
 	register "PcieRpClkReqNumber[8]" = "2"
 

-- 
To view, visit https://review.coreboot.org/22042
To unsubscribe, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6f278be54b86450575c366d68bfa6a67575b0fdd
Gerrit-Change-Number: 22042
Gerrit-PatchSet: 1
Gerrit-Owner: Youness Alaoui <snifikino at gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier at gmail.com>
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