<p>Youness Alaoui would like Matt DeVillier to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/22042">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">purism/librem13v2: Update devicetree settings<br><br>Disable SataDevSlp and update other values to match vendor/AMI firmware.<br><br>Change-Id: I6f278be54b86450575c366d68bfa6a67575b0fdd<br>Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm><br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/purism/librem13v2/devicetree.cb<br>1 file changed, 7 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/22042/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb<br>index 29d35af..a289aea 100644<br>--- a/src/mainboard/purism/librem13v2/devicetree.cb<br>+++ b/src/mainboard/purism/librem13v2/devicetree.cb<br>@@ -3,8 +3,8 @@<br>  # Enable deep Sx states<br>       register "deep_s3_enable_ac" = "0"<br>        register "deep_s3_enable_dc" = "0"<br>-       register "deep_s5_enable_ac" = "1"<br>-       register "deep_s5_enable_dc" = "1"<br>+       register "deep_s5_enable_ac" = "0"<br>+       register "deep_s5_enable_dc" = "0"<br>        register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"<br> <br>      # GPE configuration<br>@@ -32,7 +32,10 @@<br>       register "SataSalpSupport" = "0"<br>  register "SataMode" = "0"<br>         register "SataPortsEnable[0]" = "1"<br>+      register "SataPortsEnable[1]" = "0"<br>       register "SataPortsEnable[2]" = "1"<br>+      register "SataPortsDevSlp[0]" = "0"<br>+      register "SataPortsDevSlp[2]" = "0"<br>       register "EnableAzalia" = "1"<br>     register "DspEnable" = "0"<br>        register "IoBufferOwnership" = "0"<br>@@ -55,7 +58,7 @@<br>     register "SerialIrqConfigSirqEnable" = "1"<br>        register "PmConfigSlpS3MinAssert" = "2"        # 50ms<br>     register "PmConfigSlpS4MinAssert" = "1"        # 1s<br>-      register "PmConfigSlpSusMinAssert" = "1"       # 500ms<br>+   register "PmConfigSlpSusMinAssert" = "3"       # 500ms<br>    register "PmConfigSlpAMinAssert" = "3"         # 2s<br>       register "PmTimerDisabled" = "0"<br> <br>@@ -151,7 +154,7 @@<br>  register "PcieRpEnable[4]" = "1"<br>  register "PcieRpEnable[8]" = "1"<br>  # Enable CLKREQ# for RP9<br>-     register "PcieRpClkReqSupport[8]" = "1"<br>+  register "PcieRpClkReqSupport[8]" = "0"<br>   # ClkReq for NVMe - Bruteforced (no other value works)<br>        register "PcieRpClkReqNumber[8]" = "2"<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/22042">change 22042</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22042"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6f278be54b86450575c366d68bfa6a67575b0fdd </div>
<div style="display:none"> Gerrit-Change-Number: 22042 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Youness Alaoui <snifikino@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Matt DeVillier <matt.devillier@gmail.com> </div>