[coreboot-gerrit] Change in coreboot[master]: purism/librem13v2: Fix USB settings and set OC pin

[Youness Alaoui (Code Review)]

Youness Alaoui has uploaded this change for review. ( https://review.coreboot.org/22043


Change subject: purism/librem13v2: Fix USB settings and set OC pin
......................................................................

purism/librem13v2: Fix USB settings and set OC pin

The USB settings were wrong in some places, or missing and the
USB_OC values were taken from the schematics.

Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a
Signed-off-by: Youness Alaoui <youness.alaoui at puri.sm>
---
M src/mainboard/purism/librem13v2/devicetree.cb
1 file changed, 7 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/22043/1

diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index a289aea..fd095f2 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -158,14 +158,17 @@
 	# ClkReq for NVMe - Bruteforced (no other value works)
 	register "PcieRpClkReqNumber[8]" = "2"
 
-	register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)"	# Type-C Port
-	register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port (right)
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"	# Type-C Port
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-A Port (right)
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
 	register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)"	# Camera
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port (left)
+	register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)"	# Type-A Port (left)
 	register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)"	# SD
 
-	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-A Port (right)
+	# OC1 should be for Type-C but it seems to not have been wired, according to
+	# the available schematics, even though it is labeled as USB_OC_TYPEC.
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A Port (right)
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# Type-C Port
 
 	# PL2 override 25W

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a
Gerrit-Change-Number: 22043
Gerrit-PatchSet: 1
Gerrit-Owner: Youness Alaoui <snifikino at gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier at gmail.com>
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