<p>Youness Alaoui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22043">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">purism/librem13v2: Fix USB settings and set OC pin<br><br>The USB settings were wrong in some places, or missing and the<br>USB_OC values were taken from the schematics.<br><br>Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a<br>Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm><br>---<br>M src/mainboard/purism/librem13v2/devicetree.cb<br>1 file changed, 7 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/22043/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb<br>index a289aea..fd095f2 100644<br>--- a/src/mainboard/purism/librem13v2/devicetree.cb<br>+++ b/src/mainboard/purism/librem13v2/devicetree.cb<br>@@ -158,14 +158,17 @@<br>      # ClkReq for NVMe - Bruteforced (no other value works)<br>        register "PcieRpClkReqNumber[8]" = "2"<br> <br>-        register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)"        # Type-C Port<br>-        register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right)<br>+        register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"      # Type-C Port<br>+        register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"             # Type-A Port (right)<br>         register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth<br>   register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)"        # Camera<br>-     register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left)<br>+ register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)"    # Type-A Port (left)<br>  register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD<br> <br>-      register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)"     # Type-A Port (right)<br>+        # OC1 should be for Type-C but it seems to not have been wired, according to<br>+ # the available schematics, even though it is labeled as USB_OC_TYPEC.<br>+       register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)"     # Type-C Port<br>+        register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right)<br>         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"     # Type-C Port<br> <br>      # PL2 override 25W<br></pre><p>To view, visit <a href="https://review.coreboot.org/22043">change 22043</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22043"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a </div>
<div style="display:none"> Gerrit-Change-Number: 22043 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Youness Alaoui <snifikino@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Matt DeVillier <matt.devillier@gmail.com> </div>