[coreboot-gerrit] Change in coreboot[master]: mb/google/soraka: [WIP] change the pad reset config from DEEP to RSMRST
Rizwan Qureshi (Code Review)
gerrit at coreboot.org
Mon Oct 16 12:41:03 CEST 2017
Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/22039
Change subject: mb/google/soraka: [WIP] change the pad reset config from DEEP to RSMRST
......................................................................
mb/google/soraka: [WIP] change the pad reset config from DEEP to RSMRST
In skylake based platforms, it is found that the GPIO pads
are being configured as pad reset on host deep reset assuming that
their state/config would be retained across warm reboots. However,
this is not case in skylake and kabylake, the pad ireset config has
to be set to "Resume reset" (RSMRST) to achieve that.
Also, The pad reset config field values for RSMRST differ between
GPP (Primary well GPIOs) and GPD (Deep Sleep Well GPIOs) pads.
The same value (11b) was being used for both. This has been fixed
as part of Ib5c2b90a5af022ceb7312ff56fa8b4cc31ef8b8c.
BUG=b:64386481
BRANCH=None
TEST= Build and Boot soraka, S3/S0ix cycling with functionlity tests.
Change-Id: I7ed936687a40944dde71f95334d9866c0990aa50
Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
M src/mainboard/google/poppy/variants/soraka/gpio.c
1 file changed, 93 insertions(+), 93 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22039/1
diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c
index 92f866f..f0bd062 100644
--- a/src/mainboard/google/poppy/variants/soraka/gpio.c
+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c
@@ -41,14 +41,14 @@
/* A12 : BM_BUSY# ==> NC */
PAD_CFG_NC(GPP_A12),
/* A13 : SUSWARN# ==> SUSWARN_L */
- PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_A13, NONE, RSMRST, NF1),
/* A14 : ESPI_RESET# */
/* A15 : SUSACK# ==> SUSACK_L */
- PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_A15, NONE, RSMRST, NF1),
/* A16 : SD_1P8_SEL ==> SD_PWR_1800_SEL */
- PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_A16, NONE, RSMRST, NF1),
/* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */
- PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_A17, NONE, RSMRST, NF1),
/* A18 : ISH_GP0 ==> NC */
PAD_CFG_NC(GPP_A18),
/* A19 : ISH_GP1 ==> NC */
@@ -75,7 +75,7 @@
/* B5 : SRCCLKREQ0# ==> NC */
PAD_CFG_NC(GPP_B5),
/* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */
- PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B6, NONE, RSMRST, NF1),
/* B7 : SRCCLKREQ2# ==> NC */
PAD_CFG_NC(GPP_B7),
/* B9 : SRCCLKREQ4# ==> NC */
@@ -85,20 +85,20 @@
/* B11 : EXT_PWR_GATE# ==> NC */
PAD_CFG_NC(GPP_B11),
/* B12 : SLP_S0# ==> SLP_S0_L_G */
- PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B12, NONE, RSMRST, NF1),
/* B13 : PLTRST# ==> PLT_RST_L */
- PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B13, NONE, RSMRST, NF1),
/* B14 : SPKR ==> NC */
PAD_CFG_NC(GPP_B14),
#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
- PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B15, NONE, RSMRST, NF1),
/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
- PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B16, NONE, RSMRST, NF1),
/* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
- PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B17, NONE, RSMRST, NF1),
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
- PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B18, NONE, RSMRST, NF1),
#else
/* B15 : GSPI0_CS# ==> NC */
PAD_CFG_NC(GPP_B15),
@@ -133,34 +133,34 @@
/* C5 : SML0ALERT# ==> NC */
PAD_CFG_NC(GPP_C5),
/* C6 : SM1CLK ==> EC_IN_RW_OD */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, RSMRST),
/* C7 : SM1DATA ==> NC */
PAD_CFG_NC(GPP_C7),
/* C8 : UART0_RXD ==> FP_INT */
PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),
/* C9 : UART0_TXD ==> FP_RST_ODL */
- PAD_CFG_GPO(GPP_C9, 0, DEEP),
+ PAD_CFG_GPO(GPP_C9, 0, RSMRST),
/* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */
- PAD_CFG_GPO(GPP_C10, 1, DEEP),
+ PAD_CFG_GPO(GPP_C10, 1, RSMRST),
/* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */
- PAD_CFG_GPO(GPP_C11, 0, DEEP),
+ PAD_CFG_GPO(GPP_C11, 0, RSMRST),
/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, RSMRST),
/* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, RSMRST),
/* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, RSMRST),
/* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, RSMRST),
/* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */
- PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C16, NONE, RSMRST, NF1),
/* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */
- PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C17, NONE, RSMRST, NF1),
#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
- PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C18, NONE, RSMRST, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
- PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C19, NONE, RSMRST, NF1),
#else
/* C18 : I2C1_SDA ==> NC */
PAD_CFG_NC(GPP_C18),
@@ -168,13 +168,13 @@
PAD_CFG_NC(GPP_C19),
#endif
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
- PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C20, NONE, RSMRST, NF1),
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
- PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C21, NONE, RSMRST, NF1),
/* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */
- PAD_CFG_GPO(GPP_C22, 0, DEEP),
+ PAD_CFG_GPO(GPP_C22, 0, RSMRST),
/* C23 : UART2_CTS# ==> PCH_WP */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, RSMRST),
/* D0 : SPI1_CS# ==> NC */
PAD_CFG_NC(GPP_D0),
@@ -187,9 +187,9 @@
/* D4 : FASHTRIG ==> NC */
PAD_CFG_NC(GPP_D4),
/* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */
- PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_D5, NONE, RSMRST, NF1),
/* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */
- PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_D6, NONE, RSMRST, NF1),
/* D7 : ISH_I2C1_SDA ==> NC */
PAD_CFG_NC(GPP_D7),
/* D8 : ISH_I2C1_SCL ==> NC */
@@ -197,7 +197,7 @@
/* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */
PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST),
/* D10 : ISH_SPI_CLK ==> SPKR_RST_L */
- PAD_CFG_GPO(GPP_D10, 1, DEEP),
+ PAD_CFG_GPO(GPP_D10, 1, RSMRST),
/* D11 : ISH_SPI_MISO ==> SPKR_INT_L */
PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),
/* D12 : ISH_SPI_MOSI ==> NC */
@@ -211,19 +211,19 @@
/* D16 : ISH_UART0_CTS# ==> NC */
PAD_CFG_NC(GPP_D16),
/* D17 : DMIC_CLK1 */
- PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D17, NONE, RSMRST, NF1),
/* D18 : DMIC_DATA1 */
- PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D18, NONE, RSMRST, NF1),
/* D19 : DMIC_CLK0 */
- PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D19, NONE, RSMRST, NF1),
/* D20 : DMIC_DATA0 */
- PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D20, NONE, RSMRST, NF1),
/* D21 : SPI1_IO2 ==> NC */
PAD_CFG_NC(GPP_D21),
/* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */
- PAD_CFG_GPO(GPP_D22, 1, DEEP),
+ PAD_CFG_GPO(GPP_D22, 1, RSMRST),
/* D23 : I2S_MCLK ==> I2S_MCLK_R */
- PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_D23, NONE, RSMRST, NF1),
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
@@ -232,7 +232,7 @@
/* E2 : SATAXPCIE2 ==> NC */
PAD_CFG_NC(GPP_E2),
/* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */
- PAD_CFG_GPO(GPP_E3, 0, DEEP),
+ PAD_CFG_GPO(GPP_E3, 0, RSMRST),
/* E4 : SATA_DEVSLP0 ==> NC */
PAD_CFG_NC(GPP_E4),
/* E5 : SATA_DEVSLP1 ==> NC */
@@ -244,23 +244,23 @@
/* E8 : SATALED# ==> NC */
PAD_CFG_NC(GPP_E8),
/* E9 : USB2_OCO# ==> USB_C0_OC_ODL */
- PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E9, NONE, RSMRST, NF1),
/* E10 : USB2_OC1# ==> USB_C1_OC_ODL */
- PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E10, NONE, RSMRST, NF1),
/* E11 : USB2_OC2# ==> TOUCHSCREEN_STOP_L */
- PAD_CFG_GPO(GPP_E11, 0, DEEP),
+ PAD_CFG_GPO(GPP_E11, 0, RSMRST),
/* E12 : USB2_OC3# ==> USB2_OC3_L */
- PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E12, NONE, RSMRST, NF1),
/* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */
- PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),
+ PAD_CFG_NF(GPP_E13, 20K_PD, RSMRST, NF1),
/* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */
- PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),
+ PAD_CFG_NF(GPP_E14, 20K_PD, RSMRST, NF1),
/* E15 : DDPD_HPD2 ==> SD_CD# */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, RSMRST),
/* E16 : DDPE_HPD3 ==> NC(TP244) */
PAD_CFG_NC(GPP_E16),
/* E17 : EDP_HPD */
- PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E17, NONE, RSMRST, NF1),
/* E18 : DDPB_CTRLCLK ==> NC */
PAD_CFG_NC(GPP_E18),
/* E19 : DDPB_CTRLDATA ==> NC */
@@ -276,89 +276,89 @@
/* The next 4 pads are for bit banging the amplifiers, default to I2S */
/* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, RSMRST),
/* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, RSMRST),
/* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, RSMRST),
/* F3 : I2S2_RXD */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, RSMRST),
/* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */
- PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_F4, NONE, RSMRST, NF1),
/* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */
- PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_F5, NONE, RSMRST, NF1),
/* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */
- PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_F6, NONE, RSMRST, NF1),
/* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */
- PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_F7, NONE, RSMRST, NF1),
/* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */
- PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_F8, NONE, RSMRST, NF1),
/* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */
- PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_F9, NONE, RSMRST, NF1),
/* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */
- PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_F10, NONE, RSMRST, NF1),
/* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */
- PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1),
+ PAD_CFG_NF_1V8(GPP_F11, NONE, RSMRST, NF1),
/* F12 : EMMC_CMD */
- PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F12, NONE, RSMRST, NF1),
/* F13 : EMMC_DATA0 */
- PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F13, NONE, RSMRST, NF1),
/* F14 : EMMC_DATA1 */
- PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F14, NONE, RSMRST, NF1),
/* F15 : EMMC_DATA2 */
- PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F15, NONE, RSMRST, NF1),
/* F16 : EMMC_DATA3 */
- PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F16, NONE, RSMRST, NF1),
/* F17 : EMMC_DATA4 */
- PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F17, NONE, RSMRST, NF1),
/* F18 : EMMC_DATA5 */
- PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F18, NONE, RSMRST, NF1),
/* F19 : EMMC_DATA6 */
- PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F19, NONE, RSMRST, NF1),
/* F20 : EMMC_DATA7 */
- PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F20, NONE, RSMRST, NF1),
/* F21 : EMMC_RCLK */
- PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F21, NONE, RSMRST, NF1),
/* F22 : EMMC_CLK */
- PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_F22, NONE, RSMRST, NF1),
/* F23 : RSVD ==> NC */
PAD_CFG_NC(GPP_F23),
/* G0 : SD_CMD */
- PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_G0, NONE, RSMRST, NF1),
/* G1 : SD_DATA0 */
- PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_G1, NONE, RSMRST, NF1),
/* G2 : SD_DATA1 */
- PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_G2, NONE, RSMRST, NF1),
/* G3 : SD_DATA2 */
- PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_G3, NONE, RSMRST, NF1),
/* G4 : SD_DATA3 */
- PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_G4, NONE, RSMRST, NF1),
/* G5 : SD_CD# */
- PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_G5, NONE, RSMRST, NF1),
/* G6 : SD_CLK */
- PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_G6, NONE, RSMRST, NF1),
/* G7 : SD_WP */
- PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),
+ PAD_CFG_NF(GPP_G7, 20K_PD, RSMRST, NF1),
/* GPD0: BATLOW# ==> PCH_BATLOW_L */
- PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1),
/* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */
- PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPD1, NONE, RSMRST, NF1),
/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */
- PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1),
/* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */
- PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),
+ PAD_CFG_NF(GPD3, 20K_PU, RSMRST, NF1),
/* GPD4: SLP_S3# ==> SLP_S3_L */
- PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1),
/* GPD5: SLP_S4# ==> SLP_S4_L */
- PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1),
/* GPD6: SLP_A# ==> NC(TP26) */
PAD_CFG_NC(GPD6),
/* GPD7: RSVD ==> NC */
PAD_CFG_NC(GPD7),
/* GPD8: SUSCLK ==> PCH_SUSCLK */
- PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1),
/* GPD9: SLP_WLAN# ==> NC(TP25) */
PAD_CFG_NC(GPD9),
/* GPD10: SLP_S5# ==> NC(TP15) */
@@ -370,34 +370,34 @@
/* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = {
/* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */
- PAD_CFG_GPO(GPP_B8, 0, DEEP),
+ PAD_CFG_GPO(GPP_B8, 0, RSMRST),
#if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)
/* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */
- PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B15, NONE, RSMRST, NF1),
/* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */
- PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B16, NONE, RSMRST, NF1),
/* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */
- PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B17, NONE, RSMRST, NF1),
/* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */
- PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B18, NONE, RSMRST, NF1),
#endif
#if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)
/* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */
- PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C18, NONE, RSMRST, NF1),
/* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */
- PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C19, NONE, RSMRST, NF1),
#endif
/* Ensure UART pins are in native mode for H1. */
/* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */
- PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C20, NONE, RSMRST, NF1),
/* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */
- PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_C21, NONE, RSMRST, NF1),
/* C23 : UART2_CTS# ==> PCH_WP */
- PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, RSMRST),
/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7ed936687a40944dde71f95334d9866c0990aa50
Gerrit-Change-Number: 22039
Gerrit-PatchSet: 1
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi at intel.com>
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