<p>Rizwan Qureshi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22039">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/soraka: [WIP] change the pad reset config from DEEP to RSMRST<br><br>In skylake based platforms, it is found that the GPIO pads<br>are being configured as pad reset on host deep reset assuming that<br>their state/config would be retained across warm reboots. However,<br>this is not case in skylake and kabylake, the pad ireset config has<br>to be set to "Resume reset" (RSMRST) to achieve that.<br><br>Also, The pad reset config field values for RSMRST differ between<br>GPP (Primary well GPIOs) and GPD (Deep Sleep Well GPIOs) pads.<br>The same value (11b) was being used for both. This has been fixed<br>as part of Ib5c2b90a5af022ceb7312ff56fa8b4cc31ef8b8c.<br><br>BUG=b:64386481<br>BRANCH=None<br>TEST= Build and Boot soraka, S3/S0ix cycling with functionlity tests.<br><br>Change-Id: I7ed936687a40944dde71f95334d9866c0990aa50<br>Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>---<br>M src/mainboard/google/poppy/variants/soraka/gpio.c<br>1 file changed, 93 insertions(+), 93 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22039/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c<br>index 92f866f..f0bd062 100644<br>--- a/src/mainboard/google/poppy/variants/soraka/gpio.c<br>+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c<br>@@ -41,14 +41,14 @@<br> /* A12 : BM_BUSY# ==> NC */<br> PAD_CFG_NC(GPP_A12),<br> /* A13 : SUSWARN# ==> SUSWARN_L */<br>- PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_A13, NONE, RSMRST, NF1),<br> /* A14 : ESPI_RESET# */<br> /* A15 : SUSACK# ==> SUSACK_L */<br>- PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_A15, NONE, RSMRST, NF1),<br> /* A16 : SD_1P8_SEL ==> SD_PWR_1800_SEL */<br>- PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_A16, NONE, RSMRST, NF1),<br> /* A17 : SD_PWR_EN# ==> EN_SD_SOCKET_PWR_L */<br>- PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_A17, NONE, RSMRST, NF1),<br> /* A18 : ISH_GP0 ==> NC */<br> PAD_CFG_NC(GPP_A18),<br> /* A19 : ISH_GP1 ==> NC */<br>@@ -75,7 +75,7 @@<br> /* B5 : SRCCLKREQ0# ==> NC */<br> PAD_CFG_NC(GPP_B5),<br> /* B6 : SRCCLKREQ1# ==> WLAN_PCIE_CLKREQ_L */<br>- PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B6, NONE, RSMRST, NF1),<br> /* B7 : SRCCLKREQ2# ==> NC */<br> PAD_CFG_NC(GPP_B7),<br> /* B9 : SRCCLKREQ4# ==> NC */<br>@@ -85,20 +85,20 @@<br> /* B11 : EXT_PWR_GATE# ==> NC */<br> PAD_CFG_NC(GPP_B11),<br> /* B12 : SLP_S0# ==> SLP_S0_L_G */<br>- PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B12, NONE, RSMRST, NF1),<br> /* B13 : PLTRST# ==> PLT_RST_L */<br>- PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B13, NONE, RSMRST, NF1),<br> /* B14 : SPKR ==> NC */<br> PAD_CFG_NC(GPP_B14),<br> #if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)<br> /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */<br>- PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B15, NONE, RSMRST, NF1),<br> /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */<br>- PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B16, NONE, RSMRST, NF1),<br> /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */<br>- PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B17, NONE, RSMRST, NF1),<br> /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */<br>- PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B18, NONE, RSMRST, NF1),<br> #else<br> /* B15 : GSPI0_CS# ==> NC */<br> PAD_CFG_NC(GPP_B15),<br>@@ -133,34 +133,34 @@<br> /* C5 : SML0ALERT# ==> NC */<br> PAD_CFG_NC(GPP_C5),<br> /* C6 : SM1CLK ==> EC_IN_RW_OD */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, RSMRST),<br> /* C7 : SM1DATA ==> NC */<br> PAD_CFG_NC(GPP_C7),<br> /* C8 : UART0_RXD ==> FP_INT */<br> PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST),<br> /* C9 : UART0_TXD ==> FP_RST_ODL */<br>- PAD_CFG_GPO(GPP_C9, 0, DEEP),<br>+ PAD_CFG_GPO(GPP_C9, 0, RSMRST),<br> /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */<br>- PAD_CFG_GPO(GPP_C10, 1, DEEP),<br>+ PAD_CFG_GPO(GPP_C10, 1, RSMRST),<br> /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */<br>- PAD_CFG_GPO(GPP_C11, 0, DEEP),<br>+ PAD_CFG_GPO(GPP_C11, 0, RSMRST),<br> /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, RSMRST),<br> /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, RSMRST),<br> /* C14 : UART1_RTS# ==> PCH_MEM_CONFIG[2] */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, RSMRST),<br> /* C15 : UART1_CTS# ==> PCH_MEM_CONFIG[3] */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, RSMRST),<br> /* C16 : I2C0_SDA ==> PCH_I2C0_TOUCHSCREEN_3V3_SDA */<br>- PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_C16, NONE, RSMRST, NF1),<br> /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */<br>- PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_C17, NONE, RSMRST, NF1),<br> #if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)<br> /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */<br>- PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_C18, NONE, RSMRST, NF1),<br> /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */<br>- PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_C19, NONE, RSMRST, NF1),<br> #else<br> /* C18 : I2C1_SDA ==> NC */<br> PAD_CFG_NC(GPP_C18),<br>@@ -168,13 +168,13 @@<br> PAD_CFG_NC(GPP_C19),<br> #endif<br> /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */<br>- PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_C20, NONE, RSMRST, NF1),<br> /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */<br>- PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_C21, NONE, RSMRST, NF1),<br> /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */<br>- PAD_CFG_GPO(GPP_C22, 0, DEEP),<br>+ PAD_CFG_GPO(GPP_C22, 0, RSMRST),<br> /* C23 : UART2_CTS# ==> PCH_WP */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, RSMRST),<br> <br> /* D0 : SPI1_CS# ==> NC */<br> PAD_CFG_NC(GPP_D0),<br>@@ -187,9 +187,9 @@<br> /* D4 : FASHTRIG ==> NC */<br> PAD_CFG_NC(GPP_D4),<br> /* D5 : ISH_I2C0_SDA ==> ISH_I2C_SENSOR_1V8_SDA */<br>- PAD_CFG_NF_1V8(GPP_D5, NONE, DEEP, NF1),<br>+ PAD_CFG_NF_1V8(GPP_D5, NONE, RSMRST, NF1),<br> /* D6 : ISH_I2C0_SCL ==> ISH_I2C_SENSOR_1V8_SCL */<br>- PAD_CFG_NF_1V8(GPP_D6, NONE, DEEP, NF1),<br>+ PAD_CFG_NF_1V8(GPP_D6, NONE, RSMRST, NF1),<br> /* D7 : ISH_I2C1_SDA ==> NC */<br> PAD_CFG_NC(GPP_D7),<br> /* D8 : ISH_I2C1_SCL ==> NC */<br>@@ -197,7 +197,7 @@<br> /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */<br> PAD_CFG_GPI_GPIO_DRIVER(GPP_D9, NONE, PLTRST),<br> /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */<br>- PAD_CFG_GPO(GPP_D10, 1, DEEP),<br>+ PAD_CFG_GPO(GPP_D10, 1, RSMRST),<br> /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */<br> PAD_CFG_GPI_APIC(GPP_D11, NONE, PLTRST),<br> /* D12 : ISH_SPI_MOSI ==> NC */<br>@@ -211,19 +211,19 @@<br> /* D16 : ISH_UART0_CTS# ==> NC */<br> PAD_CFG_NC(GPP_D16),<br> /* D17 : DMIC_CLK1 */<br>- PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_D17, NONE, RSMRST, NF1),<br> /* D18 : DMIC_DATA1 */<br>- PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_D18, NONE, RSMRST, NF1),<br> /* D19 : DMIC_CLK0 */<br>- PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_D19, NONE, RSMRST, NF1),<br> /* D20 : DMIC_DATA0 */<br>- PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_D20, NONE, RSMRST, NF1),<br> /* D21 : SPI1_IO2 ==> NC */<br> PAD_CFG_NC(GPP_D21),<br> /* D22 : SPI1_IO3 ==> BOOT_BEEP_OVERRIDE */<br>- PAD_CFG_GPO(GPP_D22, 1, DEEP),<br>+ PAD_CFG_GPO(GPP_D22, 1, RSMRST),<br> /* D23 : I2S_MCLK ==> I2S_MCLK_R */<br>- PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_D23, NONE, RSMRST, NF1),<br> <br> /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */<br> PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),<br>@@ -232,7 +232,7 @@<br> /* E2 : SATAXPCIE2 ==> NC */<br> PAD_CFG_NC(GPP_E2),<br> /* E3 : CPU_GP0 ==> TOUCHSCREEN_RST_L */<br>- PAD_CFG_GPO(GPP_E3, 0, DEEP),<br>+ PAD_CFG_GPO(GPP_E3, 0, RSMRST),<br> /* E4 : SATA_DEVSLP0 ==> NC */<br> PAD_CFG_NC(GPP_E4),<br> /* E5 : SATA_DEVSLP1 ==> NC */<br>@@ -244,23 +244,23 @@<br> /* E8 : SATALED# ==> NC */<br> PAD_CFG_NC(GPP_E8),<br> /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */<br>- PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_E9, NONE, RSMRST, NF1),<br> /* E10 : USB2_OC1# ==> USB_C1_OC_ODL */<br>- PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_E10, NONE, RSMRST, NF1),<br> /* E11 : USB2_OC2# ==> TOUCHSCREEN_STOP_L */<br>- PAD_CFG_GPO(GPP_E11, 0, DEEP),<br>+ PAD_CFG_GPO(GPP_E11, 0, RSMRST),<br> /* E12 : USB2_OC3# ==> USB2_OC3_L */<br>- PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_E12, NONE, RSMRST, NF1),<br> /* E13 : DDPB_HPD0 ==> USB_C0_DP_HPD */<br>- PAD_CFG_NF(GPP_E13, 20K_PD, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_E13, 20K_PD, RSMRST, NF1),<br> /* E14 : DDPC_HPD1 ==> USB_C1_DP_HPD */<br>- PAD_CFG_NF(GPP_E14, 20K_PD, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_E14, 20K_PD, RSMRST, NF1),<br> /* E15 : DDPD_HPD2 ==> SD_CD# */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, 20K_PU, RSMRST),<br> /* E16 : DDPE_HPD3 ==> NC(TP244) */<br> PAD_CFG_NC(GPP_E16),<br> /* E17 : EDP_HPD */<br>- PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_E17, NONE, RSMRST, NF1),<br> /* E18 : DDPB_CTRLCLK ==> NC */<br> PAD_CFG_NC(GPP_E18),<br> /* E19 : DDPB_CTRLDATA ==> NC */<br>@@ -276,89 +276,89 @@<br> <br> /* The next 4 pads are for bit banging the amplifiers, default to I2S */<br> /* F0 : I2S2_SCLK ==> I2S2_SCLK_SPKR_R */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F0, NONE, RSMRST),<br> /* F1 : I2S2_SFRM ==> I2S2_SFRM_SPKR_R */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F1, NONE, RSMRST),<br> /* F2 : I2S2_TXD ==> I2S2_PCH_TX_SPKR_RX_R */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F2, NONE, RSMRST),<br> /* F3 : I2S2_RXD */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_F3, NONE, RSMRST),<br> /* F4 : I2C2_SDA ==> PCH_I2C2_CAM_PMIC_1V8_SDA */<br>- PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1),<br>+ PAD_CFG_NF_1V8(GPP_F4, NONE, RSMRST, NF1),<br> /* F5 : I2C2_SCL ==> PCH_I2C2_CAM_PMIC_1V8_SCL */<br>- PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1),<br>+ PAD_CFG_NF_1V8(GPP_F5, NONE, RSMRST, NF1),<br> /* F6 : I2C3_SDA ==> PCH_I2C3_PEN_1V8_SDA */<br>- PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1),<br>+ PAD_CFG_NF_1V8(GPP_F6, NONE, RSMRST, NF1),<br> /* F7 : I2C3_SCL ==> PCH_I2C3_PEN_1V8_SCL */<br>- PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1),<br>+ PAD_CFG_NF_1V8(GPP_F7, NONE, RSMRST, NF1),<br> /* F8 : I2C4_SDA ==> PCH_I2C4_UFCAM_1V8_SDA */<br>- PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),<br>+ PAD_CFG_NF_1V8(GPP_F8, NONE, RSMRST, NF1),<br> /* F9 : I2C4_SCL ==> PCH_I2C4_UFCAM_1V8_SCL */<br>- PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),<br>+ PAD_CFG_NF_1V8(GPP_F9, NONE, RSMRST, NF1),<br> /* F10 : I2C5_SDA ==> PCH_I2C5_AUDIO_1V8_SDA */<br>- PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF1),<br>+ PAD_CFG_NF_1V8(GPP_F10, NONE, RSMRST, NF1),<br> /* F11 : I2C5_SCL ==> PCH_I2C5_AUDIO_1V8_SCL */<br>- PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF1),<br>+ PAD_CFG_NF_1V8(GPP_F11, NONE, RSMRST, NF1),<br> /* F12 : EMMC_CMD */<br>- PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F12, NONE, RSMRST, NF1),<br> /* F13 : EMMC_DATA0 */<br>- PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F13, NONE, RSMRST, NF1),<br> /* F14 : EMMC_DATA1 */<br>- PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F14, NONE, RSMRST, NF1),<br> /* F15 : EMMC_DATA2 */<br>- PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F15, NONE, RSMRST, NF1),<br> /* F16 : EMMC_DATA3 */<br>- PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F16, NONE, RSMRST, NF1),<br> /* F17 : EMMC_DATA4 */<br>- PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F17, NONE, RSMRST, NF1),<br> /* F18 : EMMC_DATA5 */<br>- PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F18, NONE, RSMRST, NF1),<br> /* F19 : EMMC_DATA6 */<br>- PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F19, NONE, RSMRST, NF1),<br> /* F20 : EMMC_DATA7 */<br>- PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F20, NONE, RSMRST, NF1),<br> /* F21 : EMMC_RCLK */<br>- PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F21, NONE, RSMRST, NF1),<br> /* F22 : EMMC_CLK */<br>- PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_F22, NONE, RSMRST, NF1),<br> /* F23 : RSVD ==> NC */<br> PAD_CFG_NC(GPP_F23),<br> <br> /* G0 : SD_CMD */<br>- PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_G0, NONE, RSMRST, NF1),<br> /* G1 : SD_DATA0 */<br>- PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_G1, NONE, RSMRST, NF1),<br> /* G2 : SD_DATA1 */<br>- PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_G2, NONE, RSMRST, NF1),<br> /* G3 : SD_DATA2 */<br>- PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_G3, NONE, RSMRST, NF1),<br> /* G4 : SD_DATA3 */<br>- PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_G4, NONE, RSMRST, NF1),<br> /* G5 : SD_CD# */<br>- PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_G5, NONE, RSMRST, NF1),<br> /* G6 : SD_CLK */<br>- PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_G6, NONE, RSMRST, NF1),<br> /* G7 : SD_WP */<br>- PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_G7, 20K_PD, RSMRST, NF1),<br> <br> /* GPD0: BATLOW# ==> PCH_BATLOW_L */<br>- PAD_CFG_NF(GPD0, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1),<br> /* GPD1: ACPRESENT ==> EC_PCH_ACPRESENT */<br>- PAD_CFG_NF(GPD1, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPD1, NONE, RSMRST, NF1),<br> /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_R_L */<br>- PAD_CFG_NF(GPD2, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPD2, NONE, RSMRST, NF1),<br> /* GPD3: PWRBTN# ==> PCH_PWR_BTN_L */<br>- PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1),<br>+ PAD_CFG_NF(GPD3, 20K_PU, RSMRST, NF1),<br> /* GPD4: SLP_S3# ==> SLP_S3_L */<br>- PAD_CFG_NF(GPD4, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1),<br> /* GPD5: SLP_S4# ==> SLP_S4_L */<br>- PAD_CFG_NF(GPD5, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1),<br> /* GPD6: SLP_A# ==> NC(TP26) */<br> PAD_CFG_NC(GPD6),<br> /* GPD7: RSVD ==> NC */<br> PAD_CFG_NC(GPD7),<br> /* GPD8: SUSCLK ==> PCH_SUSCLK */<br>- PAD_CFG_NF(GPD8, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1),<br> /* GPD9: SLP_WLAN# ==> NC(TP25) */<br> PAD_CFG_NC(GPD9),<br> /* GPD10: SLP_S5# ==> NC(TP15) */<br>@@ -370,34 +370,34 @@<br> /* Early pad configuration in bootblock */<br> static const struct pad_config early_gpio_table[] = {<br> /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */<br>- PAD_CFG_GPO(GPP_B8, 0, DEEP),<br>+ PAD_CFG_GPO(GPP_B8, 0, RSMRST),<br> <br> #if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM)<br> /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */<br>- PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B15, NONE, RSMRST, NF1),<br> /* B16 : GSPI0_CLK ==> PCH_SPI_H1_3V3_CLK */<br>- PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B16, NONE, RSMRST, NF1),<br> /* B17 : GSPI0_MISO ==> PCH_SPI_H1_3V3_MISO */<br>- PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B17, NONE, RSMRST, NF1),<br> /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */<br>- PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_B18, NONE, RSMRST, NF1),<br> #endif<br> <br> #if IS_ENABLED(CONFIG_POPPY_USE_I2C_TPM)<br> /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */<br>- PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_C18, NONE, RSMRST, NF1),<br> /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */<br>- PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_C19, NONE, RSMRST, NF1),<br> #endif<br> <br> /* Ensure UART pins are in native mode for H1. */<br> /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */<br>- PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_C20, NONE, RSMRST, NF1),<br> /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */<br>- PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),<br>+ PAD_CFG_NF(GPP_C21, NONE, RSMRST, NF1),<br> <br> /* C23 : UART2_CTS# ==> PCH_WP */<br>- PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, DEEP),<br>+ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, 20K_PU, RSMRST),<br> <br> /* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */<br> PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),<br></pre><p>To view, visit <a href="https://review.coreboot.org/22039">change 22039</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22039"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7ed936687a40944dde71f95334d9866c0990aa50 </div>
<div style="display:none"> Gerrit-Change-Number: 22039 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>