[coreboot-gerrit] Change in coreboot[master]: Intel i82830 boards & chips: Remove - using LATE_CBMEM_INIT
Martin Roth (Code Review)
gerrit at coreboot.org
Sun Oct 15 23:19:22 CEST 2017
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22032
Change subject: Intel i82830 boards & chips: Remove - using LATE_CBMEM_INIT
......................................................................
Intel i82830 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.8 branch.
chips:
cpu/intel/socket_mFCBGA479
southbridge/intel/i82801dx
northbridge/intel/i82830
Mainboards:
mainboard/rca/rm4100
mainboard/thomson/ip1000
Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9
Signed-off-by: Martin Roth <gaumless at gmail.com>
---
M src/arch/x86/Makefile.inc
M src/cpu/intel/Makefile.inc
D src/cpu/intel/socket_mFCBGA479/Kconfig
D src/cpu/intel/socket_mFCBGA479/Makefile.inc
M src/cpu/x86/smm/smmrelocate.S
M src/device/Kconfig
D src/mainboard/rca/Kconfig
D src/mainboard/rca/Kconfig.name
D src/mainboard/rca/rm4100/Kconfig
D src/mainboard/rca/rm4100/Kconfig.name
D src/mainboard/rca/rm4100/board_info.txt
D src/mainboard/rca/rm4100/devicetree.cb
D src/mainboard/rca/rm4100/gpio.c
D src/mainboard/rca/rm4100/irq_tables.c
D src/mainboard/rca/rm4100/romstage.c
D src/mainboard/rca/rm4100/smihandler.c
D src/mainboard/rca/rm4100/spd_table.h
D src/mainboard/thomson/Kconfig
D src/mainboard/thomson/Kconfig.name
D src/mainboard/thomson/ip1000/Kconfig
D src/mainboard/thomson/ip1000/Kconfig.name
D src/mainboard/thomson/ip1000/board_info.txt
D src/mainboard/thomson/ip1000/devicetree.cb
D src/mainboard/thomson/ip1000/gpio.c
D src/mainboard/thomson/ip1000/irq_tables.c
D src/mainboard/thomson/ip1000/mainboard.c
D src/mainboard/thomson/ip1000/romstage.c
D src/mainboard/thomson/ip1000/smihandler.c
D src/mainboard/thomson/ip1000/spd_table.h
D src/northbridge/intel/i82830/Kconfig
D src/northbridge/intel/i82830/Makefile.inc
D src/northbridge/intel/i82830/i82830.h
D src/northbridge/intel/i82830/memory_initialized.c
D src/northbridge/intel/i82830/northbridge.c
D src/northbridge/intel/i82830/raminit.c
D src/northbridge/intel/i82830/raminit.h
D src/northbridge/intel/i82830/smihandler.c
D src/northbridge/intel/i82830/vga.c
D src/southbridge/intel/i82801dx/Kconfig
D src/southbridge/intel/i82801dx/Makefile.inc
D src/southbridge/intel/i82801dx/ac97.c
D src/southbridge/intel/i82801dx/bootblock.c
D src/southbridge/intel/i82801dx/chip.h
D src/southbridge/intel/i82801dx/early_smbus.c
D src/southbridge/intel/i82801dx/i82801dx.c
D src/southbridge/intel/i82801dx/i82801dx.h
D src/southbridge/intel/i82801dx/ide.c
D src/southbridge/intel/i82801dx/lpc.c
D src/southbridge/intel/i82801dx/nvs.h
D src/southbridge/intel/i82801dx/pci.c
D src/southbridge/intel/i82801dx/reset.c
D src/southbridge/intel/i82801dx/smi.c
D src/southbridge/intel/i82801dx/smihandler.c
D src/southbridge/intel/i82801dx/tco_timer.c
D src/southbridge/intel/i82801dx/usb.c
D src/southbridge/intel/i82801dx/usb2.c
56 files changed, 0 insertions(+), 4,917 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/22032/1
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index cc227b3..0f3eaf4 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -43,10 +43,6 @@
pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE))
pci$(stripped_vgabios_id).rom-type := optionrom
-cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin
-mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE))
-mbi.bin-type := mbi
-
###############################################################################
# common support for early assembly includes
###############################################################################
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 37fac8e..6fe13c9 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -9,7 +9,6 @@
subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284
subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370
subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
-subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN
diff --git a/src/cpu/intel/socket_mFCBGA479/Kconfig b/src/cpu/intel/socket_mFCBGA479/Kconfig
deleted file mode 100644
index 7450854..0000000
--- a/src/cpu/intel/socket_mFCBGA479/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-config CPU_INTEL_SOCKET_MFCBGA479
- bool
- select CPU_INTEL_MODEL_6BX
- select MMX
- select SSE
-
-if CPU_INTEL_SOCKET_MFCBGA479
-
-config DCACHE_RAM_BASE
- hex
- default 0xc8000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x08000
-
-endif
diff --git a/src/cpu/intel/socket_mFCBGA479/Makefile.inc b/src/cpu/intel/socket_mFCBGA479/Makefile.inc
deleted file mode 100644
index 918a54e..0000000
--- a/src/cpu/intel/socket_mFCBGA479/Makefile.inc
+++ /dev/null
@@ -1,10 +0,0 @@
-subdirs-y += ../model_6bx
-subdirs-y += ../../x86/tsc
-subdirs-y += ../../x86/mtrr
-subdirs-y += ../../x86/lapic
-subdirs-y += ../../x86/cache
-subdirs-y += ../../x86/smm
-subdirs-y += ../microcode
-
-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc
-romstage-y += ../car/romstage_legacy.c
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index ed556db..d535aa3 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -23,8 +23,6 @@
// here.
#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)
-#include "../../../southbridge/intel/i82801dx/i82801dx.h"
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)
#include "../../../southbridge/intel/i82801ix/i82801ix.h"
#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 28298d5..99eedab 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -605,23 +605,6 @@
help
The path and filename of the VBT binary.
-config INTEL_MBI
- bool "Add an MBI image"
- depends on NORTHBRIDGE_INTEL_I82830
- help
- Select this option if you have an Intel MBI image that you would
- like to add to your ROM.
-
- You will be able to specify the location and file name of the
- image later.
-
-config MBI_FILE
- string "Intel MBI path and filename"
- depends on INTEL_MBI
- default "mbi.bin"
- help
- The path and filename of the file to use as VGA BIOS.
-
config SOFTWARE_I2C
bool "Enable I2C controller emulation in software"
default n
diff --git a/src/mainboard/rca/Kconfig b/src/mainboard/rca/Kconfig
deleted file mode 100644
index d5728f2..0000000
--- a/src/mainboard/rca/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_RCA
-
-choice
- prompt "Mainboard model"
-
-source "src/mainboard/rca/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/rca/*/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "RCA"
-
-endif # VENDOR_RCA
diff --git a/src/mainboard/rca/Kconfig.name b/src/mainboard/rca/Kconfig.name
deleted file mode 100644
index 3534996..0000000
--- a/src/mainboard/rca/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_RCA
- bool "RCA"
diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig
deleted file mode 100644
index 81cfc7b..0000000
--- a/src/mainboard/rca/rm4100/Kconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-if BOARD_RCA_RM4100
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_SOCKET_MFCBGA479
- select NORTHBRIDGE_INTEL_I82830
- select SOUTHBRIDGE_INTEL_I82801DX
- select SUPERIO_SMSC_SMSCSUPERIO
- select HAVE_PIRQ_TABLE
- select BOARD_ROMSIZE_KB_1024
-
-config MAINBOARD_DIR
- string
- default rca/rm4100
-
-config MAINBOARD_PART_NUMBER
- string
- default "RM4100"
-
-config IRQ_SLOT_COUNT
- int
- default 7
-
-endif # BOARD_RCA_RM4100
diff --git a/src/mainboard/rca/rm4100/Kconfig.name b/src/mainboard/rca/rm4100/Kconfig.name
deleted file mode 100644
index fd737ab..0000000
--- a/src/mainboard/rca/rm4100/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_RCA_RM4100
- bool "RM4100"
diff --git a/src/mainboard/rca/rm4100/board_info.txt b/src/mainboard/rca/rm4100/board_info.txt
deleted file mode 100644
index 0c06a7d..0000000
--- a/src/mainboard/rca/rm4100/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: settop
-Board URL: http://www.settoplinux.org/index.php?title=RCA_RM4100
-Flashrom support: y
diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb
deleted file mode 100644
index 7c31423..0000000
--- a/src/mainboard/rca/rm4100/devicetree.cb
+++ /dev/null
@@ -1,67 +0,0 @@
-chip northbridge/intel/i82830 # Northbridge
- device cpu_cluster 0 on # APIC cluster
- chip cpu/intel/socket_mFCBGA479 # Mobile Celeron Micro-FCBGA Socket 479
- device lapic 0 on end # APIC
- end
- end
- device domain 0 on # PCI domain
- device pci 0.0 on end # Host bridge
- device pci 2.0 on end # VGA (Intel 82830 CGC)
- chip southbridge/intel/i82801dx # Southbridge
- register "pirqa_routing" = "0x05"
- register "pirqb_routing" = "0x06"
- register "pirqc_routing" = "0x07"
- register "pirqd_routing" = "0x09"
- register "pirqe_routing" = "0x0a"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x0b"
-
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
-
- device pci 1d.0 on end # USB UHCI Controller #1
- device pci 1d.1 on end # USB UHCI Controller #2
- device pci 1d.2 on end # USB UHCI Controller #3
- device pci 1d.7 on end # USB2 EHCI Controller
- device pci 1e.0 on end # PCI bridge
- device pci 1f.0 on # ISA/LPC bridge
- chip superio/smsc/smscsuperio # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 4
- end
- device pnp 2e.4 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 on # Com2 / IR
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.7 on # PS/2 keyboard/mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # Keyboard interrupt
- irq 0x72 = 12 # Mouse interrupt
- end
- device pnp 2e.9 off end # Game port
- device pnp 2e.a on # PME
- io 0x60 = 0x800
- end
- device pnp 2e.b off end # MPU-401
- end
- end
- device pci 1f.1 on end # IDE
- device pci 1f.3 on end # SMBus
- device pci 1f.5 on end # AC'97 audio
- device pci 1f.6 on end # AC'97 modem
- end
- end
-end
diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c
deleted file mode 100644
index 168bb09..0000000
--- a/src/mainboard/rca/rm4100/gpio.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-
-#define PME_DEV PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
-#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
- pci_devfn_t dev;
- uint16_t port;
- uint32_t set_gpio;
-
- /* Southbridge GPIOs. */
- /* Set the LPC device statically. */
- dev = PCI_DEV(0x0, 0x1f, 0x0);
-
- /* Set the value for GPIO base address register and enable GPIO. */
- pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
- pci_write_config8(dev, GPIO_CNTL, 0x10);
-
- /* Set GPIO23 to high, this enables the LAN controller. */
- udelay(10);
- set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
- set_gpio |= 1 << 23;
- outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
- /* Super I/O GPIOs. */
- dev = PME_DEV;
- port = dev >> 8;
-
- /* Enter the configuration state. */
- outb(0x55, port);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
- pnp_set_enable(dev, 1);
-
- /* GP21 - LED_RED */
- outl(0x01, PME_IO_BASE_ADDR + 0x2c);
-
- /* GP30 - FAN2_TACH */
- outl(0x05, PME_IO_BASE_ADDR + 0x33);
-
- /* GP31 - FAN1_TACH */
- outl(0x05, PME_IO_BASE_ADDR + 0x34);
-
- /* GP32 - FAN2_CTRL */
- outl(0x04, PME_IO_BASE_ADDR + 0x35);
-
- /* GP33 - FAN1_CTRL */
- outl(0x04, PME_IO_BASE_ADDR + 0x36);
-
- /* GP34 - AUD_MUTE_OUT_R */
- outl(0x00, PME_IO_BASE_ADDR + 0x37);
-
- /* GP36 - KBRST */
- outl(0x00, PME_IO_BASE_ADDR + 0x39);
-
- /* GP37 - A20GATE */
- outl(0x00, PME_IO_BASE_ADDR + 0x3a);
-
- /* GP42 - GPIO_PME_OUT */
- outl(0x00, PME_IO_BASE_ADDR + 0x3d);
-
- /* GP50 - SER2_RI */
- outl(0x05, PME_IO_BASE_ADDR + 0x3f);
-
- /* GP51 - SER2_DCD */
- outl(0x05, PME_IO_BASE_ADDR + 0x40);
-
- /* GP52 - SER2_RX */
- outl(0x05, PME_IO_BASE_ADDR + 0x41);
-
- /* GP53 - SER2_TX */
- outl(0x04, PME_IO_BASE_ADDR + 0x42);
-
- /* GP55 - SER2_RTS */
- outl(0x04, PME_IO_BASE_ADDR + 0x44);
-
- /* GP56 - SER2_CTS */
- outl(0x05, PME_IO_BASE_ADDR + 0x45);
-
- /* GP57 - SER2_DTR */
- outl(0x04, PME_IO_BASE_ADDR + 0x46);
-
- /* GP60 - LED_GREEN */
- outl(0x01, PME_IO_BASE_ADDR + 0x47);
-
- /* GP61 - LED_YELLOW */
- outl(0x01, PME_IO_BASE_ADDR + 0x48);
-
- /* GP3 */
- outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
-
- /* GP4 */
- outl(0x04, PME_IO_BASE_ADDR + 0x4e);
-
- /* FAN1 */
- outl(0x01, PME_IO_BASE_ADDR + 0x56);
-
- /* FAN2 */
- outl(0x01, PME_IO_BASE_ADDR + 0x57);
-
- /* Fan Control */
- outl(0x50, PME_IO_BASE_ADDR + 0x58);
-
- /* Fan1 Tachometer */
- outl(0xff, PME_IO_BASE_ADDR + 0x59);
-
- /* Fan2 Tachometer */
- outl(0xff, PME_IO_BASE_ADDR + 0x5a);
-
- /* LED1 */
- outl(0x00, PME_IO_BASE_ADDR + 0x5d);
-
- /* LED2 */
- outl(0x00, PME_IO_BASE_ADDR + 0x5e);
-
- /* Keyboard Scan Code */
- outl(0x00, PME_IO_BASE_ADDR + 0x5f);
-
- /* Exit the configuration state. */
- outb(0xaa, port);
-}
diff --git a/src/mainboard/rca/rm4100/irq_tables.c b/src/mainboard/rca/rm4100/irq_tables.c
deleted file mode 100644
index e99adfc..0000000
--- a/src/mainboard/rca/rm4100/irq_tables.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x24c0, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x07, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
- {0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
- {0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
- {0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
- {0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
- {0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
- {0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
deleted file mode 100644
index 43c518f..0000000
--- a/src/mainboard/rca/rm4100/romstage.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <lib.h>
-#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include <northbridge/intel/i82830/raminit.h>
-#include "northbridge/intel/i82830/memory_initialized.c"
-#include <southbridge/intel/i82801dx/i82801dx.h>
-#include "southbridge/intel/i82801dx/reset.c"
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include "spd_table.h"
-#include "gpio.c"
-#include "southbridge/intel/i82801dx/tco_timer.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
-/**
- * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
- * values have to be set manually, the SO-DIMM socket is located in
- * socket0 (0x50/DIMM0), and the onboard memory is located in socket1
- * (0x51/DIMM1).
- */
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- int i;
-
- if (device == DIMM0) {
- return smbus_read_byte(device, address);
- } else if (device == DIMM1) {
- for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
- if (spd_table[i].address == address)
- return spd_table[i].data;
- }
- return 0xFF; /* Return 0xFF when address is not found. */
- } else {
- return 0xFF; /* Return 0xFF on any failures. */
- }
-}
-
-#include "northbridge/intel/i82830/raminit.c"
-
-/**
- * Setup mainboard specific registers pre raminit.
- */
-static void mb_early_setup(void)
-{
- /* - Hub Interface to PCI Bridge Registers - */
- /* 12-Clock Retry Enable */
- pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
- /* Master Latency Timer Count */
- pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
- /* I/O Address Base */
- pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
-
- /* - LPC Interface Bridge Registers - */
- /* Delayed Transaction Enable */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
- /* Disable the TCO Timer system reboot feature */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
- /* CPU Frequency Strap */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
- /* ACPI base address and enable Resource Indicator */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
- /* Enable the SMBUS */
- enable_smbus();
- /* ACPI base address and disable Resource Indicator */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));
- /* ACPI Enable */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
- if (bist == 0) {
- if (memory_initialized())
- hard_reset();
- }
-
- /* Set southbridge and superio gpios */
- mb_gpio_init();
-
- smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
-
- /* disable TCO timers */
- i82801dx_halt_tco_timer();
-
- /* Setup mainboard specific registers */
- mb_early_setup();
-
- /* Initialize memory */
- sdram_initialize();
-}
diff --git a/src/mainboard/rca/rm4100/smihandler.c b/src/mainboard/rca/rm4100/smihandler.c
deleted file mode 100644
index a8a7aca..0000000
--- a/src/mainboard/rca/rm4100/smihandler.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-
-int mainboard_io_trap_handler(int smif)
-{
- printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
- return 1;
-}
diff --git a/src/mainboard/rca/rm4100/spd_table.h b/src/mainboard/rca/rm4100/spd_table.h
deleted file mode 100644
index 14bc85b..0000000
--- a/src/mainboard/rca/rm4100/spd_table.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <spd.h>
-
-struct spd_entry {
- unsigned int address;
- unsigned int data;
-};
-
-/*
- * The onboard 128MB PC133 memory does not have an SPD EEPROM so the values
- * have to be set manually, the onboard memory is located in socket1 (0x51).
- */
-const struct spd_entry spd_table [] = {
- {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */
- {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */
- {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */
- {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */
- {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
- {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
- {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */
-};
diff --git a/src/mainboard/thomson/Kconfig b/src/mainboard/thomson/Kconfig
deleted file mode 100644
index e439ba7..0000000
--- a/src/mainboard/thomson/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_THOMSON
-
-choice
- prompt "Mainboard model"
-
-source "src/mainboard/thomson/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/thomson/*/Kconfig"
-
-config MAINBOARD_VENDOR
- string
- default "Thomson"
-
-endif # VENDOR_THOMSON
diff --git a/src/mainboard/thomson/Kconfig.name b/src/mainboard/thomson/Kconfig.name
deleted file mode 100644
index b22bbbb..0000000
--- a/src/mainboard/thomson/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config VENDOR_THOMSON
- bool "Thomson"
diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig
deleted file mode 100644
index 1c21ace..0000000
--- a/src/mainboard/thomson/ip1000/Kconfig
+++ /dev/null
@@ -1,36 +0,0 @@
-if BOARD_THOMSON_IP1000
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_SOCKET_MFCBGA479
- select NORTHBRIDGE_INTEL_I82830
- select SOUTHBRIDGE_INTEL_I82801DX
- select SUPERIO_SMSC_SMSCSUPERIO
- select HAVE_PIRQ_TABLE
- select BOARD_ROMSIZE_KB_512
- select INTEL_INT15
-
-config MAINBOARD_DIR
- string
- default thomson/ip1000
-
-config MAINBOARD_PART_NUMBER
- string
- default "IP1000"
-
-config IRQ_SLOT_COUNT
- int
- default 7
-
-choice
- prompt "IP1000 Onboard Memory"
- default ONBOARD_MEMORY_64MB
-
-config ONBOARD_MEMORY_64MB
- bool "IP1000-64MB"
-config ONBOARD_MEMORY_128MB
- bool "IP1000T-128MB"
-
-endchoice
-
-endif # BOARD_THOMSON_IP1000
diff --git a/src/mainboard/thomson/ip1000/Kconfig.name b/src/mainboard/thomson/ip1000/Kconfig.name
deleted file mode 100644
index ad3d884..0000000
--- a/src/mainboard/thomson/ip1000/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_THOMSON_IP1000
- bool "IP1000"
diff --git a/src/mainboard/thomson/ip1000/board_info.txt b/src/mainboard/thomson/ip1000/board_info.txt
deleted file mode 100644
index 77f0895..0000000
--- a/src/mainboard/thomson/ip1000/board_info.txt
+++ /dev/null
@@ -1,3 +0,0 @@
-Category: settop
-Board URL: http://www.settoplinux.org/index.php?title=Thomson_IP1000
-Flashrom support: y
diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb
deleted file mode 100644
index 2f8903e..0000000
--- a/src/mainboard/thomson/ip1000/devicetree.cb
+++ /dev/null
@@ -1,68 +0,0 @@
-chip northbridge/intel/i82830 # Northbridge
- device cpu_cluster 0 on # APIC cluster
- chip cpu/intel/socket_mFCBGA479 # Low Voltage PIII Micro-FCBGA Socket 479
- device lapic 0 on end # APIC
- end
- end
-
- device domain 0 on # PCI domain
- device pci 0.0 on end # Host bridge
- device pci 2.0 on end # VGA (Intel 82830 CGC)
- chip southbridge/intel/i82801dx # Southbridge
- register "pirqa_routing" = "0x05"
- register "pirqb_routing" = "0x06"
- register "pirqc_routing" = "0x07"
- register "pirqd_routing" = "0x09"
- register "pirqe_routing" = "0x0a"
- register "pirqf_routing" = "0x80"
- register "pirqg_routing" = "0x80"
- register "pirqh_routing" = "0x0b"
-
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
-
- device pci 1d.0 on end # USB UHCI Controller #1
- device pci 1d.1 on end # USB UHCI Controller #2
- device pci 1d.2 on end # USB UHCI Controller #3
- device pci 1d.7 on end # USB2 EHCI Controller
- device pci 1e.0 on end # PCI bridge
- device pci 1f.0 on # ISA/LPC bridge
- chip superio/smsc/smscsuperio # Super I/O
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 4
- end
- device pnp 2e.4 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 on # Com2 / IR
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.7 on # PS/2 keyboard/mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # Keyboard interrupt
- irq 0x72 = 12 # Mouse interrupt
- end
- device pnp 2e.9 off end # Game port
- device pnp 2e.a on # PME
- io 0x60 = 0x800
- end
- device pnp 2e.b off end # MPU-401
- end
- end
- device pci 1f.1 on end # IDE
- device pci 1f.3 on end # SMBus
- device pci 1f.5 on end # AC'97 audio
- device pci 1f.6 off end # AC'97 modem
- end
- end
-end
diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c
deleted file mode 100644
index b4bf30e..0000000
--- a/src/mainboard/thomson/ip1000/gpio.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-
-#define PME_DEV PNP_DEV(0x2e, 0x0a)
-#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
-#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
- pci_devfn_t dev;
- uint16_t port;
- uint32_t set_gpio;
-
- /* Southbridge GPIOs. */
- /* Set the LPC device statically. */
- dev = PCI_DEV(0x0, 0x1f, 0x0);
-
- /* Set the value for GPIO base address register and enable GPIO. */
- pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));
- pci_write_config8(dev, GPIO_CNTL, 0x10);
-
- /* Set GPIO23 to high, this enables the LAN controller. */
- udelay(10);
- set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);
- set_gpio |= 1 << 23;
- outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);
-
- /* Disable AC97 Modem */
- pci_write_config8(dev, 0xf2, 0x40);
-
- /* Super I/O GPIOs. */
- dev = PME_DEV;
- port = dev >> 8;
-
- /* Enter the configuration state. */
- outb(0x55, port);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
- pnp_set_enable(dev, 1);
-
- /* GP21 - LED_RED */
- outl(0x01, PME_IO_BASE_ADDR + 0x2c);
-
- /* GP30 - FAN2_TACH */
- outl(0x05, PME_IO_BASE_ADDR + 0x33);
-
- /* GP31 - FAN1_TACH */
- outl(0x05, PME_IO_BASE_ADDR + 0x34);
-
- /* GP32 - FAN2_CTRL */
- outl(0x04, PME_IO_BASE_ADDR + 0x35);
-
- /* GP33 - FAN1_CTRL */
- outl(0x04, PME_IO_BASE_ADDR + 0x36);
-
- /* GP34 - AUD_MUTE_OUT_R */
- outl(0x00, PME_IO_BASE_ADDR + 0x37);
-
- /* GP36 - KBRST */
- outl(0x00, PME_IO_BASE_ADDR + 0x39);
-
- /* GP37 - A20GATE */
- outl(0x00, PME_IO_BASE_ADDR + 0x3a);
-
- /* GP42 - GPIO_PME_OUT */
- outl(0x00, PME_IO_BASE_ADDR + 0x3d);
-
- /* GP50 - SER2_RI */
- outl(0x05, PME_IO_BASE_ADDR + 0x3f);
-
- /* GP51 - SER2_DCD */
- outl(0x05, PME_IO_BASE_ADDR + 0x40);
-
- /* GP52 - SER2_RX */
- outl(0x05, PME_IO_BASE_ADDR + 0x41);
-
- /* GP53 - SER2_TX */
- outl(0x04, PME_IO_BASE_ADDR + 0x42);
-
- /* GP55 - SER2_RTS */
- outl(0x04, PME_IO_BASE_ADDR + 0x44);
-
- /* GP56 - SER2_CTS */
- outl(0x05, PME_IO_BASE_ADDR + 0x45);
-
- /* GP57 - SER2_DTR */
- outl(0x04, PME_IO_BASE_ADDR + 0x46);
-
- /* GP60 - LED_GREEN */
- outl(0x01, PME_IO_BASE_ADDR + 0x47);
-
- /* GP61 - LED_YELLOW */
- outl(0x01, PME_IO_BASE_ADDR + 0x48);
-
- /* GP3 */
- outl(0xc0, PME_IO_BASE_ADDR + 0x4d);
-
- /* GP4 */
- outl(0x04, PME_IO_BASE_ADDR + 0x4e);
-
- /* FAN1 */
- outl(0x01, PME_IO_BASE_ADDR + 0x56);
-
- /* FAN2 */
- outl(0x01, PME_IO_BASE_ADDR + 0x57);
-
- /* Fan Control */
- outl(0x50, PME_IO_BASE_ADDR + 0x58);
-
- /* Fan1 Tachometer */
- outl(0xff, PME_IO_BASE_ADDR + 0x59);
-
- /* Fan2 Tachometer */
- outl(0xff, PME_IO_BASE_ADDR + 0x5a);
-
- /* LED1 */
- outl(0x00, PME_IO_BASE_ADDR + 0x5d);
-
- /* LED2 */
- outl(0x00, PME_IO_BASE_ADDR + 0x5e);
-
- /* Keyboard Scan Code */
- outl(0x00, PME_IO_BASE_ADDR + 0x5f);
-
- /* Exit the configuration state. */
- outb(0xaa, port);
-}
diff --git a/src/mainboard/thomson/ip1000/irq_tables.c b/src/mainboard/thomson/ip1000/irq_tables.c
deleted file mode 100644
index e99adfc..0000000
--- a/src/mainboard/thomson/ip1000/irq_tables.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x8086, /* Vendor */
- 0x24c0, /* Device */
- 0, /* Miniport data */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x07, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */
- {0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */
- {0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */
- {0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */
- {0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */
- {0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */
- {0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c
deleted file mode 100644
index bdcc1fa..0000000
--- a/src/mainboard/thomson/ip1000/mainboard.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe at settoplinux.org>
- * Copyright (C) 2010 Stefan Reinauer <stepan at openbios.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <delay.h>
-#include <drivers/intel/gma/int15.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
-
-// setting the bit disables the led.
-#define PARPORT_GPIO_LED_GREEN (1 << 0)
-#define PARPORT_GPIO_LED_ORANGE (1 << 1)
-#define PARPORT_GPIO_LED_RED (1 << 2)
-#define PARPORT_GPIO_IR_PORT (1 << 6)
-
-static u8 get_parport_gpio(void)
-{
- return inb(0x378);
-}
-
-static void set_parport_gpio(u8 gpios)
-{
- outb(gpios, 0x378);
-}
-
-static void parport_gpios(void)
-{
- u8 pp_gpios = get_parport_gpio();
-
- /* disable red led */
- pp_gpios |= PARPORT_GPIO_LED_RED;
- set_parport_gpio(pp_gpios);
-
- pp_gpios = get_parport_gpio();
-
- printk(BIOS_DEBUG, "IP1000 GPIOs:\n");
- printk(BIOS_DEBUG, " GPIO mask: %02x\n", pp_gpios);
- printk(BIOS_DEBUG, " green led: %s\n",
- (pp_gpios & PARPORT_GPIO_LED_GREEN) ? "off" : "on");
- printk(BIOS_DEBUG, " orange led: %s\n",
- (pp_gpios & PARPORT_GPIO_LED_ORANGE) ? "off" : "on");
- printk(BIOS_DEBUG, " red led: %s\n",
- (pp_gpios & PARPORT_GPIO_LED_RED) ? "off" : "on");
- printk(BIOS_DEBUG, " IR port: %s\n",
- (pp_gpios & PARPORT_GPIO_IR_PORT) ? "off" : "on");
-}
-
-static void flash_gpios(void)
-{
- u8 manufacturer_id = read8((u8 *)0xffbc0000);
- u8 device_id = read8((u8 *)0xffbc0001);
-
- if ((manufacturer_id == 0x20) &&
- ((device_id == 0x2c) || (device_id == 0x2d))) {
- printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n",
- (device_id == 0x2c)?'4':'8');
- u8 fgpi = read8((u8 *)0xffbc0100);
- printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n",
- (fgpi & (1 << 0)) ? 'X' : ' ',
- (fgpi & (1 << 1)) ? 'X' : ' ',
- (fgpi & (1 << 2)) ? 'X' : ' ',
- (fgpi & (1 << 3)) ? 'X' : ' ',
- (fgpi & (1 << 4)) ? 'X' : ' ');
- } else {
- printk(BIOS_DEBUG, "No ST M50FW040/M50FW080 flash, don't read FGPI.\n");
- }
-}
-
-static void mainboard_init(device_t dev)
-{
- parport_gpios();
- flash_gpios();
-}
-
-static void mainboard_enable(device_t dev)
-{
- dev->ops->init = mainboard_init;
- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c
deleted file mode 100644
index 9ad1225..0000000
--- a/src/mainboard/thomson/ip1000/romstage.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <lib.h>
-#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include <northbridge/intel/i82830/raminit.h>
-#include "northbridge/intel/i82830/memory_initialized.c"
-#include <southbridge/intel/i82801dx/i82801dx.h>
-#include "southbridge/intel/i82801dx/reset.c"
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include "spd_table.h"
-#include "gpio.c"
-#include "southbridge/intel/i82801dx/tco_timer.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
-/**
- * The onboard 64MB PC133 memory does not have a SPD EEPROM so the
- * values have to be set manually, the SO-DIMM socket is located in
- * socket0 (0x50/DIMM0), and the onboard memory is located in socket1
- * (0x51/DIMM1).
- */
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- int i;
-
- if (device == DIMM0) {
- return smbus_read_byte(device, address);
- } else if (device == DIMM1) {
- for (i = 0; i < ARRAY_SIZE(spd_table); i++) {
- if (spd_table[i].address == address)
- return spd_table[i].data;
- }
- return 0xFF; /* Return 0xFF when address is not found. */
- } else {
- return 0xFF; /* Return 0xFF on any failures. */
- }
-}
-
-#include "northbridge/intel/i82830/raminit.c"
-
-/**
- * Setup mainboard specific registers pre raminit.
- */
-static void mb_early_setup(void)
-{
- /* - Hub Interface to PCI Bridge Registers - */
- /* 12-Clock Retry Enable */
- pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);
- /* Master Latency Timer Count */
- pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
- /* I/O Address Base */
- pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);
-
- /* - LPC Interface Bridge Registers - */
- /* Delayed Transaction Enable */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);
- /* Disable the TCO Timer system reboot feature */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);
- /* CPU Frequency Strap */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);
- /* ACPI base address and enable Resource Indicator */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));
- /* Enable the SMBUS */
- enable_smbus();
- /* ACPI Enable */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
- if (bist == 0) {
- if (memory_initialized())
- hard_reset();
- }
-
- /* Set southbridge and superio gpios */
- mb_gpio_init();
-
- smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure. */
- report_bist_failure(bist);
-
- /* disable TCO timers */
- i82801dx_halt_tco_timer();
-
- /* Setup mainboard specific registers */
- mb_early_setup();
-
- /* Initialize memory */
- sdram_initialize();
-}
diff --git a/src/mainboard/thomson/ip1000/smihandler.c b/src/mainboard/thomson/ip1000/smihandler.c
deleted file mode 100644
index a8a7aca..0000000
--- a/src/mainboard/thomson/ip1000/smihandler.c
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-
-int mainboard_io_trap_handler(int smif)
-{
- printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");
- return 1;
-}
diff --git a/src/mainboard/thomson/ip1000/spd_table.h b/src/mainboard/thomson/ip1000/spd_table.h
deleted file mode 100644
index 1de05ed..0000000
--- a/src/mainboard/thomson/ip1000/spd_table.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <spd.h>
-
-#if IS_ENABLED(CONFIG_ONBOARD_MEMORY_64MB)
-
-#define DENSITY 0x10
-
-#elif IS_ENABLED(CONFIG_ONBOARD_MEMORY_128MB)
-
-#define DENSITY 0x20
-
-#endif
-
-struct spd_entry {
- unsigned int address;
- unsigned int data;
-};
-
-/*
- * The onboard 64MB PC133 memory does not have an SPD EEPROM so the values
- * have to be set manually, the onboard memory is located in socket1 (0x51).
- */
-const struct spd_entry spd_table [] = {
- {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */
- {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */
- {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */
- {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */
- {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */
- {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */
- {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, DENSITY}, /* Density of each row on module */
-};
diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig
deleted file mode 100644
index d0bee8f..0000000
--- a/src/northbridge/intel/i82830/Kconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-config NORTHBRIDGE_INTEL_I82830
- bool
- select NO_MMCONF_SUPPORT
- select HAVE_DEBUG_RAM_SETUP
- select LATE_CBMEM_INIT
- select UDELAY_IO
-
-choice
- prompt "Onboard graphics"
- default I830_VIDEO_MB_8MB
- depends on NORTHBRIDGE_INTEL_I82830
-
-config I830_VIDEO_MB_OFF
- bool "Disabled, 0KB"
-config I830_VIDEO_MB_512KB
- bool "Enabled, 512KB"
-config I830_VIDEO_MB_1MB
- bool "Enabled, 1MB"
-config I830_VIDEO_MB_8MB
- bool "Enabled, 8MB"
-
-endchoice
-
-config VIDEO_MB
- int
- default 0 if I830_VIDEO_MB_OFF
- default 512 if I830_VIDEO_MB_512KB
- default 1 if I830_VIDEO_MB_1MB
- default 8 if I830_VIDEO_MB_8MB
- depends on NORTHBRIDGE_INTEL_I82830
diff --git a/src/northbridge/intel/i82830/Makefile.inc b/src/northbridge/intel/i82830/Makefile.inc
deleted file mode 100644
index ebbae81..0000000
--- a/src/northbridge/intel/i82830/Makefile.inc
+++ /dev/null
@@ -1,8 +0,0 @@
-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I82830),y)
-
-ramstage-y += northbridge.c
-ramstage-y += vga.c
-
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-endif
diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h
deleted file mode 100644
index a4b0a86..0000000
--- a/src/northbridge/intel/i82830/i82830.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at smittys.pointclark.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef NORTHBRIDGE_INTEL_I82830_I82830_H
-#define NORTHBRIDGE_INTEL_I82830_I82830_H
-
-#define RRBAR 0x48 /* Register Range Base Address (0x00000000) */
-#define GCC0 0x50 /* GMCH Control #0 (0xa072) */
-#define GCC1 0x52 /* GMCH Control #1 (0x0000) */
-#define FDHC 0x58 /* Fixed DRAM Hole Control (0x00) */
-#define PAM0 0x59 /* Programmable Attribute Map #0 (0x00) */
-#define PAM1 0x5a /* Programmable Attribute Map #1 (0x00) */
-#define PAM2 0x5b /* Programmable Attribute Map #2 (0x00) */
-#define PAM3 0x5c /* Programmable Attribute Map #3 (0x00) */
-#define PAM4 0x5d /* Programmable Attribute Map #4 (0x00) */
-#define PAM5 0x5e /* Programmable Attribute Map #5 (0x00) */
-#define PAM6 0x5f /* Programmable Attribute Map #6 (0x00) */
-#define DRB 0x60 /* DRAM Row Boundary #0 (0x00) */
-#define DRB1 0x61 /* DRAM Row Boundary #1 (0x00) */
-#define DRB2 0x62 /* DRAM Row Boundary #2 (0x00) */
-#define DRB3 0x63 /* DRAM Row Boundary #3 (0x00) */
-#define DRA 0x70 /* DRAM Row Attribute #0 (0xff) */
-#define DRA1 0x71 /* DRAM Row Attribute #1 (0xff) */
-#define DRT 0x78 /* DRAM Timing (0x00000010) */
-#define DRC 0x7c /* DRAM Controller Mode #0 (0x00000000) */
-#define DRC1 0x7d /* DRAM Controller Mode #1 (0x00000000) */
-#define DRC2 0x7e /* DRAM Controller Mode #2 (0x00000000) */
-#define DRC3 0x7f /* DRAM Controller Mode #3 (0x00000000) */
-#define DTC 0x8c /* DRAM Throttling Control (0x00000000) */
-#define SMRAM 0x90 /* System Management RAM Control (0x02) */
-#define ESMRAMC 0x91 /* Extended System Management RAM Control Reg. (0x38) */
-#define ERRSTS 0x92 /* Error Status (0x0000) */
-#define ERRCMD 0x94 /* Error Command (0x0000) */
-#define BUFF_SC 0xec /* System Memory Buffer Strength Control (0x00000000) */
-#define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */
-#define APSIZE 0xb4 /* Aperture Size (0x00) */
-#define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */
-
-#endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */
diff --git a/src/northbridge/intel/i82830/memory_initialized.c b/src/northbridge/intel/i82830/memory_initialized.c
deleted file mode 100644
index 7ccc1a6..0000000
--- a/src/northbridge/intel/i82830/memory_initialized.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include "i82830.h"
-#define NB_DEV PCI_DEV(0, 0, 0)
-
-static inline int memory_initialized(void)
-{
- u32 drc;
- drc = pci_read_config32(NB_DEV, DRC);
- return (drc & (1<<29));
-}
diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c
deleted file mode 100644
index ce9a3fb..0000000
--- a/src/northbridge/intel/i82830/northbridge.c
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cbmem.h>
-#include <cpu/cpu.h>
-#include <stdlib.h>
-#include <string.h>
-#include "i82830.h"
-
-static void northbridge_init(device_t dev)
-{
- printk(BIOS_SPEW, "Northbridge init\n");
-}
-
-static struct device_operations northbridge_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = northbridge_init,
- .enable = 0,
- .ops_pci = 0,
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &northbridge_operations,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x3575,
-};
-
-static void pci_domain_set_resources(device_t dev)
-{
- device_t mc_dev;
- int igd_memory = 0;
- uint64_t uma_memory_base = 0, uma_memory_size = 0;
-
- mc_dev = dev->link_list->children;
- if (!mc_dev)
- return;
-
- unsigned long tomk, tomk_stolen;
- int idx;
-
- if (CONFIG_VIDEO_MB == 512) {
- igd_memory = (CONFIG_VIDEO_MB);
- printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);
- } else {
- igd_memory = (CONFIG_VIDEO_MB * 1024);
- printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);
- }
-
- /* Get the value of the highest DRB. This tells the end of
- * the physical memory. The units are ticks of 32MB
- * i.e. 1 means 32MB.
- */
- tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;
- tomk_stolen = tomk - igd_memory;
-
- /* For reserving UMA memory in the memory map */
- uma_memory_base = tomk_stolen * 1024ULL;
- uma_memory_size = igd_memory * 1024ULL;
- printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk_stolen);
-
- /* Report the memory regions. */
- idx = 10;
- ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 768, tomk - 768);
- uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10);
-
- assign_resources(dev->link_list);
-
- set_late_cbmem_top(tomk_stolen * 1024);
-}
-
-static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
- .ops_pci_bus = pci_bus_default_ops,
-};
-
-static void cpu_bus_init(device_t dev)
-{
- initialize_cpus(dev->link_list);
-}
-
-static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- struct device_path;
-
- /* Set the operations if it is a special bus type. */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
-}
-
-struct chip_operations northbridge_intel_i82830_ops = {
- CHIP_NAME("Intel 82830 Northbridge")
- .enable_dev = enable_dev,
-};
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
deleted file mode 100644
index e0f2c6e..0000000
--- a/src/northbridge/intel/i82830/raminit.c
+++ /dev/null
@@ -1,508 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <spd.h>
-#include <delay.h>
-#include "lib/debug.c"
-#include "i82830.h"
-
-/*-----------------------------------------------------------------------------
-Macros and definitions.
------------------------------------------------------------------------------*/
-
-/* Debugging macros. */
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
-#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)
-#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
-#else
-#define PRINTK_DEBUG(x...)
-#define DUMPNORTH()
-#endif
-
-/* DRC[10:8] - Refresh Mode Select (RMS).
- * 0x0 for Refresh Disabled (Self Refresh)
- * 0x1 for Refresh interval 15.6 us for 133MHz
- * 0x2 for Refresh interval 7.8 us for 133MHz
- * 0x7 for Refresh interval 128 Clocks. (Fast Refresh Mode)
- */
-#define RAM_COMMAND_REFRESH 0x1
-
-/* DRC[6:4] - SDRAM Mode Select (SMS). */
-#define RAM_COMMAND_SELF_REFRESH 0x0
-#define RAM_COMMAND_NOP 0x1
-#define RAM_COMMAND_PRECHARGE 0x2
-#define RAM_COMMAND_MRS 0x3
-#define RAM_COMMAND_CBR 0x6
-#define RAM_COMMAND_NORMAL 0x7
-
-/* DRC[29] - Initialization Complete (IC). */
-#define RAM_COMMAND_IC 0x1
-
-/*-----------------------------------------------------------------------------
-DIMM-initialization functions.
------------------------------------------------------------------------------*/
-
-static void do_ram_command(u32 command)
-{
- u32 reg32;
-
- /* Configure the RAM command. */
- reg32 = pci_read_config32(NORTHBRIDGE, DRC);
- /* Clear bits 29, 10-8, 6-4. */
- reg32 &= 0xdffff88f;
- reg32 |= command << 4;
- PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32);
- pci_write_config32(NORTHBRIDGE, DRC, reg32);
-}
-
-static void ram_read32(u8 dimm_start, u32 offset)
-{
- u32 reg32, base_addr = 32 * 1024 * 1024 * dimm_start;
- if (offset == 0x55aa55aa) {
- reg32 = read32((u32 *)base_addr);
- PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
- PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", base_addr, offset);
- write32((u32 *)base_addr, offset);
- reg32 = read32((u32 *)base_addr);
- PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
- } else {
- PRINTK_DEBUG(" to 0x%08x\n", base_addr + offset);
- read32((u32 *)(base_addr + offset));
- }
-}
-
-static void initialize_dimm_rows(void)
-{
- int i, row;
- u8 dimm_start, dimm_end;
- unsigned device;
-
- dimm_start = 0;
-
- for (row = 0; row < (DIMM_SOCKETS * 2); row++) {
-
- switch (row) {
- case 0:
- device = DIMM0;
- break;
- case 1:
- device = DIMM0;
- break;
- case 2:
- device = DIMM0 + 1;
- break;
- case 3:
- device = DIMM0 + 1;
- break;
- }
-
- dimm_end = pci_read_config8(NORTHBRIDGE, DRB + row);
-
- if (dimm_end > dimm_start) {
- printk(BIOS_DEBUG, "Initializing SDRAM Row %u\n", row);
-
- /* NOP command */
- PRINTK_DEBUG(" NOP\n");
- do_ram_command(RAM_COMMAND_NOP);
- ram_read32(dimm_start, 0);
- udelay(200);
-
- /* Pre-charge all banks (at least 200 us after NOP) */
- PRINTK_DEBUG(" Pre-charging all banks\n");
- do_ram_command(RAM_COMMAND_PRECHARGE);
- ram_read32(dimm_start, 0);
- udelay(1);
-
- /* 8 CBR refreshes (Auto Refresh) */
- PRINTK_DEBUG(" 8 CBR refreshes\n");
- for (i = 0; i < 8; i++) {
- do_ram_command(RAM_COMMAND_CBR);
- ram_read32(dimm_start, 0);
- udelay(1);
- }
-
- /* MRS command */
- /* TODO: Set offset 0x1d0 according to DRT values */
- PRINTK_DEBUG(" MRS\n");
- do_ram_command(RAM_COMMAND_MRS);
- ram_read32(dimm_start, 0x1d0);
- udelay(2);
-
- /* Set GMCH-M Mode Select bits back to NORMAL operation mode */
- PRINTK_DEBUG(" Normal operation mode\n");
- do_ram_command(RAM_COMMAND_NORMAL);
- ram_read32(dimm_start, 0);
- udelay(1);
-
- /* Perform a dummy memory read/write cycle */
- PRINTK_DEBUG(" Performing dummy read/write\n");
- ram_read32(dimm_start, 0x55aa55aa);
- udelay(1);
- }
- /* Set the start of the next DIMM. */
- dimm_start = dimm_end;
- }
-}
-
-/*-----------------------------------------------------------------------------
-DIMM-independent configuration functions.
------------------------------------------------------------------------------*/
-
-struct dimm_size {
- unsigned int side1;
- unsigned int side2;
-};
-
-static struct dimm_size spd_get_dimm_size(unsigned device)
-{
- struct dimm_size sz;
- int i, module_density, dimm_banks;
- sz.side1 = 0;
- module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
- dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
-
- /* Find the size of side1. */
- /* Find the larger value. The larger value is always side1. */
- for (i = 512; i >= 0; i >>= 1) {
- if ((module_density & i) == i) {
- sz.side1 = i;
- break;
- }
- }
-
- /* Set to 0 in case it's single sided. */
- sz.side2 = 0;
-
- /* Test if it's a dual-sided DIMM. */
- if (dimm_banks > 1) {
- /* Test to see if there's a second value, if so it's asymmetrical. */
- if (module_density != i) {
- /* Find the second value, picking up where we left off. */
- /* i >>= 1 done initially to make sure we don't get the same value again. */
- for (i >>= 1; i >= 0; i >>= 1) {
- if (module_density == (sz.side1 | i)) {
- sz.side2 = i;
- break;
- }
- }
- /* If not, it's symmetrical */
- } else {
- sz.side2 = sz.side1;
- }
- }
-
- /* SPD byte 31 is the memory size divided by 4 so we
- * need to multiply by 4 to get the total size.
- */
- sz.side1 *= 4;
- sz.side2 *= 4;
- return sz;
-}
-
-static void set_dram_row_boundaries(void)
-{
- int i, value, drb1, drb2;
-
- for (i = 0; i < DIMM_SOCKETS; i++) {
- struct dimm_size sz;
- unsigned device;
- device = DIMM0 + i;
- drb1 = 0;
- drb2 = 0;
-
- /* First check if a DIMM is actually present. */
- if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
- printk(BIOS_DEBUG, "Found DIMM in slot %u\n", i);
- sz = spd_get_dimm_size(device);
- printk(BIOS_DEBUG, " DIMM is %uMB on side 1\n", sz.side1);
- printk(BIOS_DEBUG, " DIMM is %uMB on side 2\n", sz.side2);
-
- /* - Memory compatibility checks - */
-
- /* Test for PC133 (i82830 only supports PC133) */
- /* PC133 SPD9 - cycle time is always 75 */
- if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) {
- printk(BIOS_ERR, "SPD9 DIMM Is Not PC133 Compatable\n");
- die("HALT\n");
- }
- /* PC133 SPD10 - access time is always 54 */
- if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) {
- printk(BIOS_ERR, "SPD10 DIMM Is Not PC133 Compatable\n");
- die("HALT\n");
- }
-
- /* The i82830 only supports a symmetrical dual-sided dimms
- * and can't handle DIMMs smaller than 32MB per
- * side or larger than 256MB per side.
- */
- if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {
- printk(BIOS_ERR, "This northbridge only supports\n");
- printk(BIOS_ERR, "symmetrical dual-sided DIMMs\n");
- printk(BIOS_ERR, "booting as a single-sided DIMM\n");
- sz.side2 = 0;
- }
- if ((sz.side1 < 32)) {
- printk(BIOS_ERR, "DIMMs smaller than 32MB per side\n");
- printk(BIOS_ERR, "are not supported on this northbridge\n");
- die("HALT\n");
- }
-
- if ((sz.side1 > 256)) {
- printk(BIOS_ERR, "DIMMs larger than 256MB per side\n");
- printk(BIOS_ERR, "are not supported on this northbridge\n");
- die("HALT\n");
- }
- /* - End Memory compatibility checks - */
-
- /* We need to divide size by 32 to set up the
- * DRB registers.
- */
- if (sz.side1)
- drb1 = sz.side1 / 32;
- if (sz.side2)
- drb2 = sz.side2 / 32;
- } else {
- printk(BIOS_DEBUG, "No DIMM found in slot %u\n", i);
-
- /* If there's no DIMM in the slot, set value to 0. */
- drb1 = 0;
- drb2 = 0;
- }
- /* Set the value for DRAM Row Boundary Registers */
- if (i == 0) {
- pci_write_config8(NORTHBRIDGE, DRB, drb1);
- pci_write_config8(NORTHBRIDGE, DRB + 1, drb1 + drb2);
- PRINTK_DEBUG(" DRB 0x%02x has been set to 0x%02x\n", DRB, drb1);
- PRINTK_DEBUG(" DRB1 0x%02x has been set to 0x%02x\n", DRB + 1, drb1 + drb2);
- } else if (i == 1) {
- value = pci_read_config8(NORTHBRIDGE, DRB + 1);
- pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1);
- pci_write_config8(NORTHBRIDGE, DRB + 3, value + drb1 + drb2);
- PRINTK_DEBUG(" DRB2 0x%02x has been set to 0x%02x\n", DRB + 2, value + drb1);
- PRINTK_DEBUG(" DRB3 0x%02x has been set to 0x%02x\n", DRB + 3, value + drb1 + drb2);
-
- /* We need to set the highest DRB value to 0x64 and 0x65.
- * These are supposed to be "Reserved" but memory will
- * not initialize properly if we don't.
- */
- value = pci_read_config8(NORTHBRIDGE, DRB + 3);
- pci_write_config8(NORTHBRIDGE, DRB + 4, value);
- pci_write_config8(NORTHBRIDGE, DRB + 5, value);
- }
- }
-}
-
-static void set_dram_row_attributes(void)
-{
- int i, dra, col, width, value;
-
- for (i = 0; i < DIMM_SOCKETS; i++) {
- unsigned device;
- device = DIMM0 + i;
-
- /* First check if a DIMM is actually present. */
- if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
- PRINTK_DEBUG("Found DIMM in slot %u\n", i);
-
- dra = 0x00;
-
- /* columns */
- col = spd_read_byte(device, SPD_NUM_COLUMNS);
-
- /* data width */
- width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);
-
- /* calculate page size in bits */
- value = ((1 << col) * width);
-
- /* convert to Kilobytes */
- dra = ((value / 8) >> 10);
-
- /* # of banks of DIMM (single or double sided) */
- value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);
-
- if (value == 1) {
- if (dra == 2) {
- dra = 0xF0; /* 2KB */
- } else if (dra == 4) {
- dra = 0xF1; /* 4KB */
- } else if (dra == 8) {
- dra = 0xF2; /* 8KB */
- } else if (dra == 16) {
- dra = 0xF3; /* 16KB */
- } else {
- printk(BIOS_ERR, "Page size not supported\n");
- die("HALT\n");
- }
- } else if (value == 2) {
- if (dra == 2) {
- dra = 0x00; /* 2KB */
- } else if (dra == 4) {
- dra = 0x11; /* 4KB */
- } else if (dra == 8) {
- dra = 0x22; /* 8KB */
- } else if (dra == 16) {
- dra = 0x33; /* 16KB */
- } else {
- printk(BIOS_ERR, "Page size not supported\n");
- die("HALT\n");
- }
- } else {
- printk(BIOS_ERR, "# of banks of DIMM not supported\n");
- die("HALT\n");
- }
-
- } else {
- PRINTK_DEBUG("No DIMM found in slot %u\n", i);
-
- /* If there's no DIMM in the slot, set dra value to 0xFF. */
- dra = 0xFF;
- }
-
- /* Set the value for DRAM Row Attribute Registers */
- pci_write_config8(NORTHBRIDGE, DRA + i, dra);
- PRINTK_DEBUG(" DRA 0x%02x has been set to 0x%02x\n", DRA + i, dra);
- }
-}
-
-static void set_dram_timing(void)
-{
- /* Set the value for DRAM Timing Register */
- /* TODO: Configure the value according to SPD values. */
- pci_write_config32(NORTHBRIDGE, DRT, 0x00000010);
-}
-
-static void set_dram_buffer_strength(void)
-{
- /* TODO: This needs to be set according to the DRAM tech
- * (x8, x16, or x32). Argh, Intel provides no docs on this!
- * Currently, it needs to be pulled from the output of
- * lspci -xxx Rx92
- */
-
- /* Set the value for System Memory Buffer Strength Control Registers */
- pci_write_config32(NORTHBRIDGE, BUFF_SC, 0xFC9B491B);
-}
-
-/*-----------------------------------------------------------------------------
-Public interface.
------------------------------------------------------------------------------*/
-
-static void sdram_set_registers(void)
-{
- printk(BIOS_DEBUG, "Setting initial SDRAM registers....\n");
-
- /* Calculate the value for DRT DRAM Timing Register */
- set_dram_timing();
-
- /* Setup System Memory Buffer Strength Control Registers */
- set_dram_buffer_strength();
-
- /* Setup DRAM Row Boundary Registers */
- set_dram_row_boundaries();
-
- /* Setup DRAM Row Attribute Registers */
- set_dram_row_attributes();
-
- printk(BIOS_DEBUG, "Initial SDRAM registers have been set.\n");
-}
-
-static void northbridge_set_registers(void)
-{
- u16 value;
- int igd_memory = 0;
-
- printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n");
-
- /* Set the value for Fixed DRAM Hole Control Register */
- pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
-
- /* Set the value for Programmable Attribute Map Registers
- * Ideally, this should be R/W for as many ranges as possible.
- */
- pci_write_config8(NORTHBRIDGE, PAM0, 0x30);
- pci_write_config8(NORTHBRIDGE, PAM1, 0x33);
- pci_write_config8(NORTHBRIDGE, PAM2, 0x33);
- pci_write_config8(NORTHBRIDGE, PAM3, 0x33);
- pci_write_config8(NORTHBRIDGE, PAM4, 0x33);
- pci_write_config8(NORTHBRIDGE, PAM5, 0x33);
- pci_write_config8(NORTHBRIDGE, PAM6, 0x33);
-
- /* Set the value for System Management RAM Control Register */
- pci_write_config8(NORTHBRIDGE, SMRAM, 0x02);
-
- /* Set the value for GMCH Control Register #0 */
- pci_write_config16(NORTHBRIDGE, GCC0, 0xA072);
-
- /* Set the value for Aperture Base Configuration Register */
- pci_write_config32(NORTHBRIDGE, APBASE, 0x00000008);
-
- /* Set the value for GMCH Control Register #1 */
- switch (CONFIG_VIDEO_MB) {
- case 512: /* 512K of memory */
- igd_memory = 0x2;
- break;
- case 1: /* 1M of memory */
- igd_memory = 0x3;
- break;
- case 8: /* 8M of memory */
- igd_memory = 0x4;
- break;
- default: /* No memory */
- pci_write_config16(NORTHBRIDGE, GCC1, 0x0002);
- igd_memory = 0x0;
- }
-
- value = pci_read_config16(NORTHBRIDGE, GCC1);
- value |= igd_memory << 4;
- value |= 1; // 64MB aperture
- pci_write_config16(NORTHBRIDGE, GCC1, value);
-
- printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");
-}
-
-static void sdram_initialize(void)
-{
- u32 reg32;
-
- /* Setup Initial SDRAM Registers */
- sdram_set_registers();
-
- /* Wait until power/voltages and clocks are stable (200us). */
- udelay(200);
-
- /* Initialize each row of memory one at a time */
- initialize_dimm_rows();
-
- /* Enable Refresh */
- PRINTK_DEBUG("Enabling Refresh\n");
- reg32 = pci_read_config32(NORTHBRIDGE, DRC);
- reg32 |= (RAM_COMMAND_REFRESH << 8);
- pci_write_config32(NORTHBRIDGE, DRC, reg32);
-
- /* Set initialization complete */
- PRINTK_DEBUG("Setting initialization complete\n");
- reg32 = pci_read_config32(NORTHBRIDGE, DRC);
- reg32 |= (RAM_COMMAND_IC << 29);
- pci_write_config32(NORTHBRIDGE, DRC, reg32);
-
- /* Setup Initial Northbridge Registers */
- northbridge_set_registers();
-
- PRINTK_DEBUG("Northbridge following SDRAM init:\n");
- DUMPNORTH();
-}
diff --git a/src/northbridge/intel/i82830/raminit.h b/src/northbridge/intel/i82830/raminit.h
deleted file mode 100644
index 6b51db1..0000000
--- a/src/northbridge/intel/i82830/raminit.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2010 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef NORTHBRIDGE_INTEL_I82830_RAMINIT_H
-#define NORTHBRIDGE_INTEL_I82830_RAMINIT_H
-
-/* 82830 Northbridge PCI device */
-#define NORTHBRIDGE PCI_DEV(0, 0, 0)
-
-/* The 82830 supports max. 2 dual-sided SO-DIMMs. */
-#define DIMM_SOCKETS 2
-
-#endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
deleted file mode 100644
index 569e62e..0000000
--- a/src/northbridge/intel/i82830/smihandler.c
+++ /dev/null
@@ -1,387 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <compiler.h>
-#include <string.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/smm.h>
-#include <device/pci_def.h>
-#include "i82830.h"
-
-extern unsigned char *mbi;
-extern u32 mbi_len;
-
-// #define DEBUG_SMI_I82830
-
-/* If YABEL is enabled and it's not running at 0x00000000, we have to add some
- * offset to all our mbi object memory accesses
- */
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && !CONFIG_YABEL_DIRECTHW
-#define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION
-#else
-#define OBJ_OFFSET 0x00000
-#endif
-
-/* I830M */
-#define SMRAM 0x90
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRANE (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-
-
-typedef struct {
- u32 mhid;
- u32 function;
- u32 retsts;
- u32 rfu;
-} __packed banner_id_t;
-
-#define MSH_OK 0x0000
-#define MSH_OK_RESTART 0x0001
-#define MSH_FWH_ERR 0x00ff
-#define MSH_IF_BAD_ID 0x0100
-#define MSH_IF_BAD_FUNC 0x0101
-#define MSH_IF_MBI_CORRUPT 0x0102
-#define MSH_IF_BAD_HANDLE 0x0103
-#define MSH_ALRDY_ATCHED 0x0104
-#define MSH_NOT_ATCHED 0x0105
-#define MSH_IF 0x0106
-#define MSH_IF_INVADDR 0x0107
-#define MSH_IF_UKN_TYPE 0x0108
-#define MSH_IF_NOT_FOUND 0x0109
-#define MSH_IF_NO_KEY 0x010a
-#define MSH_IF_BUF_SIZE 0x010b
-#define MSH_IF_NOT_PENDING 0x010c
-
-#ifdef DEBUG_SMI_I82830
-static void
-dump(u8 * addr, u32 len)
-{
- printk(BIOS_DEBUG, "\n%s(%p, %x):\n", __func__, addr, len);
- while (len) {
- unsigned int tmpCnt = len;
- unsigned char x;
- if (tmpCnt > 8)
- tmpCnt = 8;
- printk(BIOS_DEBUG, "\n%p: ", addr);
- // print hex
- while (tmpCnt--) {
- x = *addr++;
- printk(BIOS_DEBUG, "%02x ", x);
- }
- tmpCnt = len;
- if (tmpCnt > 8)
- tmpCnt = 8;
- len -= tmpCnt;
- //reset addr ptr to print ascii
- addr = addr - tmpCnt;
- // print ascii
- while (tmpCnt--) {
- x = *addr++;
- if ((x < 32) || (x >= 127)) {
- //non-printable char
- x = '.';
- }
- printk(BIOS_DEBUG, "%c", x);
- }
- }
- printk(BIOS_DEBUG, "\n");
-}
-#endif
-
-typedef struct {
- banner_id_t banner;
- u16 versionmajor;
- u16 versionminor;
- u32 smicombuffersize;
-} __packed version_t;
-
-typedef struct {
- u16 header_id;
- u16 attributes;
- u16 size;
- u8 name_len;
- u8 reserved;
- u32 type;
- u32 header_ext;
- u8 name[0];
-} __packed mbi_header_t;
-
-typedef struct {
- banner_id_t banner;
- u64 handle;
- u32 objnum;
- mbi_header_t header;
-} __packed obj_header_t;
-
-typedef struct {
- banner_id_t banner;
- u64 handle;
- u32 objnum;
- u32 start;
- u32 numbytes;
- u32 buflen;
- u32 buffer;
-} __packed get_object_t;
-
-static void mbi_call(u8 subf, banner_id_t *banner_id)
-{
-#ifdef DEBUG_SMI_I82830
- printk(BIOS_DEBUG, "MBI\n");
- printk(BIOS_DEBUG, "|- sub function %x\n", subf);
- printk(BIOS_DEBUG, "|- banner id @ %x\n", (u32)banner_id);
- printk(BIOS_DEBUG, "| |- mhid %x\n", banner_id->mhid);
- printk(BIOS_DEBUG, "| |- function %x\n", banner_id->function);
- printk(BIOS_DEBUG, "| |- return status %x\n", banner_id->retsts);
- printk(BIOS_DEBUG, "| |- rfu %x\n", banner_id->rfu);
-#endif
-
- switch(banner_id->function) {
- case 0x0001: {
- version_t *version;
- printk(BIOS_DEBUG, "|- MBI_QueryInterface\n");
- version = (version_t *)banner_id;
- version->banner.retsts = MSH_OK;
- version->versionmajor = 1;
- version->versionminor = 3;
- version->smicombuffersize = 0x1000;
- break;
- }
- case 0x0002:
- printk(BIOS_DEBUG, "|- MBI_Attach\n");
- printk(BIOS_DEBUG, "| |- Not Implemented!\n");
- break;
- case 0x0003:
- printk(BIOS_DEBUG, "|- MBI_Detach\n");
- printk(BIOS_DEBUG, "| |- Not Implemented!\n");
- break;
- case 0x0201: {
- obj_header_t *obj_header = (obj_header_t *)banner_id;
- mbi_header_t *mbi_header = NULL;
- printk(BIOS_DEBUG, "|- MBI_GetObjectHeader\n");
- printk(BIOS_DEBUG, "| |- objnum = %d\n", obj_header->objnum);
-
- int i, count = 0;
- obj_header->banner.retsts = MSH_IF_NOT_FOUND;
-
- for (i = 0; i < mbi_len;) {
- int len;
-
- if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {
- i+=16;
- continue;
- }
-
- mbi_header = (mbi_header_t *)&mbi[i];
- len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
-
- if (obj_header->objnum == count) {
-#ifdef DEBUG_SMI_I82830
- if (mbi_header->name_len == 0xff) {
- printk(BIOS_DEBUG, "| |- corrupt.\n");
- break;
- }
-#endif
- int headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
-#ifdef DEBUG_SMI_I82830
- printk(BIOS_DEBUG, "| |- headerlen = %d\n", headerlen);
-#endif
- memcpy(&obj_header->header, mbi_header, headerlen);
- obj_header->banner.retsts = MSH_OK;
- printk(BIOS_DEBUG, "| |- MBI module '");
- int j;
- for (j = 0; j < mbi_header->name_len && mbi_header->name[j]; j++)
- printk(BIOS_DEBUG, "%c", mbi_header->name[j]);
- printk(BIOS_DEBUG, "' found.\n");
-#ifdef DEBUG_SMI_I82830
- dump((u8 *)banner_id, sizeof(obj_header_t) + ALIGN(mbi_header->name_len, 16));
-#endif
- break;
- }
- i += len;
- count++;
- }
- if (obj_header->banner.retsts == MSH_IF_NOT_FOUND)
- printk(BIOS_DEBUG, "| |- MBI object #%d not found.\n", obj_header->objnum);
- break;
- }
- case 0x0203: {
- get_object_t *getobj = (get_object_t *)banner_id;
- mbi_header_t *mbi_header = NULL;
- printk(BIOS_DEBUG, "|- MBI_GetObject\n");
-#ifdef DEBUG_SMI_I82830
- printk(BIOS_DEBUG, "| |- handle = %016Lx\n", getobj->handle);
-#endif
- printk(BIOS_DEBUG, "| |- objnum = %d\n", getobj->objnum);
- printk(BIOS_DEBUG, "| |- start = %x\n", getobj->start);
- printk(BIOS_DEBUG, "| |- numbytes = %x\n", getobj->numbytes);
- printk(BIOS_DEBUG, "| |- buflen = %x\n", getobj->buflen);
- printk(BIOS_DEBUG, "| |- buffer = %x\n", getobj->buffer);
-
- int i, count = 0;
- getobj->banner.retsts = MSH_IF_NOT_FOUND;
-
- for (i = 0; i< mbi_len;) {
- int headerlen, objectlen;
-
- if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {
- i+=16;
- continue;
- }
-
- mbi_header = (mbi_header_t *)&mbi[i];
- headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);
- objectlen = ALIGN((mbi_header->size * 16), 16);
-
- if (getobj->objnum == count) {
- printk(BIOS_DEBUG, "| |- len = %x\n", headerlen + objectlen);
-
- memcpy((void *)(getobj->buffer + OBJ_OFFSET),
- ((char *)mbi_header) + headerlen, (objectlen > getobj->buflen) ? getobj->buflen : objectlen);
-
- getobj->banner.retsts = MSH_OK;
-#ifdef DEBUG_SMI_I82830
- dump((u8 *)banner_id, sizeof(*getobj));
- dump((u8 *)getobj->buffer + OBJ_OFFSET, objectlen);
-#endif
- break;
- }
- i += (headerlen + objectlen);
- count++;
- }
- if (getobj->banner.retsts == MSH_IF_NOT_FOUND)
- printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum);
- break;
- }
- default:
- printk(BIOS_DEBUG, "|- function %x\n", banner_id->function);
- printk(BIOS_DEBUG, "| |- Unknown Function!\n");
- break;
- }
- printk(BIOS_DEBUG, "\n");
- //dump(banner_id, 0x20);
-}
-
-#define SMI_IFC_SUCCESS 1
-#define SMI_IFC_FAILURE_GENERIC 0
-#define SMI_IFC_FAILURE_INVALID 2
-#define SMI_IFC_FAILURE_CRITICAL 4
-#define SMI_IFC_FAILURE_NONCRITICAL 6
-
-#define PC10 0x10
-#define PC11 0x11
-#define PC12 0x12
-#define PC13 0x13
-
-static void smi_interface_call(void)
-{
- u8 *mmio = (u8 *)pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
- // mmio &= 0xfff80000;
- // printk(BIOS_DEBUG, "mmio=%x\n", mmio);
- u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
-
- if (!(swsmi & 1))
- return;
-
- swsmi &= ~(1 << 0); // clear SMI toggle
-
- switch ((swsmi>>1) & 0xf) {
- case 0:
- printk(BIOS_DEBUG, "Interface Function Presence Test.\n");
- swsmi = 0;
- swsmi &= ~(7 << 5); // Exit: Result
- swsmi |= (SMI_IFC_SUCCESS << 5);
- swsmi &= 0xff;
- swsmi |= (PC13 << 8);
- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
- // write magic
- write32(mmio + 0x71428, 0x494e5443);
- return;
- case 4:
- printk(BIOS_DEBUG, "Get BIOS Data.\n");
- printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
- break;
- case 5:
- printk(BIOS_DEBUG, "Call MBI Functions.\n");
- mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );
- // swsmi = 0x0000;
- swsmi &= ~(7 << 5); // Exit: Result
- swsmi |= (SMI_IFC_SUCCESS << 5);
- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
- return;
- case 6:
- printk(BIOS_DEBUG, "System BIOS Callbacks.\n");
- printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);
- break;
- default:
- printk(BIOS_DEBUG, "Unknown SMI interface call %04x\n", swsmi);
- break;
- }
-
- swsmi &= ~(7 << 5); // Exit: Result
- swsmi |= (SMI_IFC_FAILURE_CRITICAL << 7);
- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);
-}
-
-/**
- * @brief read and clear ERRSTS
- * @return ERRSTS register
- */
-static u16 reset_err_status(void)
-{
- u16 reg16;
-
- reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), ERRSTS);
- /* set status bits are cleared by writing 1 to them */
- pci_write_config16(PCI_DEV(0, 0x00, 0), ERRSTS, reg16);
-
- return reg16;
-}
-
-static void dump_err_status(u32 errsts)
-{
- printk(BIOS_DEBUG, "ERRSTS: ");
- if (errsts & (1 << 12)) printk(BIOS_DEBUG, "MBI ");
- if (errsts & (1 << 9)) printk(BIOS_DEBUG, "LCKF ");
- if (errsts & (1 << 8)) printk(BIOS_DEBUG, "DTF ");
- if (errsts & (1 << 5)) printk(BIOS_DEBUG, "UNSC ");
- if (errsts & (1 << 4)) printk(BIOS_DEBUG, "OOGF ");
- if (errsts & (1 << 3)) printk(BIOS_DEBUG, "IAAF ");
- if (errsts & (1 << 2)) printk(BIOS_DEBUG, "ITTEF ");
- printk(BIOS_DEBUG, "\n");
-}
-
-void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
-{
- u16 errsts;
-
- /* We need to clear the SMI status registers, or we won't see what's
- * happening in the following calls.
- */
- errsts = reset_err_status();
- if (errsts & (1 << 12)) {
- smi_interface_call();
- } else {
- if (errsts)
- dump_err_status(errsts);
- }
-
-}
diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c
deleted file mode 100644
index 20c9d0a..0000000
--- a/src/northbridge/intel/i82830/vga.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cbfs.h>
-#include <x86emu/x86emu.h>
-
-static void vga_init(device_t dev)
-{
- printk(BIOS_INFO, "Starting Graphics Initialization\n");
- size_t mbi_len;
- void *mbi = cbfs_boot_map_with_leak("mbi.bin", CBFS_TYPE_MBI, &mbi_len);
-
- if (mbi && mbi_len) {
- /* The GDT or coreboot table is going to live here. But
- * a long time after we relocated the GNVS, so this is
- * not troublesome.
- */
- *(u32 *)0x500 = (u32)mbi;
- *(u32 *)0x504 = (u32)mbi_len;
- outb(0xeb, 0xb2);
- }
-
- pci_dev_init(dev);
- printk(BIOS_INFO, "Graphics Initialization Complete\n");
-
- /* Enable TV-Out */
-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)
-#define PIPE_A_CRT (1 << 0)
-#define PIPE_A_LFP (1 << 1)
-#define PIPE_A_TV (1 << 3)
-#define PIPE_B_CRT (1 << 8)
-#define PIPE_B_TV (1 << 10)
- printk(BIOS_DEBUG, "Enabling TV-Out\n");
- void runInt10(void);
- X86_AX = 0x5f64;
- X86_BX = 0x0001; // Set Display Device, force execution
- X86_CX = PIPE_A_CRT | PIPE_A_TV;
- // M.x86.R_CX = PIPE_B_TV;
- runInt10();
- switch (X86_AX) {
- case 0x005f:
- printk(BIOS_DEBUG, "... failed.\n");
- break;
- case 0x015f:
- printk(BIOS_DEBUG, "... ok.\n");
- break;
- default:
- printk(BIOS_DEBUG, "... not supported.\n");
- break;
- }
-#endif
-}
-
-static const struct device_operations vga_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = vga_init,
- .scan_bus = 0,
- .enable = 0,
- .ops_pci = 0,
-};
-
-static const struct pci_driver vga_driver __pci_driver = {
- .ops = &vga_operations,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x3577,
-};
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
deleted file mode 100644
index 35e597a..0000000
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SOUTHBRIDGE_INTEL_I82801DX
- bool
- select ACPI_INTEL_HARDWARE_SLEEP_VALUES
- select SOUTHBRIDGE_INTEL_COMMON
- select IOAPIC
- select HAVE_HARD_RESET
- select HAVE_SMI_HANDLER
- select HAVE_USBDEBUG
- select SOUTHBRIDGE_INTEL_COMMON
- select SOUTHBRIDGE_INTEL_COMMON_SMBUS
-
-if SOUTHBRIDGE_INTEL_I82801DX
-
-config EHCI_BAR
- hex
- default 0xfef00000
-
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/intel/i82801dx/bootblock.c"
-
-endif
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc
deleted file mode 100644
index c514883..0000000
--- a/src/southbridge/intel/i82801dx/Makefile.inc
+++ /dev/null
@@ -1,35 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y)
-
-ramstage-y += i82801dx.c
-ramstage-y += ac97.c
-ramstage-y += ide.c
-ramstage-y += lpc.c
-#ramstage-y += pci.c
-ramstage-y += usb.c
-ramstage-y += usb2.c
-
-ramstage-y += reset.c
-
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-romstage-y += early_smbus.c
-
-endif
diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c
deleted file mode 100644
index 3ed83b7..0000000
--- a/src/southbridge/intel/i82801dx/ac97.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <delay.h>
-#include "i82801dx.h"
-
-#define NAMBAR 0x10
-#define MASTER_VOL 0x02
-#define PAGING 0x24
-#define EXT_AUDIO 0x28
-#define FUNC_SEL 0x66
-#define INFO_IO 0x68
-#define CONNECTOR 0x6a
-#define VENDOR_ID1 0x7c
-#define VENDOR_ID2 0x7e
-#define SEC_VENDOR_ID1 0xfc
-#define SEC_VENDOR_ID2 0xfe
-
-#define NABMBAR 0x14
-#define GLOB_CNT 0x2c
-#define GLOB_STA 0x30
-#define CAS 0x34
-
-#define MMBAR 0x10
-#define EXT_MODEM_ID1 0x3c
-#define EXT_MODEM_ID2 0xbc
-
-#define MBAR 0x14
-#define SEC_CODEC 0x40
-
-
-/* FIXME. This table is probably mainboard specific */
-static u16 ac97_function[16*2][4] = {
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },
- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) }
-};
-
-static u16 nabmbar;
-static u16 nambar;
-
-static int ac97_semaphore(void)
-{
- int timeout;
- u8 reg8;
-
- timeout = 0xffff;
- do {
- reg8 = inb(nabmbar + CAS);
- timeout--;
- } while ((reg8 & 1) && timeout);
- if (! timeout) {
- printk(BIOS_DEBUG, "Timeout!\n");
- }
-
- return (!timeout);
-}
-
-static void init_cnr(void)
-{
- // TODO
-}
-
-static void program_sigid(struct device *dev, u32 id)
-{
- pci_write_config32(dev, 0x2c, id);
-}
-
-static void ac97_audio_init(struct device *dev)
-{
- u16 reg16;
- u32 reg32;
- int i;
-
- printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n");
-
- /* top 16 bits are zero, so don't read them */
- nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe;
- nambar = pci_read_config16(dev, NAMBAR) & 0xfffe;
-
- reg16 = inw(nabmbar + GLOB_CNT);
- reg16 |= (1 << 1); /* Remove AC_RESET# */
- outw(reg16, nabmbar + GLOB_CNT);
-
- /* Wait 600ms. Ouch. */
- udelay(600 * 1000);
-
- init_cnr();
-
- /* Detect Primary AC'97 Codec */
- reg32 = inl(nabmbar + GLOB_STA);
- if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) {
- /* Primary Codec not found */
- printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n");
- return;
- }
-
- ac97_semaphore();
-
- /* Detect if codec is programmable */
- outw(0x8000, nambar + MASTER_VOL);
- ac97_semaphore();
- if (inw(nambar + MASTER_VOL) != 0x8000) {
- printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n");
- return;
- }
-
- /* Program Vendor IDs */
- reg32 = inw(nambar + VENDOR_ID1);
- reg32 <<= 16;
- reg32 |= (u16)inw(nambar + VENDOR_ID2);
-
- program_sigid(dev, reg32);
-
- /* Is Codec AC'97 2.3 compliant? */
- reg16 = inw(nambar + EXT_AUDIO);
- /* [11:10] = 10b -> AC'97 2.3 */
- if ((reg16 & 0x0c00) != 0x0800) {
- /* No 2.3 Codec. We're done */
- return;
- }
-
- /* Select Page 1 */
- reg16 = inw(nambar + PAGING);
- reg16 &= 0xfff0;
- reg16 |= 0x0001;
- outw(reg16, nambar + PAGING);
-
- for (i = 0x0a * 2; i > 0; i--) {
- outw(i, nambar + FUNC_SEL);
-
- /* Function could not be selected. Next one */
- if (inw(nambar + FUNC_SEL) != i)
- continue;
-
- reg16 = inw(nambar + INFO_IO);
-
- /* Function Information present? */
- if (!(reg16 & (1 << 0)))
- continue;
-
- /* Function Information valid? */
- if (!(reg16 & (1 << 4)))
- continue;
-
- /* Program Buffer Delay [9:5] */
- reg16 &= 0x03e0;
- reg16 |= ac97_function[i][0];
-
- /* Program Gain [15:11] */
- reg16 |= ac97_function[i][1];
-
- /* Program Inversion [10] */
- reg16 |= ac97_function[i][2];
-
- outw(reg16, nambar + INFO_IO);
-
- /* Program Connector / Jack Location */
- reg16 = inw(nambar + CONNECTOR);
- reg16 &= 0x1fff;
- reg16 |= ac97_function[i][3];
- outw(reg16, nambar + CONNECTOR);
- }
-}
-
-static void ac97_modem_init(struct device *dev)
-{
- u16 reg16;
- u32 reg32;
- u16 mmbar, mbar;
-
- mmbar = pci_read_config16(dev, MMBAR) & 0xfffe;
- mbar = pci_read_config16(dev, MBAR) & 0xfffe;
-
- reg16 = inw(mmbar + EXT_MODEM_ID1);
- if ((reg16 & 0xc000) != 0xc000 ) {
- if (reg16 & (1 << 0)) {
- reg32 = inw(mmbar + VENDOR_ID2);
- reg32 <<= 16;
- reg32 |= (u16)inw(mmbar + VENDOR_ID1);
- program_sigid(dev, reg32);
- return;
- }
- }
-
- /* Secondary codec? */
- reg16 = inw(mbar + SEC_CODEC);
- if ((reg16 & (1 << 9)) == 0)
- return;
-
- reg16 = inw(mmbar + EXT_MODEM_ID2);
- if ((reg16 & 0xc000) == 0x4000) {
- if (reg16 & (1 << 0)) {
- reg32 = inw(mmbar + SEC_VENDOR_ID2);
- reg32 <<= 16;
- reg32 |= (u16)inw(mmbar + SEC_VENDOR_ID1);
- program_sigid(dev, reg32);
- return;
- }
- }
-}
-
-static struct device_operations ac97_audio_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = i82801dx_enable,
- .init = ac97_audio_init,
- .scan_bus = 0,
-};
-
-static struct device_operations ac97_modem_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .enable = i82801dx_enable,
- .init = ac97_modem_init,
- .scan_bus = 0,
-};
-
-/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */
-static const struct pci_driver i82801db_ac97_audio __pci_driver = {
- .ops = &ac97_audio_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO,
-};
-
-static const struct pci_driver i82801db_ac97_modem __pci_driver = {
- .ops = &ac97_modem_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM,
-};
diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c
deleted file mode 100644
index 8ae419d..0000000
--- a/src/southbridge/intel/i82801dx/bootblock.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-
-static void bootblock_southbridge_init(void)
-{
- /* Set FWH IDs for 2 MB flash part. */
- if (CONFIG_ROM_SIZE == 0x200000)
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111);
-}
diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h
deleted file mode 100644
index f77413d..0000000
--- a/src/southbridge/intel/i82801dx/chip.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Eric Biederman
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef I82801DX_CHIP_H
-#define I82801DX_CHIP_H
-
-struct southbridge_intel_i82801dx_config {
- int enable_usb;
- int enable_native_ide;
- /**
- * Interrupt Routing configuration
- * If bit7 is 1, the interrupt is disabled.
- */
- uint8_t pirqa_routing;
- uint8_t pirqb_routing;
- uint8_t pirqc_routing;
- uint8_t pirqd_routing;
- uint8_t pirqe_routing;
- uint8_t pirqf_routing;
- uint8_t pirqg_routing;
- uint8_t pirqh_routing;
-
- uint8_t ide0_enable;
- uint8_t ide1_enable;
-};
-
-#endif /* I82801DX_CHIP_H */
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
deleted file mode 100644
index fabb58b..0000000
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ronald G. Minnich
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <device/pci_def.h>
-#include <console/console.h>
-#include <southbridge/intel/common/smbus.h>
-
-#include "i82801dx.h"
-
-void enable_smbus(void)
-{
- pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);
-
- printk(BIOS_DEBUG, "SMBus controller enabled\n");
- /* set smbus iobase */
- pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
- /* Set smbus enable */
- pci_write_config8(dev, 0x40, 0x01);
- /* Set smbus iospace enable */
- pci_write_config16(dev, 0x4, 0x01);
- /* Disable interrupt generation */
- outb(0, SMBUS_IO_BASE + SMBHSTCTL);
- /* clear any lingering errors, so the transaction will run */
- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-}
-
-int smbus_read_byte(unsigned int device, unsigned int address)
-{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c
deleted file mode 100644
index a4eb048..0000000
--- a/src/southbridge/intel/i82801dx/i82801dx.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ron G. Minnich
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include "i82801dx.h"
-
-void i82801dx_enable(device_t dev)
-{
- unsigned int index = 0;
- uint8_t bHasDisableBit = 0;
- uint16_t cur_disable_mask, new_disable_mask;
-
-// all 82801dbm devices are in bus 0
- unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc
- device_t lpc_dev = dev_find_slot(0, devfn); // 0
- if (!lpc_dev)
- return;
-
- // Calculate disable bit position for specified device:function
- // NOTE: For ICH-4, only the following devices can be disabled:
- // D31: F0, F1, F3, F5, F6,
- // D29: F0, F1, F2, F7
-
- if (PCI_SLOT(dev->path.pci.devfn) == 31) {
- index = PCI_FUNC(dev->path.pci.devfn);
-
- switch (index) {
- case 0:
- case 1:
- case 3:
- case 5:
- case 6:
- bHasDisableBit = 1;
- break;
-
- default:
- break;
- };
-
- if (index == 0)
- index = 14; // D31:F0 bit is an exception
-
- } else if (PCI_SLOT(dev->path.pci.devfn) == 29) {
- index = 8 + PCI_FUNC(dev->path.pci.devfn);
-
- if ((PCI_FUNC(dev->path.pci.devfn) < 3)
- || (PCI_FUNC(dev->path.pci.devfn) == 7))
- bHasDisableBit = 1;
- }
-
- if (bHasDisableBit) {
- cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);
- new_disable_mask = cur_disable_mask & ~(1 << index); // enable it
- if (!dev->enabled) {
- new_disable_mask |= (1 << index); // disable it
- }
- if (new_disable_mask != cur_disable_mask) {
- pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);
- }
- }
-}
-
-struct chip_operations southbridge_intel_i82801dx_ops = {
- CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge")
- .enable_dev = i82801dx_enable,
-};
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
deleted file mode 100644
index 14ca28f..0000000
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ron G. Minnich
- * Copyright (C) 2004 Eric Biederman
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* the problem: we have 82801dbm support in fb1, and 82801er in fb2.
- * fb1 code is what we want, fb2 structure is needed however.
- * so we need to get fb1 code for 82801dbm into fb2 structure.
- */
-/* What I did: took the 80801er stuff from fb2, verify it against the
- * db stuff in fb1, and made sure it was right.
- */
-
-#ifndef I82801DX_H
-#define I82801DX_H
-
-#include <arch/acpi.h>
-
-#if !defined(__ASSEMBLER__)
-#if !defined(__SIMPLE_DEVICE__)
-#include "chip.h"
-extern void i82801dx_enable(device_t dev);
-#else
-void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
-#endif
-#endif
-
-#define DEBUG_PERIODIC_SMIS 0
-
-#define MAINBOARD_POWER_OFF 0
-#define MAINBOARD_POWER_ON 1
-#define MAINBOARD_POWER_KEEP 2
-
-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
-#endif
-
-/*
- * 000 = Non-combined. P0 is primary master. P1 is secondary master.
- * 001 = Non-combined. P0 is secondary master. P1 is primary master.
- * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary;
- * Primary IDE channel disabled.
- * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.
- * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary
- * slave; Secondary IDE channel disabled.
- * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.
- */
-/* PCI Configuration Space (D31:F1) */
-#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
-#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
-
-/* IDE_TIM bits */
-#define IDE_DECODE_ENABLE (1 << 15)
-
-
-
-#define PCI_DMA_CFG 0x90
-#define SERIRQ_CNTL 0x64
-#define GEN_CNTL 0xd0
-#define GEN_STS 0xd4
-#define RTC_CONF 0xd8
-#define GEN_PMCON_3 0xa4
-
-#define PCICMD 0x04
-#define PMBASE 0x40
-#define PMBASE_ADDR 0x0400
-#define DEFAULT_PMBASE PMBASE_ADDR
-#define ACPI_CNTL 0x44
-#define ACPI_EN (1 << 4)
-#define BIOS_CNTL 0x4E
-#define GPIO_BASE 0x58
-#define GPIO_CNTL 0x5C
-#define GPIOBASE_ADDR 0x0500
-#define PIRQA_ROUT 0x60
-#define PIRQB_ROUT 0x61
-#define PIRQC_ROUT 0x62
-#define PIRQD_ROUT 0x63
-#define PIRQE_ROUT 0x68
-#define PIRQF_ROUT 0x69
-#define PIRQG_ROUT 0x6A
-#define PIRQH_ROUT 0x6B
-#define COM_DEC 0xE0
-#define LPC_EN 0xE6
-#define FUNC_DIS 0xF2
-
-/* 1e f0 244e */
-
-#define CMD 0x04
-#define SBUS_NUM 0x19
-#define SUB_BUS_NUM 0x1A
-#define SMLT 0x1B
-#define IOBASE 0x1C
-#define IOLIM 0x1D
-#define MEMBASE 0x20
-#define MEMLIM 0x22
-#define CNF 0x50
-#define MTT 0x70
-#define PCI_MAST_STS 0x82
-
-#define RTC_FAILED (1 <<2)
-
-
-#define SMBUS_IO_BASE 0x1000
-
-#define PM1_STS 0x00
-#define WAK_STS (1 << 15)
-#define PCIEXPWAK_STS (1 << 14)
-#define PRBTNOR_STS (1 << 11)
-#define RTC_STS (1 << 10)
-#define PWRBTN_STS (1 << 8)
-#define GBL_STS (1 << 5)
-#define BM_STS (1 << 4)
-#define TMROF_STS (1 << 0)
-#define PM1_EN 0x02
-#define PCIEXPWAK_DIS (1 << 14)
-#define RTC_EN (1 << 10)
-#define PWRBTN_EN (1 << 8)
-#define GBL_EN (1 << 5)
-#define TMROF_EN (1 << 0)
-#define PM1_CNT 0x04
-#define GBL_RLS (1 << 2)
-#define BM_RLD (1 << 1)
-#define SCI_EN (1 << 0)
-#define PM1_TMR 0x08
-#define PROC_CNT 0x10
-#define LV2 0x14
-#define LV3 0x15
-#define LV4 0x16
-#define PM2_CNT 0x20 // mobile only
-#define GPE0_STS 0x28
-#define PME_B0_STS (1 << 13)
-#define USB3_STS (1 << 12)
-#define PME_STS (1 << 11)
-#define BATLOW_STS (1 << 10)
-#define GST_STS (1 << 9)
-#define RI_STS (1 << 8)
-#define SMB_WAK_STS (1 << 7)
-#define TCOSCI_STS (1 << 6)
-#define AC97_STS (1 << 5)
-#define USB2_STS (1 << 4)
-#define USB1_STS (1 << 3)
-#define SWGPE_STS (1 << 2)
-#define HOT_PLUG_STS (1 << 1)
-#define THRM_STS (1 << 0)
-#define GPE0_EN 0x2c
-#define PME_B0_EN (1 << 13)
-#define PME_EN (1 << 11)
-#define SMI_EN 0x30
-#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology
-#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
-#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
-#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS
-#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)
-#define MCSMI_EN (1 << 11) // Trap microcontroller range access
-#define BIOS_RLS (1 << 7) // asserts SCI on bit set
-#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set
-#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#
-#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#
-#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic
-#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit
-#define EOS (1 << 1) // End of SMI (deassert SMI#)
-#define GBL_SMI_EN (1 << 0) // SMI# generation at all?
-#define SMI_STS 0x34
-#define ALT_GP_SMI_EN 0x38
-#define ALT_GP_SMI_STS 0x3a
-#define GPE_CNTL 0x42
-#define DEVACT_STS 0x44
-#define SS_CNT 0x50
-#define C3_RES 0x54
-
-#define TCOBASE 0x60 /* TCO Base Address Register */
-#define TCO1_CNT 0x08 /* TCO1 Control Register */
-
-#define GEN_PMCON_1 0xa0
-#define GEN_PMCON_2 0xa2
-#define GEN_PMCON_3 0xa4
-
-/* GEN_PMCON_3 bits */
-#define RTC_BATTERY_DEAD (1 << 2)
-#define RTC_POWER_FAILED (1 << 1)
-#define SLEEP_AFTER_POWER_FAIL (1 << 0)
-
-#endif /* I82801DX_H */
diff --git a/src/southbridge/intel/i82801dx/ide.c b/src/southbridge/intel/i82801dx/ide.c
deleted file mode 100644
index 51e2c89..0000000
--- a/src/southbridge/intel/i82801dx/ide.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ronald G. Minnich
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801dx.h"
-
-typedef struct southbridge_intel_i82801dx_config config_t;
-
-static void ide_init(struct device *dev)
-{
- /* Get the chip configuration */
- config_t *config = dev->chip_info;
-
- /* Enable IDE devices so the Linux IDE driver will work. */
- uint16_t ideTimingConfig;
-
- ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
- ideTimingConfig &= ~IDE_DECODE_ENABLE;
- if (!config || config->ide0_enable) {
- /* Enable primary IDE interface. */
- ideTimingConfig |= IDE_DECODE_ENABLE;
- printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");
- } else {
- printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");
- }
- pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
-
- ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
- ideTimingConfig &= ~IDE_DECODE_ENABLE;
- if (!config || config->ide1_enable) {
- /* Enable secondary IDE interface. */
- ideTimingConfig |= IDE_DECODE_ENABLE;
- printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");
- } else {
- printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");
- }
- pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
-}
-
-static struct device_operations ide_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ide_init,
- .scan_bus = 0,
- .enable = i82801dx_enable,
-};
-
-/* 82801DB */
-static const struct pci_driver i82801db_ide __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24cb,
-};
-
-/* 82801DBM */
-static const struct pci_driver i82801dbm_ide __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x24ca,
-};
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
deleted file mode 100644
index 3502c8b..0000000
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Linux Networx
- * Copyright (C) 2004 SuSE Linux AG
- * Copyright (C) 2004 Tyan Computer
- * Copyright (C) 2010 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include <pc80/isa-dma.h>
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include "i82801dx.h"
-
-#define NMI_OFF 0
-
-typedef struct southbridge_intel_i82801dx_config config_t;
-
-/**
- * Enable ACPI I/O range.
- *
- * @param dev PCI device with ACPI and PM BAR's
- */
-static void i82801dx_enable_acpi(struct device *dev)
-{
- /* Set ACPI base address (I/O space). */
- pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
-
- /* Enable ACPI I/O range decode and ACPI power management. */
- pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
-}
-
-/**
- * Set miscellanous static southbridge features.
- *
- * @param dev PCI device with I/O APIC control registers
- */
-static void i82801dx_enable_ioapic(struct device *dev)
-{
- u32 reg32;
-
- reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */
- reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */
- reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */
- reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */
- pci_write_config32(dev, GEN_CNTL, reg32);
- printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);
-
- set_ioapic_id(VIO_APIC_VADDR, 0x02);
-
- /*
- * Select Boot Configuration register (0x03) and
- * use Processor System Bus (0x01) to deliver interrupts.
- */
- io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
-}
-
-static void i82801dx_enable_serial_irqs(struct device *dev)
-{
- /* Set packet length and toggle silent mode bit. */
- pci_write_config8(dev, SERIRQ_CNTL,
- (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
- pci_write_config8(dev, SERIRQ_CNTL,
- (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
-}
-
-static void i82801dx_pirq_init(device_t dev)
-{
- /* Get the chip configuration */
- config_t *config = dev->chip_info;
-
- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
- pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
- pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
- pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
- pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
- pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
- pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
-}
-
-static void i82801dx_power_options(device_t dev)
-{
- u8 reg8;
- u16 reg16, pmbase;
- u32 reg32;
- const char *state;
-
- int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
- int nmi_option;
-
- /* Which state do we want to goto after g3 (power restored)?
- * 0 == S0 Full On
- * 1 == S5 Soft Off
- *
- * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
- */
- pwr_on = MAINBOARD_POWER_ON;
- get_option(&pwr_on, "power_on_after_fail");
-
- reg8 = pci_read_config8(dev, GEN_PMCON_3);
- reg8 &= 0xfe;
- switch (pwr_on) {
- case MAINBOARD_POWER_OFF:
- reg8 |= 1;
- state = "off";
- break;
- case MAINBOARD_POWER_ON:
- reg8 &= ~1;
- state = "on";
- break;
- case MAINBOARD_POWER_KEEP:
- reg8 &= ~1;
- state = "state keep";
- break;
- default:
- state = "undefined";
- }
-
- reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */
-
- pci_write_config8(dev, GEN_PMCON_3, reg8);
- printk(BIOS_INFO, "Set power %s after power failure.\n", state);
-
- /* Set up NMI on errors. */
- reg8 = inb(0x61);
- reg8 &= 0x0f; /* Higher Nibble must be 0 */
- reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */
- // reg8 &= ~(1 << 2); /* PCI SERR# Enable */
- reg8 |= (1 << 2); /* PCI SERR# Disable for now */
- outb(reg8, 0x61);
-
- reg8 = inb(0x70);
- nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
- if (nmi_option) {
- printk(BIOS_INFO, "NMI sources enabled.\n");
- reg8 &= ~(1 << 7); /* Set NMI. */
- } else {
- printk(BIOS_INFO, "NMI sources disabled.\n");
- reg8 |= ( 1 << 7); /* Disable NMI. */
- }
- outb(reg8, 0x70);
-
- /* Set SMI# rate down and enable CPU_SLP# */
- reg16 = pci_read_config16(dev, GEN_PMCON_1);
- reg16 &= ~(3 << 0); // SMI# rate 1 minute
- reg16 |= (1 << 5); // CPUSLP_EN Desktop only
- pci_write_config16(dev, GEN_PMCON_1, reg16);
-
- pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
-
- /* Set up power management block and determine sleep mode */
- reg32 = inl(pmbase + 0x04); // PM1_CNT
-
- reg32 &= ~(7 << 10); // SLP_TYP
- reg32 |= (1 << 0); // SCI_EN
- outl(reg32, pmbase + 0x04);
-}
-
-static void gpio_init(device_t dev)
-{
- /* This should be done in romstage.c already */
- pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1));
- pci_write_config8(dev, GPIO_CNTL, 0x10);
-}
-
-static void i82801dx_rtc_init(struct device *dev)
-{
- u8 reg8;
- u32 reg32;
- int rtc_failed;
-
- reg8 = pci_read_config8(dev, GEN_PMCON_3);
- rtc_failed = reg8 & RTC_BATTERY_DEAD;
- if (rtc_failed) {
- reg8 &= ~(1 << 1); /* Preserve the power fail state. */
- pci_write_config8(dev, GEN_PMCON_3, reg8);
- }
- reg32 = pci_read_config32(dev, GEN_STS);
- rtc_failed |= reg32 & (1 << 2);
- cmos_init(rtc_failed);
-
- /* Enable access to the upper 128 byte bank of CMOS RAM. */
- pci_write_config8(dev, RTC_CONF, 0x04);
-}
-
-static void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
-{
- u16 reg16;
- int i;
-
- reg16 = pci_read_config16(dev, PCI_DMA_CFG);
- reg16 &= 0x300;
- for (i = 0; i < 8; i++) {
- if (i == 4)
- continue;
- reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);
- }
- pci_write_config16(dev, PCI_DMA_CFG, reg16);
-}
-
-static void i82801dx_lpc_decode_en(device_t dev)
-{
- /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.
- * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.
- * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.
- * We also need to set the value for LPC I/F Enables Register.
- */
- pci_write_config8(dev, COM_DEC, 0x10);
- pci_write_config16(dev, LPC_EN, 0x300F);
-}
-
-/* ICH4 does not mention HPET in the docs, but
- * all ICH3 and ICH4 do have HPETs built in.
- */
-static void enable_hpet(struct device *dev)
-{
- u32 reg32, hpet, val;
-
- /* Set HPET base address and enable it */
- printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS);
- reg32 = pci_read_config32(dev, GEN_CNTL);
- /*
- * Bit 17 is HPET enable bit.
- * Bit 16:15 control the HPET base address.
- */
- reg32 &= ~(3 << 15); /* Clear it */
-
- hpet = CONFIG_HPET_ADDRESS >> 12;
- hpet &= 0x3;
-
- reg32 |= (hpet << 15);
- reg32 |= (1 << 17); /* Enable HPET. */
- pci_write_config32(dev, GEN_CNTL, reg32);
-
- /* Check to see whether it took */
- reg32 = pci_read_config32(dev, GEN_CNTL);
- val = reg32 >> 15;
- val &= 0x7;
-
- if ((val & 0x4) && (hpet == (val & 0x3))) {
- printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS);
- } else {
- printk(BIOS_WARNING, "HPET was not enabled correctly\n");
- reg32 &= ~(1 << 17); /* Clear Enable */
- pci_write_config32(dev, GEN_CNTL, reg32);
- }
-}
-
-static void lpc_init(struct device *dev)
-{
- /* Set the value for PCI command register. */
- pci_write_config16(dev, PCI_COMMAND, 0x000f);
-
- i82801dx_enable_acpi(dev);
- /* IO APIC initialization. */
- i82801dx_enable_ioapic(dev);
-
- i82801dx_enable_serial_irqs(dev);
-
- /* Setup the PIRQ. */
- i82801dx_pirq_init(dev);
-
- /* Setup power options. */
- i82801dx_power_options(dev);
-
- /* Set the state of the GPIO lines. */
- gpio_init(dev);
-
- /* Initialize the real time clock. */
- i82801dx_rtc_init(dev);
-
- /* Route DMA. */
- i82801dx_lpc_route_dma(dev, 0xff);
-
- /* Initialize ISA DMA. */
- isa_dma_init();
-
- /* Setup decode ports and LPC I/F enables. */
- i82801dx_lpc_decode_en(dev);
-
- /* Initialize the High Precision Event Timers */
- enable_hpet(dev);
-}
-
-static void i82801dx_lpc_read_resources(device_t dev)
-{
- struct resource *res;
-
- /* Get the normal PCI resources of this device. */
- pci_dev_read_resources(dev);
-
- /* Add an extra subtractive resource for both memory and I/O. */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->base = 0;
- res->size = 0x1000;
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->base = 0xff800000;
- res->size = 0x00800000; /* 8 MB for flash */
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = IO_APIC_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static struct device_operations lpc_ops = {
- .read_resources = i82801dx_lpc_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = lpc_init,
- .scan_bus = scan_lpc_bus,
- .enable = i82801dx_enable,
-};
-
-/* 82801DB/DBL */
-static const struct pci_driver lpc_driver_db __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_LPC,
-};
-
-/* 82801DBM */
-static const struct pci_driver lpc_driver_dbm __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DBM_LPC,
-};
diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h
deleted file mode 100644
index bdc6b45..0000000
--- a/src/southbridge/intel/i82801dx/nvs.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <compiler.h>
-
-typedef struct {
- /* Miscellaneous */
- u16 osys; /* 0x00 - Operating System */
- u8 smif; /* 0x02 - SMI function call ("TRAP") */
- u8 prm0; /* 0x03 - SMI function call parameter */
- u8 prm1; /* 0x04 - SMI function call parameter */
- u8 scif; /* 0x05 - SCI function call (via _L00) */
- u8 prm2; /* 0x06 - SCI function call parameter */
- u8 prm3; /* 0x07 - SCI function call parameter */
- u8 lckf; /* 0x08 - Global Lock function for EC */
- u8 prm4; /* 0x09 - Lock function parameter */
- u8 prm5; /* 0x0a - Lock function parameter */
- u32 p80d; /* 0x0b - Debug port (IO 0x80) value */
- u8 lids; /* 0x0f - LID state (open = 1) */
- u8 pwrs; /* 0x10 - Power state (AC = 1) */
- u8 dbgs; /* 0x11 - Debug state */
- u8 linx; /* 0x12 - Linux OS */
- u8 dckn; /* 0x13 - PCIe docking state */
- /* Thermal policy */
- u8 actt; /* 0x14 - active trip point */
- u8 psvt; /* 0x15 - passive trip point */
- u8 tc1v; /* 0x16 - passive trip point TC1 */
- u8 tc2v; /* 0x17 - passive trip point TC2 */
- u8 tspv; /* 0x18 - passive trip point TSP */
- u8 crtt; /* 0x19 - critical trip point */
- u8 dtse; /* 0x1a - Digital Thermal Sensor enable */
- u8 dts1; /* 0x1b - DT sensor 1 */
- u8 dts2; /* 0x1c - DT sensor 2 */
- u8 rsvd2;
- /* Battery Support */
- u8 bnum; /* 0x1e - number of batteries */
- u8 b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */
- u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
- u8 rsvd3[3];
- /* Processor Identification */
- u8 apic; /* 0x28 - APIC enabled */
- u8 mpen; /* 0x29 - MP capable/enabled */
- u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
- u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
- u8 ppcm; /* 0x2c - Max. PPC state */
- u8 rsvd4[5];
- /* Super I/O & CMOS config */
- u8 natp; /* 0x32 - SIO type */
- u8 cmap; /* 0x33 - */
- u8 cmbp; /* 0x34 - */
- u8 lptp; /* 0x35 - LPT port */
- u8 fdcp; /* 0x36 - Floppy Disk Controller */
- u8 rfdv; /* 0x37 - */
- u8 hotk; /* 0x38 - Hot Key */
- u8 rtcf;
- u8 util;
- u8 acin;
- /* Integrated Graphics Device */
- u8 igds; /* 0x3c - IGD state */
- u8 tlst; /* 0x3d - Display Toggle List Pointer */
- u8 cadl; /* 0x3e - currently attached devices */
- u8 padl; /* 0x3f - previously attached devices */
- u16 cste; /* 0x40 - current display state */
- u16 nste; /* 0x42 - next display state */
- u16 sste; /* 0x44 - set display state */
- u8 ndid; /* 0x46 - number of device ids */
- u32 did[5]; /* 0x47 - 5b device id 1..5 */
- u8 rsvd5[0x9];
- /* Backlight Control */
- u8 blcs; /* 0x64 - Backlight Control possible */
- u8 brtl;
- u8 odds;
- u8 rsvd6[0x7];
- /* Ambient Light Sensors*/
- u8 alse; /* 0x6e - ALS enable */
- u8 alaf;
- u8 llow;
- u8 lhih;
- u8 rsvd7[0x6];
- /* EMA */
- u8 emae; /* 0x78 - EMA enable */
- u16 emap;
- u16 emal;
- u8 rsvd8[0x5];
- /* MEF */
- u8 mefe; /* 0x82 - MEF enable */
- u8 rsvd9[0x9];
- /* TPM support */
- u8 tpmp; /* 0x8c - TPM */
- u8 tpme;
- u8 rsvd10[8];
- /* SATA */
- u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
- u8 gtf1[7];
- u8 gtf2[7];
- u8 idem;
- u8 idet;
- u8 rsvd11[7];
- /* IGD OpRegion (not implemented yet) */
- u32 aslb; /* 0xb4 - IGD OpRegion Base Address */
- u8 ibtt;
- u8 ipat;
- u8 itvf;
- u8 itvm;
- u8 ipsc;
- u8 iblc;
- u8 ibia;
- u8 issc;
- u8 i409;
- u8 i509;
- u8 i609;
- u8 i709;
- u8 idmm;
- u8 idms;
- u8 if1e;
- u8 hvco;
- u32 nxd[8];
- u8 rsvd12[8];
- /* Mainboard specific */
- u8 dock; /* 0xf0 - Docking Status */
- u8 bten;
- u8 rsvd13[14];
-} __packed global_nvs_t;
diff --git a/src/southbridge/intel/i82801dx/pci.c b/src/southbridge/intel/i82801dx/pci.c
deleted file mode 100644
index c062c85..0000000
--- a/src/southbridge/intel/i82801dx/pci.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ronald G. Minnich
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801dx.h"
-
-static void pci_init(struct device *dev)
-{
- /* Enable pci error detecting */
- uint32_t dword;
- /* System error enable */
- dword = pci_read_config32(dev, 0x04);
- dword |= (1 << 8); /* SERR# Enable */
- dword |= (1 << 6); /* Parity Error Response */
- pci_write_config32(dev, 0x04, dword);
-}
-
-static struct device_operations pci_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pci_init,
- .scan_bus = pci_scan_bridge,
-};
-
-/* 82801DB */
-static const struct pci_driver pci_driver_db __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_PCI,
-};
-
-/* 82801DBM/DBL */
-static const struct pci_driver pci_driver_dbm __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DBM_PCI,
-};
diff --git a/src/southbridge/intel/i82801dx/reset.c b/src/southbridge/intel/i82801dx/reset.c
deleted file mode 100644
index 1839ad6..0000000
--- a/src/southbridge/intel/i82801dx/reset.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ronald G. Minnich
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_hard_reset(void)
-{
- /* Try rebooting through port 0xcf9 */
- outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c
deleted file mode 100644
index 945fcf2..0000000
--- a/src/southbridge/intel/i82801dx/smi.c
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <device/device.h>
-#include <device/pci.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/io.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/smm.h>
-#include <string.h>
-#include "i82801dx.h"
-
-/* I945 */
-#define SMRAM 0x90
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRAME (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-
-/* While we read PMBASE dynamically in case it changed, let's
- * initialize it with a sane value
- */
-static u16 pmbase = PMBASE_ADDR;
-
-/**
- * @brief read and clear PM1_STS
- * @return PM1_STS register
- */
-static u16 reset_pm1_status(void)
-{
- u16 reg16;
-
- reg16 = inw(pmbase + PM1_STS);
- /* set status bits are cleared by writing 1 to them */
- outw(reg16, pmbase + PM1_STS);
-
- return reg16;
-}
-
-static void dump_pm1_status(u16 pm1_sts)
-{
- printk(BIOS_DEBUG, "PM1_STS: ");
- if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
- if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
- if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
- if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
- if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");
- if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");
- if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");
- if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");
- printk(BIOS_DEBUG, "\n");
-}
-
-/**
- * @brief read and clear SMI_STS
- * @return SMI_STS register
- */
-static u32 reset_smi_status(void)
-{
- u32 reg32;
-
- reg32 = inl(pmbase + SMI_STS);
- /* set status bits are cleared by writing 1 to them */
- outl(reg32, pmbase + SMI_STS);
-
- return reg32;
-}
-
-static void dump_smi_status(u32 smi_sts)
-{
- printk(BIOS_DEBUG, "SMI_STS: ");
- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
- if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
- printk(BIOS_DEBUG, "\n");
-}
-
-
-/**
- * @brief read and clear GPE0_STS
- * @return GPE0_STS register
- */
-static u32 reset_gpe0_status(void)
-{
- u32 reg32;
-
- reg32 = inl(pmbase + GPE0_STS);
- /* set status bits are cleared by writing 1 to them */
- outl(reg32, pmbase + GPE0_STS);
-
- return reg32;
-}
-
-static void dump_gpe0_status(u32 gpe0_sts)
-{
- int i;
- printk(BIOS_DEBUG, "GPE0_STS: ");
- for (i=31; i>= 16; i--) {
- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
- }
- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
- printk(BIOS_DEBUG, "\n");
-}
-
-
-/**
- * @brief read and clear ALT_GP_SMI_STS
- * @return ALT_GP_SMI_STS register
- */
-static u16 reset_alt_gp_smi_status(void)
-{
- u16 reg16;
-
- reg16 = inl(pmbase + ALT_GP_SMI_STS);
- /* set status bits are cleared by writing 1 to them */
- outl(reg16, pmbase + ALT_GP_SMI_STS);
-
- return reg16;
-}
-
-static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
-{
- int i;
- printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
- for (i=15; i>= 0; i--) {
- if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);
- }
- printk(BIOS_DEBUG, "\n");
-}
-
-
-
-/**
- * @brief read and clear TCOx_STS
- * @return TCOx_STS registers
- */
-static u32 reset_tco_status(void)
-{
- u32 tcobase = pmbase + 0x60;
- u32 reg32;
-
- reg32 = inl(tcobase + 0x04);
- /* set status bits are cleared by writing 1 to them */
- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
- if (reg32 & (1 << 18))
- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
-
- return reg32;
-}
-
-
-static void dump_tco_status(u32 tco_sts)
-{
- printk(BIOS_DEBUG, "TCO_STS: ");
- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
- printk(BIOS_DEBUG, "\n");
-}
-
-
-
-/**
- * @brief Set the EOS bit
- */
-static void smi_set_eos(void)
-{
- u8 reg8;
-
- reg8 = inb(pmbase + SMI_EN);
- reg8 |= EOS;
- outb(reg8, pmbase + SMI_EN);
-}
-
-extern uint8_t smm_relocation_start, smm_relocation_end;
-static void *default_smm_area = NULL;
-
-static void smm_relocate(void)
-{
- u32 smi_en;
- u16 pm1_en;
-
- printk(BIOS_DEBUG, "Initializing SMM handler...");
-
- pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc;
- printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
-
- smi_en = inl(pmbase + SMI_EN);
- if (smi_en & APMC_EN) {
- printk(BIOS_INFO, "SMI# handler already enabled?\n");
- return;
- }
-
- default_smm_area = backup_default_smm_area();
-
- /* copy the SMM relocation code */
- memcpy((void *)0x38000, &smm_relocation_start,
- &smm_relocation_end - &smm_relocation_start);
- wbinvd();
-
- printk(BIOS_DEBUG, "\n");
- dump_smi_status(reset_smi_status());
- dump_pm1_status(reset_pm1_status());
- dump_gpe0_status(reset_gpe0_status());
- dump_alt_gp_smi_status(reset_alt_gp_smi_status());
- dump_tco_status(reset_tco_status());
-
- /* Enable SMI generation:
- * - on TCO events
- * - on APMC writes (io 0xb2)
- * - on writes to SLP_EN (sleep states)
- * - on writes to GBL_RLS (bios commands)
- * No SMIs:
- * - on microcontroller writes (io 0x62/0x66)
- */
-
- smi_en = 0; /* reset SMI enables */
-
-#if 0
- smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
-#endif
- smi_en |= TCO_EN;
- smi_en |= APMC_EN;
-#if DEBUG_PERIODIC_SMIS
- /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using
- * periodic SMIs.
- */
- smi_en |= PERIODIC_EN;
-#endif
- smi_en |= SLP_SMI_EN;
- smi_en |= BIOS_EN;
-
- /* The following need to be on for SMIs to happen */
- smi_en |= EOS | GBL_SMI_EN;
-
- outl(smi_en, pmbase + SMI_EN);
-
- pm1_en = 0;
- pm1_en |= PWRBTN_EN;
- pm1_en |= GBL_EN;
- outw(pm1_en, pmbase + PM1_EN);
-
- /**
- * There are several methods of raising a controlled SMI# via
- * software, among them:
- * - Writes to io 0xb2 (APMC)
- * - Writes to the Local Apic ICR with Delivery mode SMI.
- *
- * Using the local apic is a bit more tricky. According to
- * AMD Family 11 Processor BKDG no destination shorthand must be
- * used.
- * The whole SMM initialization is quite a bit hardware specific, so
- * I'm not too worried about the better of the methods at the moment
- */
-
- /* raise an SMI interrupt */
- printk(BIOS_SPEW, " ... raise SMI#\n");
- outb(0x00, 0xb2);
-}
-
-static void smm_install(void)
-{
- /* enable the SMM memory window */
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
- D_OPEN | G_SMRAME | C_BASE_SEG);
-
- /* copy the real SMM handler */
- memcpy((void *)0xa0000, _binary_smm_start,
- _binary_smm_end - _binary_smm_start);
- wbinvd();
-
- /* close the SMM memory window and enable normal SMM */
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
- G_SMRAME | C_BASE_SEG);
-}
-
-void smm_init(void)
-{
- /* Put SMM code to 0xa0000 */
- smm_install();
-
- /* Put relocation code to 0x38000 and relocate SMBASE */
- smm_relocate();
-
- /* We're done. Make sure SMIs can happen! */
- smi_set_eos();
-}
-
-void smm_init_completion(void)
-{
- restore_default_smm_area(default_smm_area);
-}
-
-void smm_lock(void)
-{
- /* LOCK the SMM memory window and enable normal SMM.
- * After running this function, only a full reset can
- * make the SMM registers writable again.
- */
- printk(BIOS_DEBUG, "Locking SMM.\n");
- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
- D_LCK | G_SMRAME | C_BASE_SEG);
-}
-
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
- /* The GDT or coreboot table is going to live here. But a long time
- * after we relocated the GNVS, so this is not troublesome.
- */
- *(u32 *)0x500 = (u32)gnvs;
- *(u32 *)0x504 = (u32)tcg;
- *(u32 *)0x508 = (u32)smi1;
- outb(0xea, 0xb2);
-}
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
deleted file mode 100644
index 3a08daa..0000000
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ /dev/null
@@ -1,643 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <arch/io.h>
-#include <console/console.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/smm.h>
-#include <device/pci_def.h>
-#include "i82801dx.h"
-
-#define DEBUG_SMI
-
-/* I830M */
-#define SMRAM 0x90
-#define D_OPEN (1 << 6)
-#define D_CLS (1 << 5)
-#define D_LCK (1 << 4)
-#define G_SMRANE (1 << 3)
-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-
-#include "nvs.h"
-
-/* While we read PMBASE dynamically in case it changed, let's
- * initialize it with a sane value
- */
-u16 pmbase = PMBASE_ADDR;
-u8 smm_initialized = 0;
-
-unsigned char *mbi = NULL;
-u32 mbi_len;
-u8 mbi_initialized = 0;
-
-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
- * by coreboot.
- */
-global_nvs_t *gnvs = (global_nvs_t *)0x0;
-void *tcg = (void *)0x0;
-void *smi1 = (void *)0x0;
-
-/**
- * @brief read and clear PM1_STS
- * @return PM1_STS register
- */
-static u16 reset_pm1_status(void)
-{
- u16 reg16;
-
- reg16 = inw(pmbase + PM1_STS);
- /* set status bits are cleared by writing 1 to them */
- outw(reg16, pmbase + PM1_STS);
-
- return reg16;
-}
-
-static void dump_pm1_status(u16 pm1_sts)
-{
- printk(BIOS_SPEW, "PM1_STS: ");
- if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
- if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
- if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
- if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
- if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
- if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
- if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
- if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
- printk(BIOS_SPEW, "\n");
- int reg16 = inw(pmbase + PM1_EN);
- printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
-}
-
-/**
- * @brief read and clear SMI_STS
- * @return SMI_STS register
- */
-static u32 reset_smi_status(void)
-{
- u32 reg32;
-
- reg32 = inl(pmbase + SMI_STS);
- /* set status bits are cleared by writing 1 to them */
- outl(reg32, pmbase + SMI_STS);
-
- return reg32;
-}
-
-static void dump_smi_status(u32 smi_sts)
-{
- printk(BIOS_DEBUG, "SMI_STS: ");
- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
- if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
- printk(BIOS_DEBUG, "\n");
-}
-
-
-/**
- * @brief read and clear GPE0_STS
- * @return GPE0_STS register
- */
-static u32 reset_gpe0_status(void)
-{
- u32 reg32;
-
- reg32 = inl(pmbase + GPE0_STS);
- /* set status bits are cleared by writing 1 to them */
- outl(reg32, pmbase + GPE0_STS);
-
- return reg32;
-}
-
-static void dump_gpe0_status(u32 gpe0_sts)
-{
- int i;
- printk(BIOS_DEBUG, "GPE0_STS: ");
- for (i=31; i>= 16; i--) {
- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
- }
- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");
- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");
- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
- printk(BIOS_DEBUG, "\n");
-}
-
-
-/**
- * @brief read and clear TCOx_STS
- * @return TCOx_STS registers
- */
-static u32 reset_tco_status(void)
-{
- u32 tcobase = pmbase + 0x60;
- u32 reg32;
-
- reg32 = inl(tcobase + 0x04);
- /* set status bits are cleared by writing 1 to them */
- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS
- if (reg32 & (1 << 18))
- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
-
- return reg32;
-}
-
-
-static void dump_tco_status(u32 tco_sts)
-{
- printk(BIOS_DEBUG, "TCO_STS: ");
- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
- printk(BIOS_DEBUG, "\n");
-}
-
-int southbridge_io_trap_handler(int smif)
-{
- switch (smif) {
- case 0x32:
- printk(BIOS_DEBUG, "OS Init\n");
- /* gnvs->smif:
- * On success, the IO Trap Handler returns 0
- * On failure, the IO Trap Handler returns a value != 0
- */
- gnvs->smif = 0;
- return 1; /* IO trap handled */
- }
-
- /* Not handled */
- return 0;
-}
-
-/**
- * @brief Set the EOS bit
- */
-void southbridge_smi_set_eos(void)
-{
- u8 reg8;
-
- reg8 = inb(pmbase + SMI_EN);
- reg8 |= EOS;
- outb(reg8, pmbase + SMI_EN);
-}
-
-static void busmaster_disable_on_bus(int bus)
-{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- pci_devfn_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
-}
-
-
-static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
-{
- u8 reg8;
- u32 reg32;
- u8 slp_typ;
- /* FIXME: the power state on boot should be read from
- * CMOS or even better from GNVS. Right now it's hard
- * coded at compile time.
- */
- u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
-
- /* First, disable further SMIs */
- reg8 = inb(pmbase + SMI_EN);
- reg8 &= ~SLP_SMI_EN;
- outb(reg8, pmbase + SMI_EN);
-
- /* Figure out SLP_TYP */
- reg32 = inl(pmbase + PM1_CNT);
- printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
- slp_typ = acpi_sleep_from_pm1(reg32);
-
- /* Next, do the deed.
- */
-
- switch (slp_typ) {
- case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
- case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
- case ACPI_S3:
- printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
- /* Invalidate the cache before going to S3 */
- wbinvd();
- break;
- case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
- case ACPI_S5:
- printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
-
- outl(0, pmbase + GPE0_EN);
-
- /* Should we keep the power state after a power loss?
- * In case the setting is "ON" or "OFF" we don't have
- * to do anything. But if it's "KEEP" we have to switch
- * to "OFF" before entering S5.
- */
- if (s5pwr == MAINBOARD_POWER_KEEP) {
- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
- reg8 |= 1;
- pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
- }
-
- /* also iterates over all bridges on bus 0 */
- busmaster_disable_on_bus(0);
- break;
- default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
- }
-
- /* Write back to the SLP register to cause the originally intended
- * event again. We need to set BIT13 (SLP_EN) though to make the
- * sleep happen.
- */
- outl(reg32 | SLP_EN, pmbase + PM1_CNT);
-
- /* In most sleep states, the code flow of this function ends at
- * the line above. However, if we entered sleep state S1 and wake
- * up again, we will continue to execute code in this function.
- */
- reg32 = inl(pmbase + PM1_CNT);
- if (reg32 & SCI_EN) {
- /* The OS is not an ACPI OS, so we set the state to S0 */
- reg32 &= ~(SLP_EN | SLP_TYP);
- outl(reg32, pmbase + PM1_CNT);
- }
-}
-
-static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
-{
- u32 pmctrl;
- u8 reg8;
-
- /* Emulate B2 register as the FADT / Linux expects it */
-
- reg8 = inb(APM_CNT);
- switch (reg8) {
- case APM_CNT_CST_CONTROL:
- /* Calling this function seems to cause
- * some kind of race condition in Linux
- * and causes a kernel oops
- */
- printk(BIOS_DEBUG, "C-state control\n");
- break;
- case APM_CNT_PST_CONTROL:
- /* Calling this function seems to cause
- * some kind of race condition in Linux
- * and causes a kernel oops
- */
- printk(BIOS_DEBUG, "P-state control\n");
- break;
- case APM_CNT_ACPI_DISABLE:
- pmctrl = inl(pmbase + PM1_CNT);
- pmctrl &= ~SCI_EN;
- outl(pmctrl, pmbase + PM1_CNT);
- printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
- break;
- case APM_CNT_ACPI_ENABLE:
- pmctrl = inl(pmbase + PM1_CNT);
- pmctrl |= SCI_EN;
- outl(pmctrl, pmbase + PM1_CNT);
- printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
- break;
- case APM_CNT_GNVS_UPDATE:
- if (smm_initialized) {
- printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
- return;
- }
- gnvs = *(global_nvs_t **)0x500;
- tcg = *(void **)0x504;
- smi1 = *(void **)0x508;
- smm_initialized = 1;
- printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
- break;
- case APM_CNT_MBI_UPDATE: // FIXME
- if (mbi_initialized) {
- printk(BIOS_DEBUG, "SMI#: mbi already registered!\n");
- return;
- }
- mbi = *(void **)0x500;
- mbi_len = *(u32 *)0x504;
- mbi_initialized = 1;
- printk(BIOS_DEBUG, "SMI#: Registered MBI at %p (%d bytes)\n", mbi, mbi_len);
- break;
-
- default:
- printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);
- }
-}
-
-static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
-{
- u16 pm1_sts;
-
- pm1_sts = reset_pm1_status();
- dump_pm1_status(pm1_sts);
-
- /* While OSPM is not active, poweroff immediately
- * on a power button event.
- */
- if (pm1_sts & PWRBTN_STS) {
- // power button pressed
- u32 reg32;
- reg32 = (7 << 10) | (1 << 13);
- outl(reg32, pmbase + PM1_CNT);
- }
-}
-
-static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
-{
- u32 gpe0_sts;
-
- gpe0_sts = reset_gpe0_status();
- dump_gpe0_status(gpe0_sts);
-}
-
-static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
-{
- u16 reg16;
- reg16 = inw(pmbase + ALT_GP_SMI_STS);
- outl(reg16, pmbase + ALT_GP_SMI_STS);
-
- reg16 &= inw(pmbase + ALT_GP_SMI_EN);
-
- mainboard_smi_gpi(reg16);
-
- if (reg16)
- printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
-}
-
-static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
-{
- u32 reg32;
-
- reg32 = inl(pmbase + SMI_EN);
-
- /* Are periodic SMIs enabled? */
- if ((reg32 & MCSMI_EN) == 0)
- return;
-
- printk(BIOS_DEBUG, "Microcontroller SMI.\n");
-}
-
-
-
-static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
-{
- u32 tco_sts;
-
- tco_sts = reset_tco_status();
-
- /* Any TCO event? */
- if (!tco_sts)
- return;
-
- if (tco_sts & (1 << 8)) { // BIOSWR
- u8 bios_cntl;
-
- bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
-
- if (bios_cntl & 1) {
- /* BWE is RW, so the SMI was caused by a
- * write to BWE, not by a write to the BIOS
- */
-
- /* This is the place where we notice someone
- * is trying to tinker with the BIOS. We are
- * trying to be nice and just ignore it. A more
- * resolute answer would be to power down the
- * box.
- */
- printk(BIOS_DEBUG, "Switching back to RO\n");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
- } /* No else for now? */
- } else if (tco_sts & (1 << 3)) { /* TIMEOUT */
- /* Handle TCO timeout */
- printk(BIOS_DEBUG, "TCO Timeout.\n");
- } else if (!tco_sts) {
- dump_tco_status(tco_sts);
- }
-}
-
-static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
-{
- u32 reg32;
-
- reg32 = inl(pmbase + SMI_EN);
-
- /* Are periodic SMIs enabled? */
- if ((reg32 & PERIODIC_EN) == 0)
- return;
-
- printk(BIOS_DEBUG, "Periodic SMI.\n");
-}
-
-static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
-{
-#define IOTRAP(x) (trap_sts & (1 << x))
-#if 0
- u32 trap_sts, trap_cycle;
- u32 data, mask = 0;
- int i;
-
- trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
- RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
-
- trap_cycle = RCBA32(0x1e10);
- for (i=16; i<20; i++) {
- if (trap_cycle & (1 << i))
- mask |= (0xff << ((i - 16) << 2));
- }
-
-
- /* IOTRAP(3) SMI function call */
- if (IOTRAP(3)) {
- if (gnvs && gnvs->smif)
- io_trap_handler(gnvs->smif); // call function smif
- return;
- }
-
- /* IOTRAP(2) currently unused
- * IOTRAP(1) currently unused */
-
- /* IOTRAP(0) SMIC */
- if (IOTRAP(0)) {
- if (!(trap_cycle & (1 << 24))) { // It's a write
- printk(BIOS_DEBUG, "SMI1 command\n");
- data = RCBA32(0x1e18);
- data &= mask;
- // if (smi1)
- // southbridge_smi_command(data);
- // return;
- }
- // Fall through to debug
- }
-
- printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
- printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
- printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
- printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
-
- if (!(trap_cycle & (1 << 24))) {
- /* Write Cycle */
- data = RCBA32(0x1e18);
- printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);
- }
-#endif
-#undef IOTRAP
-}
-
-typedef void (*smi_handler_t)(unsigned int node,
- smm_state_save_area_t *state_save);
-
-smi_handler_t southbridge_smi[32] = {
- NULL, // [0] reserved
- NULL, // [1] reserved
- NULL, // [2] BIOS_STS
- NULL, // [3] LEGACY_USB_STS
- southbridge_smi_sleep, // [4] SLP_SMI_STS
- southbridge_smi_apmc, // [5] APM_STS
- NULL, // [6] SWSMI_TMR_STS
- NULL, // [7] reserved
- southbridge_smi_pm1, // [8] PM1_STS
- southbridge_smi_gpe0, // [9] GPE0_STS
- southbridge_smi_gpi, // [10] GPI_STS
- southbridge_smi_mc, // [11] MCSMI_STS
- NULL, // [12] DEVMON_STS
- southbridge_smi_tco, // [13] TCO_STS
- southbridge_smi_periodic, // [14] PERIODIC_STS
- NULL, // [15] SERIRQ_SMI_STS
- NULL, // [16] SMBUS_SMI_STS
- NULL, // [17] LEGACY_USB2_STS
- NULL, // [18] INTEL_USB2_STS
- NULL, // [19] reserved
- NULL, // [20] PCI_EXP_SMI_STS
- southbridge_smi_monitor, // [21] MONITOR_STS
- NULL, // [22] reserved
- NULL, // [23] reserved
- NULL, // [24] reserved
- NULL, // [25] EL_SMI_STS
- NULL, // [26] SPI_STS
- NULL, // [27] reserved
- NULL, // [28] reserved
- NULL, // [29] reserved
- NULL, // [30] reserved
- NULL // [31] reserved
-};
-
-/**
- * @brief Interrupt handler for SMI#
- * @param node
- * @param state_save
- */
-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
-{
- int i, dump = 0;
- u32 smi_sts;
-
- /* Update global variable pmbase */
- pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
-
- /* We need to clear the SMI status registers, or we won't see what's
- * happening in the following calls.
- */
- smi_sts = reset_smi_status();
-
- /* Filter all non-enabled SMI events */
- // FIXME Double check, this clears MONITOR
- // smi_sts &= inl(pmbase + SMI_EN);
-
- /* Call SMI sub handler for each of the status bits */
- for (i = 0; i < 31; i++) {
- if (smi_sts & (1 << i)) {
- if (southbridge_smi[i])
- southbridge_smi[i](node, state_save);
- else {
- printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "
- "handler available.\n", i);
- dump = 1;
- }
- }
- }
-
- if (dump) {
- dump_smi_status(smi_sts);
- }
-
-}
diff --git a/src/southbridge/intel/i82801dx/tco_timer.c b/src/southbridge/intel/i82801dx/tco_timer.c
deleted file mode 100644
index e773fa4..0000000
--- a/src/southbridge/intel/i82801dx/tco_timer.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe at settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-static void i82801dx_halt_tco_timer(void)
-{
- /* Set the LPC device statically. */
- pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x0);
-
- /* Temporarily set ACPI base address (I/O space). */
- pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
-
- /* Enable ACPI I/O. */
- pci_write_config8(dev, ACPI_CNTL, 0x10);
-
- /* Halt the TCO timer, preventing SMI and automatic reboot */
- outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11),
- PMBASE_ADDR + TCOBASE + TCO1_CNT);
-}
diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c
deleted file mode 100644
index 518f608..0000000
--- a/src/southbridge/intel/i82801dx/usb.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2004 Ronald G. Minnich
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "i82801dx.h"
-
-static void usb_init(struct device *dev)
-{
- u32 cmd;
- printk(BIOS_DEBUG, "USB: Setting up controller.. ");
- cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
- cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
- printk(BIOS_DEBUG, "done.\n");
-}
-
-static struct device_operations usb_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = usb_init,
- .scan_bus = 0,
- .enable = i82801dx_enable,
-};
-
-/* 82801DB/DBL/DBM USB1 */
-static const struct pci_driver usb_driver_1 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_USB1,
-};
-
-/* 82801DB/DBL/DBM USB2 */
-static const struct pci_driver usb_driver_2 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_USB2,
-};
-
-/* 82801DB/DBL/DBM USB3 */
-static const struct pci_driver usb_driver_3 __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_USB3,
-};
diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c
deleted file mode 100644
index dda3d95..0000000
--- a/src/southbridge/intel/i82801dx/usb2.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2003 Tyan
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <device/pci_ehci.h>
-#include "i82801dx.h"
-
-static void usb2_init(struct device *dev)
-{
- u32 cmd;
- printk(BIOS_DEBUG, "USB: Setting up controller.. ");
- cmd = pci_read_config32(dev, PCI_COMMAND);
- pci_write_config32(dev, PCI_COMMAND,
- cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);
- printk(BIOS_DEBUG, "done.\n");
-}
-
-static struct device_operations usb2_ops = {
- .read_resources = pci_ehci_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = usb2_init,
- .scan_bus = 0,
- .enable = i82801dx_enable,
-};
-
-/* 82801DB/DBM USB 2.0 */
-static const struct pci_driver usb2_driver __pci_driver = {
- .ops = &usb2_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82801DB_EHCI,
-};
--
To view, visit https://review.coreboot.org/22032
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9
Gerrit-Change-Number: 22032
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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