<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22032">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Intel i82830 boards & chips: Remove - using LATE_CBMEM_INIT<br><br>All boards and chips that are still using LATE_CBMEM_INIT are being<br>removed as previously discussed.<br><br>If these boards and chips are updated to not use LATE_CBMEM_INIT, they<br>can be restored to the active codebase from the 4.8 branch.<br><br>chips:<br>cpu/intel/socket_mFCBGA479<br>southbridge/intel/i82801dx<br>northbridge/intel/i82830<br><br>Mainboards:<br>mainboard/rca/rm4100<br>mainboard/thomson/ip1000<br><br>Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9<br>Signed-off-by: Martin Roth <gaumless@gmail.com><br>---<br>M src/arch/x86/Makefile.inc<br>M src/cpu/intel/Makefile.inc<br>D src/cpu/intel/socket_mFCBGA479/Kconfig<br>D src/cpu/intel/socket_mFCBGA479/Makefile.inc<br>M src/cpu/x86/smm/smmrelocate.S<br>M src/device/Kconfig<br>D src/mainboard/rca/Kconfig<br>D src/mainboard/rca/Kconfig.name<br>D src/mainboard/rca/rm4100/Kconfig<br>D src/mainboard/rca/rm4100/Kconfig.name<br>D src/mainboard/rca/rm4100/board_info.txt<br>D src/mainboard/rca/rm4100/devicetree.cb<br>D src/mainboard/rca/rm4100/gpio.c<br>D src/mainboard/rca/rm4100/irq_tables.c<br>D src/mainboard/rca/rm4100/romstage.c<br>D src/mainboard/rca/rm4100/smihandler.c<br>D src/mainboard/rca/rm4100/spd_table.h<br>D src/mainboard/thomson/Kconfig<br>D src/mainboard/thomson/Kconfig.name<br>D src/mainboard/thomson/ip1000/Kconfig<br>D src/mainboard/thomson/ip1000/Kconfig.name<br>D src/mainboard/thomson/ip1000/board_info.txt<br>D src/mainboard/thomson/ip1000/devicetree.cb<br>D src/mainboard/thomson/ip1000/gpio.c<br>D src/mainboard/thomson/ip1000/irq_tables.c<br>D src/mainboard/thomson/ip1000/mainboard.c<br>D src/mainboard/thomson/ip1000/romstage.c<br>D src/mainboard/thomson/ip1000/smihandler.c<br>D src/mainboard/thomson/ip1000/spd_table.h<br>D src/northbridge/intel/i82830/Kconfig<br>D src/northbridge/intel/i82830/Makefile.inc<br>D src/northbridge/intel/i82830/i82830.h<br>D src/northbridge/intel/i82830/memory_initialized.c<br>D src/northbridge/intel/i82830/northbridge.c<br>D src/northbridge/intel/i82830/raminit.c<br>D src/northbridge/intel/i82830/raminit.h<br>D src/northbridge/intel/i82830/smihandler.c<br>D src/northbridge/intel/i82830/vga.c<br>D src/southbridge/intel/i82801dx/Kconfig<br>D src/southbridge/intel/i82801dx/Makefile.inc<br>D src/southbridge/intel/i82801dx/ac97.c<br>D src/southbridge/intel/i82801dx/bootblock.c<br>D src/southbridge/intel/i82801dx/chip.h<br>D src/southbridge/intel/i82801dx/early_smbus.c<br>D src/southbridge/intel/i82801dx/i82801dx.c<br>D src/southbridge/intel/i82801dx/i82801dx.h<br>D src/southbridge/intel/i82801dx/ide.c<br>D src/southbridge/intel/i82801dx/lpc.c<br>D src/southbridge/intel/i82801dx/nvs.h<br>D src/southbridge/intel/i82801dx/pci.c<br>D src/southbridge/intel/i82801dx/reset.c<br>D src/southbridge/intel/i82801dx/smi.c<br>D src/southbridge/intel/i82801dx/smihandler.c<br>D src/southbridge/intel/i82801dx/tco_timer.c<br>D src/southbridge/intel/i82801dx/usb.c<br>D src/southbridge/intel/i82801dx/usb2.c<br>56 files changed, 0 insertions(+), 4,917 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/22032/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc<br>index cc227b3..0f3eaf4 100644<br>--- a/src/arch/x86/Makefile.inc<br>+++ b/src/arch/x86/Makefile.inc<br>@@ -43,10 +43,6 @@<br> pci$(stripped_vgabios_id).rom-file := $(call strip_quotes,$(CONFIG_VGA_BIOS_FILE))<br> pci$(stripped_vgabios_id).rom-type := optionrom<br> <br>-cbfs-files-$(CONFIG_INTEL_MBI) += mbi.bin<br>-mbi.bin-file := $(call strip_quotes,$(CONFIG_MBI_FILE))<br>-mbi.bin-type := mbi<br>-<br> ###############################################################################<br> # common support for early assembly includes<br> ###############################################################################<br>diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc<br>index 37fac8e..6fe13c9 100644<br>--- a/src/cpu/intel/Makefile.inc<br>+++ b/src/cpu/intel/Makefile.inc<br>@@ -9,7 +9,6 @@<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA1284) += socket_BGA1284<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559<br>-subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478<br> subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478MN) += socket_mPGA478MN<br>diff --git a/src/cpu/intel/socket_mFCBGA479/Kconfig b/src/cpu/intel/socket_mFCBGA479/Kconfig<br>deleted file mode 100644<br>index 7450854..0000000<br>--- a/src/cpu/intel/socket_mFCBGA479/Kconfig<br>+++ /dev/null<br>@@ -1,17 +0,0 @@<br>-config CPU_INTEL_SOCKET_MFCBGA479<br>- bool<br>- select CPU_INTEL_MODEL_6BX<br>- select MMX<br>- select SSE<br>-<br>-if CPU_INTEL_SOCKET_MFCBGA479<br>-<br>-config DCACHE_RAM_BASE<br>- hex<br>- default 0xc8000<br>-<br>-config DCACHE_RAM_SIZE<br>- hex<br>- default 0x08000<br>-<br>-endif<br>diff --git a/src/cpu/intel/socket_mFCBGA479/Makefile.inc b/src/cpu/intel/socket_mFCBGA479/Makefile.inc<br>deleted file mode 100644<br>index 918a54e..0000000<br>--- a/src/cpu/intel/socket_mFCBGA479/Makefile.inc<br>+++ /dev/null<br>@@ -1,10 +0,0 @@<br>-subdirs-y += ../model_6bx<br>-subdirs-y += ../../x86/tsc<br>-subdirs-y += ../../x86/mtrr<br>-subdirs-y += ../../x86/lapic<br>-subdirs-y += ../../x86/cache<br>-subdirs-y += ../../x86/smm<br>-subdirs-y += ../microcode<br>-<br>-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram.inc<br>-romstage-y += ../car/romstage_legacy.c<br>diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S<br>index ed556db..d535aa3 100644<br>--- a/src/cpu/x86/smm/smmrelocate.S<br>+++ b/src/cpu/x86/smm/smmrelocate.S<br>@@ -23,8 +23,6 @@<br> // here.<br> #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)<br> #include "../../../southbridge/intel/i82801gx/i82801gx.h"<br>-#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)<br>-#include "../../../southbridge/intel/i82801dx/i82801dx.h"<br> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801IX)<br> #include "../../../southbridge/intel/i82801ix/i82801ix.h"<br> #elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801JX)<br>diff --git a/src/device/Kconfig b/src/device/Kconfig<br>index 28298d5..99eedab 100644<br>--- a/src/device/Kconfig<br>+++ b/src/device/Kconfig<br>@@ -605,23 +605,6 @@<br> help<br> The path and filename of the VBT binary.<br> <br>-config INTEL_MBI<br>- bool "Add an MBI image"<br>- depends on NORTHBRIDGE_INTEL_I82830<br>- help<br>- Select this option if you have an Intel MBI image that you would<br>- like to add to your ROM.<br>-<br>- You will be able to specify the location and file name of the<br>- image later.<br>-<br>-config MBI_FILE<br>- string "Intel MBI path and filename"<br>- depends on INTEL_MBI<br>- default "mbi.bin"<br>- help<br>- The path and filename of the file to use as VGA BIOS.<br>-<br> config SOFTWARE_I2C<br> bool "Enable I2C controller emulation in software"<br> default n<br>diff --git a/src/mainboard/rca/Kconfig b/src/mainboard/rca/Kconfig<br>deleted file mode 100644<br>index d5728f2..0000000<br>--- a/src/mainboard/rca/Kconfig<br>+++ /dev/null<br>@@ -1,16 +0,0 @@<br>-if VENDOR_RCA<br>-<br>-choice<br>- prompt "Mainboard model"<br>-<br>-source "src/mainboard/rca/*/Kconfig.name"<br>-<br>-endchoice<br>-<br>-source "src/mainboard/rca/*/Kconfig"<br>-<br>-config MAINBOARD_VENDOR<br>- string<br>- default "RCA"<br>-<br>-endif # VENDOR_RCA<br>diff --git a/src/mainboard/rca/Kconfig.name b/src/mainboard/rca/Kconfig.name<br>deleted file mode 100644<br>index 3534996..0000000<br>--- a/src/mainboard/rca/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config VENDOR_RCA<br>- bool "RCA"<br>diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig<br>deleted file mode 100644<br>index 81cfc7b..0000000<br>--- a/src/mainboard/rca/rm4100/Kconfig<br>+++ /dev/null<br>@@ -1,24 +0,0 @@<br>-if BOARD_RCA_RM4100<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_SOCKET_MFCBGA479<br>- select NORTHBRIDGE_INTEL_I82830<br>- select SOUTHBRIDGE_INTEL_I82801DX<br>- select SUPERIO_SMSC_SMSCSUPERIO<br>- select HAVE_PIRQ_TABLE<br>- select BOARD_ROMSIZE_KB_1024<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default rca/rm4100<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "RM4100"<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 7<br>-<br>-endif # BOARD_RCA_RM4100<br>diff --git a/src/mainboard/rca/rm4100/Kconfig.name b/src/mainboard/rca/rm4100/Kconfig.name<br>deleted file mode 100644<br>index fd737ab..0000000<br>--- a/src/mainboard/rca/rm4100/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_RCA_RM4100<br>- bool "RM4100"<br>diff --git a/src/mainboard/rca/rm4100/board_info.txt b/src/mainboard/rca/rm4100/board_info.txt<br>deleted file mode 100644<br>index 0c06a7d..0000000<br>--- a/src/mainboard/rca/rm4100/board_info.txt<br>+++ /dev/null<br>@@ -1,3 +0,0 @@<br>-Category: settop<br>-Board URL: http://www.settoplinux.org/index.php?title=RCA_RM4100<br>-Flashrom support: y<br>diff --git a/src/mainboard/rca/rm4100/devicetree.cb b/src/mainboard/rca/rm4100/devicetree.cb<br>deleted file mode 100644<br>index 7c31423..0000000<br>--- a/src/mainboard/rca/rm4100/devicetree.cb<br>+++ /dev/null<br>@@ -1,67 +0,0 @@<br>-chip northbridge/intel/i82830 # Northbridge<br>- device cpu_cluster 0 on # APIC cluster<br>- chip cpu/intel/socket_mFCBGA479 # Mobile Celeron Micro-FCBGA Socket 479<br>- device lapic 0 on end # APIC<br>- end<br>- end<br>- device domain 0 on # PCI domain<br>- device pci 0.0 on end # Host bridge<br>- device pci 2.0 on end # VGA (Intel 82830 CGC)<br>- chip southbridge/intel/i82801dx # Southbridge<br>- register "pirqa_routing" = "0x05"<br>- register "pirqb_routing" = "0x06"<br>- register "pirqc_routing" = "0x07"<br>- register "pirqd_routing" = "0x09"<br>- register "pirqe_routing" = "0x0a"<br>- register "pirqf_routing" = "0x80"<br>- register "pirqg_routing" = "0x80"<br>- register "pirqh_routing" = "0x0b"<br>-<br>- register "ide0_enable" = "1"<br>- register "ide1_enable" = "1"<br>-<br>- device pci 1d.0 on end # USB UHCI Controller #1<br>- device pci 1d.1 on end # USB UHCI Controller #2<br>- device pci 1d.2 on end # USB UHCI Controller #3<br>- device pci 1d.7 on end # USB2 EHCI Controller<br>- device pci 1e.0 on end # PCI bridge<br>- device pci 1f.0 on # ISA/LPC bridge<br>- chip superio/smsc/smscsuperio # Super I/O<br>- device pnp 2e.0 off # Floppy<br>- io 0x60 = 0x3f0<br>- irq 0x70 = 6<br>- drq 0x74 = 2<br>- end<br>- device pnp 2e.3 on # Parallel port<br>- io 0x60 = 0x378<br>- irq 0x70 = 7<br>- drq 0x74 = 4<br>- end<br>- device pnp 2e.4 on # Com1<br>- io 0x60 = 0x3f8<br>- irq 0x70 = 4<br>- end<br>- device pnp 2e.5 on # Com2 / IR<br>- io 0x60 = 0x2f8<br>- irq 0x70 = 3<br>- end<br>- device pnp 2e.7 on # PS/2 keyboard/mouse<br>- io 0x60 = 0x60<br>- io 0x62 = 0x64<br>- irq 0x70 = 1 # Keyboard interrupt<br>- irq 0x72 = 12 # Mouse interrupt<br>- end<br>- device pnp 2e.9 off end # Game port<br>- device pnp 2e.a on # PME<br>- io 0x60 = 0x800<br>- end<br>- device pnp 2e.b off end # MPU-401<br>- end<br>- end<br>- device pci 1f.1 on end # IDE<br>- device pci 1f.3 on end # SMBus<br>- device pci 1f.5 on end # AC'97 audio<br>- device pci 1f.6 on end # AC'97 modem<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c<br>deleted file mode 100644<br>index 168bb09..0000000<br>--- a/src/mainboard/rca/rm4100/gpio.c<br>+++ /dev/null<br>@@ -1,141 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <delay.h><br>-<br>-#define PME_DEV PNP_DEV(0x2e, 0x0a)<br>-#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */<br>-#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */<br>-<br>-/* Early mainboard specific GPIO setup. */<br>-static void mb_gpio_init(void)<br>-{<br>- pci_devfn_t dev;<br>- uint16_t port;<br>- uint32_t set_gpio;<br>-<br>- /* Southbridge GPIOs. */<br>- /* Set the LPC device statically. */<br>- dev = PCI_DEV(0x0, 0x1f, 0x0);<br>-<br>- /* Set the value for GPIO base address register and enable GPIO. */<br>- pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));<br>- pci_write_config8(dev, GPIO_CNTL, 0x10);<br>-<br>- /* Set GPIO23 to high, this enables the LAN controller. */<br>- udelay(10);<br>- set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);<br>- set_gpio |= 1 << 23;<br>- outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);<br>-<br>- /* Super I/O GPIOs. */<br>- dev = PME_DEV;<br>- port = dev >> 8;<br>-<br>- /* Enter the configuration state. */<br>- outb(0x55, port);<br>- pnp_set_logical_device(dev);<br>- pnp_set_enable(dev, 0);<br>- pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);<br>- pnp_set_enable(dev, 1);<br>-<br>- /* GP21 - LED_RED */<br>- outl(0x01, PME_IO_BASE_ADDR + 0x2c);<br>-<br>- /* GP30 - FAN2_TACH */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x33);<br>-<br>- /* GP31 - FAN1_TACH */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x34);<br>-<br>- /* GP32 - FAN2_CTRL */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x35);<br>-<br>- /* GP33 - FAN1_CTRL */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x36);<br>-<br>- /* GP34 - AUD_MUTE_OUT_R */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x37);<br>-<br>- /* GP36 - KBRST */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x39);<br>-<br>- /* GP37 - A20GATE */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x3a);<br>-<br>- /* GP42 - GPIO_PME_OUT */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x3d);<br>-<br>- /* GP50 - SER2_RI */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x3f);<br>-<br>- /* GP51 - SER2_DCD */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x40);<br>-<br>- /* GP52 - SER2_RX */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x41);<br>-<br>- /* GP53 - SER2_TX */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x42);<br>-<br>- /* GP55 - SER2_RTS */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x44);<br>-<br>- /* GP56 - SER2_CTS */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x45);<br>-<br>- /* GP57 - SER2_DTR */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x46);<br>-<br>- /* GP60 - LED_GREEN */<br>- outl(0x01, PME_IO_BASE_ADDR + 0x47);<br>-<br>- /* GP61 - LED_YELLOW */<br>- outl(0x01, PME_IO_BASE_ADDR + 0x48);<br>-<br>- /* GP3 */<br>- outl(0xc0, PME_IO_BASE_ADDR + 0x4d);<br>-<br>- /* GP4 */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x4e);<br>-<br>- /* FAN1 */<br>- outl(0x01, PME_IO_BASE_ADDR + 0x56);<br>-<br>- /* FAN2 */<br>- outl(0x01, PME_IO_BASE_ADDR + 0x57);<br>-<br>- /* Fan Control */<br>- outl(0x50, PME_IO_BASE_ADDR + 0x58);<br>-<br>- /* Fan1 Tachometer */<br>- outl(0xff, PME_IO_BASE_ADDR + 0x59);<br>-<br>- /* Fan2 Tachometer */<br>- outl(0xff, PME_IO_BASE_ADDR + 0x5a);<br>-<br>- /* LED1 */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x5d);<br>-<br>- /* LED2 */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x5e);<br>-<br>- /* Keyboard Scan Code */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x5f);<br>-<br>- /* Exit the configuration state. */<br>- outb(0xaa, port);<br>-}<br>diff --git a/src/mainboard/rca/rm4100/irq_tables.c b/src/mainboard/rca/rm4100/irq_tables.c<br>deleted file mode 100644<br>index e99adfc..0000000<br>--- a/src/mainboard/rca/rm4100/irq_tables.c<br>+++ /dev/null<br>@@ -1,46 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */<br>- 0x00, /* Where the interrupt router lies (bus) */<br>- (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */<br>- 0, /* IRQs devoted exclusively to PCI usage */<br>- 0x8086, /* Vendor */<br>- 0x24c0, /* Device */<br>- 0, /* Miniport data */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0x07, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */<br>- {<br>- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */<br>- {0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */<br>- {0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */<br>- {0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */<br>- {0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */<br>- {0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */<br>- {0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c<br>deleted file mode 100644<br>index 43c518f..0000000<br>--- a/src/mainboard/rca/rm4100/romstage.c<br>+++ /dev/null<br>@@ -1,116 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <stdlib.h><br>-#include <device/pci_def.h><br>-#include <arch/io.h><br>-#include <device/pnp_def.h><br>-#include <console/console.h><br>-#include <lib.h><br>-#include <superio/smsc/smscsuperio/smscsuperio.h><br>-#include <northbridge/intel/i82830/raminit.h><br>-#include "northbridge/intel/i82830/memory_initialized.c"<br>-#include <southbridge/intel/i82801dx/i82801dx.h><br>-#include "southbridge/intel/i82801dx/reset.c"<br>-#include <cpu/x86/bist.h><br>-#include <cpu/intel/romstage.h><br>-#include "spd_table.h"<br>-#include "gpio.c"<br>-#include "southbridge/intel/i82801dx/tco_timer.c"<br>-<br>-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)<br>-<br>-/**<br>- * The onboard 64MB PC133 memory does not have a SPD EEPROM so the<br>- * values have to be set manually, the SO-DIMM socket is located in<br>- * socket0 (0x50/DIMM0), and the onboard memory is located in socket1<br>- * (0x51/DIMM1).<br>- */<br>-static inline int spd_read_byte(unsigned device, unsigned address)<br>-{<br>- int i;<br>-<br>- if (device == DIMM0) {<br>- return smbus_read_byte(device, address);<br>- } else if (device == DIMM1) {<br>- for (i = 0; i < ARRAY_SIZE(spd_table); i++) {<br>- if (spd_table[i].address == address)<br>- return spd_table[i].data;<br>- }<br>- return 0xFF; /* Return 0xFF when address is not found. */<br>- } else {<br>- return 0xFF; /* Return 0xFF on any failures. */<br>- }<br>-}<br>-<br>-#include "northbridge/intel/i82830/raminit.c"<br>-<br>-/**<br>- * Setup mainboard specific registers pre raminit.<br>- */<br>-static void mb_early_setup(void)<br>-{<br>- /* - Hub Interface to PCI Bridge Registers - */<br>- /* 12-Clock Retry Enable */<br>- pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);<br>- /* Master Latency Timer Count */<br>- pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);<br>- /* I/O Address Base */<br>- pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);<br>-<br>- /* - LPC Interface Bridge Registers - */<br>- /* Delayed Transaction Enable */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);<br>- /* Disable the TCO Timer system reboot feature */<br>- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);<br>- /* CPU Frequency Strap */<br>- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);<br>- /* ACPI base address and enable Resource Indicator */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));<br>- /* Enable the SMBUS */<br>- enable_smbus();<br>- /* ACPI base address and disable Resource Indicator */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR));<br>- /* ACPI Enable */<br>- pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);<br>-}<br>-<br>-void mainboard_romstage_entry(unsigned long bist)<br>-{<br>- if (bist == 0) {<br>- if (memory_initialized())<br>- hard_reset();<br>- }<br>-<br>- /* Set southbridge and superio gpios */<br>- mb_gpio_init();<br>-<br>- smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>- console_init();<br>-<br>- /* Halt if there was a built in self test failure. */<br>- report_bist_failure(bist);<br>-<br>- /* disable TCO timers */<br>- i82801dx_halt_tco_timer();<br>-<br>- /* Setup mainboard specific registers */<br>- mb_early_setup();<br>-<br>- /* Initialize memory */<br>- sdram_initialize();<br>-}<br>diff --git a/src/mainboard/rca/rm4100/smihandler.c b/src/mainboard/rca/rm4100/smihandler.c<br>deleted file mode 100644<br>index a8a7aca..0000000<br>--- a/src/mainboard/rca/rm4100/smihandler.c<br>+++ /dev/null<br>@@ -1,25 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <console/console.h><br>-#include <cpu/x86/smm.h><br>-<br>-int mainboard_io_trap_handler(int smif)<br>-{<br>- printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");<br>- return 1;<br>-}<br>diff --git a/src/mainboard/rca/rm4100/spd_table.h b/src/mainboard/rca/rm4100/spd_table.h<br>deleted file mode 100644<br>index 14bc85b..0000000<br>--- a/src/mainboard/rca/rm4100/spd_table.h<br>+++ /dev/null<br>@@ -1,36 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <spd.h><br>-<br>-struct spd_entry {<br>- unsigned int address;<br>- unsigned int data;<br>-};<br>-<br>-/*<br>- * The onboard 128MB PC133 memory does not have an SPD EEPROM so the values<br>- * have to be set manually, the onboard memory is located in socket1 (0x51).<br>- */<br>-const struct spd_entry spd_table [] = {<br>- {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */<br>- {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */<br>- {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */<br>- {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */<br>- {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */<br>- {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */<br>- {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, 0x20}, /* Density of each row on module */<br>-};<br>diff --git a/src/mainboard/thomson/Kconfig b/src/mainboard/thomson/Kconfig<br>deleted file mode 100644<br>index e439ba7..0000000<br>--- a/src/mainboard/thomson/Kconfig<br>+++ /dev/null<br>@@ -1,16 +0,0 @@<br>-if VENDOR_THOMSON<br>-<br>-choice<br>- prompt "Mainboard model"<br>-<br>-source "src/mainboard/thomson/*/Kconfig.name"<br>-<br>-endchoice<br>-<br>-source "src/mainboard/thomson/*/Kconfig"<br>-<br>-config MAINBOARD_VENDOR<br>- string<br>- default "Thomson"<br>-<br>-endif # VENDOR_THOMSON<br>diff --git a/src/mainboard/thomson/Kconfig.name b/src/mainboard/thomson/Kconfig.name<br>deleted file mode 100644<br>index b22bbbb..0000000<br>--- a/src/mainboard/thomson/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config VENDOR_THOMSON<br>- bool "Thomson"<br>diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig<br>deleted file mode 100644<br>index 1c21ace..0000000<br>--- a/src/mainboard/thomson/ip1000/Kconfig<br>+++ /dev/null<br>@@ -1,36 +0,0 @@<br>-if BOARD_THOMSON_IP1000<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_SOCKET_MFCBGA479<br>- select NORTHBRIDGE_INTEL_I82830<br>- select SOUTHBRIDGE_INTEL_I82801DX<br>- select SUPERIO_SMSC_SMSCSUPERIO<br>- select HAVE_PIRQ_TABLE<br>- select BOARD_ROMSIZE_KB_512<br>- select INTEL_INT15<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default thomson/ip1000<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "IP1000"<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 7<br>-<br>-choice<br>- prompt "IP1000 Onboard Memory"<br>- default ONBOARD_MEMORY_64MB<br>-<br>-config ONBOARD_MEMORY_64MB<br>- bool "IP1000-64MB"<br>-config ONBOARD_MEMORY_128MB<br>- bool "IP1000T-128MB"<br>-<br>-endchoice<br>-<br>-endif # BOARD_THOMSON_IP1000<br>diff --git a/src/mainboard/thomson/ip1000/Kconfig.name b/src/mainboard/thomson/ip1000/Kconfig.name<br>deleted file mode 100644<br>index ad3d884..0000000<br>--- a/src/mainboard/thomson/ip1000/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_THOMSON_IP1000<br>- bool "IP1000"<br>diff --git a/src/mainboard/thomson/ip1000/board_info.txt b/src/mainboard/thomson/ip1000/board_info.txt<br>deleted file mode 100644<br>index 77f0895..0000000<br>--- a/src/mainboard/thomson/ip1000/board_info.txt<br>+++ /dev/null<br>@@ -1,3 +0,0 @@<br>-Category: settop<br>-Board URL: http://www.settoplinux.org/index.php?title=Thomson_IP1000<br>-Flashrom support: y<br>diff --git a/src/mainboard/thomson/ip1000/devicetree.cb b/src/mainboard/thomson/ip1000/devicetree.cb<br>deleted file mode 100644<br>index 2f8903e..0000000<br>--- a/src/mainboard/thomson/ip1000/devicetree.cb<br>+++ /dev/null<br>@@ -1,68 +0,0 @@<br>-chip northbridge/intel/i82830 # Northbridge<br>- device cpu_cluster 0 on # APIC cluster<br>- chip cpu/intel/socket_mFCBGA479 # Low Voltage PIII Micro-FCBGA Socket 479<br>- device lapic 0 on end # APIC<br>- end<br>- end<br>-<br>- device domain 0 on # PCI domain<br>- device pci 0.0 on end # Host bridge<br>- device pci 2.0 on end # VGA (Intel 82830 CGC)<br>- chip southbridge/intel/i82801dx # Southbridge<br>- register "pirqa_routing" = "0x05"<br>- register "pirqb_routing" = "0x06"<br>- register "pirqc_routing" = "0x07"<br>- register "pirqd_routing" = "0x09"<br>- register "pirqe_routing" = "0x0a"<br>- register "pirqf_routing" = "0x80"<br>- register "pirqg_routing" = "0x80"<br>- register "pirqh_routing" = "0x0b"<br>-<br>- register "ide0_enable" = "1"<br>- register "ide1_enable" = "1"<br>-<br>- device pci 1d.0 on end # USB UHCI Controller #1<br>- device pci 1d.1 on end # USB UHCI Controller #2<br>- device pci 1d.2 on end # USB UHCI Controller #3<br>- device pci 1d.7 on end # USB2 EHCI Controller<br>- device pci 1e.0 on end # PCI bridge<br>- device pci 1f.0 on # ISA/LPC bridge<br>- chip superio/smsc/smscsuperio # Super I/O<br>- device pnp 2e.0 off # Floppy<br>- io 0x60 = 0x3f0<br>- irq 0x70 = 6<br>- drq 0x74 = 2<br>- end<br>- device pnp 2e.3 on # Parallel port<br>- io 0x60 = 0x378<br>- irq 0x70 = 7<br>- drq 0x74 = 4<br>- end<br>- device pnp 2e.4 on # Com1<br>- io 0x60 = 0x3f8<br>- irq 0x70 = 4<br>- end<br>- device pnp 2e.5 on # Com2 / IR<br>- io 0x60 = 0x2f8<br>- irq 0x70 = 3<br>- end<br>- device pnp 2e.7 on # PS/2 keyboard/mouse<br>- io 0x60 = 0x60<br>- io 0x62 = 0x64<br>- irq 0x70 = 1 # Keyboard interrupt<br>- irq 0x72 = 12 # Mouse interrupt<br>- end<br>- device pnp 2e.9 off end # Game port<br>- device pnp 2e.a on # PME<br>- io 0x60 = 0x800<br>- end<br>- device pnp 2e.b off end # MPU-401<br>- end<br>- end<br>- device pci 1f.1 on end # IDE<br>- device pci 1f.3 on end # SMBus<br>- device pci 1f.5 on end # AC'97 audio<br>- device pci 1f.6 off end # AC'97 modem<br>- end<br>- end<br>-end<br>diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c<br>deleted file mode 100644<br>index b4bf30e..0000000<br>--- a/src/mainboard/thomson/ip1000/gpio.c<br>+++ /dev/null<br>@@ -1,144 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <delay.h><br>-<br>-#define PME_DEV PNP_DEV(0x2e, 0x0a)<br>-#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */<br>-#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */<br>-<br>-/* Early mainboard specific GPIO setup. */<br>-static void mb_gpio_init(void)<br>-{<br>- pci_devfn_t dev;<br>- uint16_t port;<br>- uint32_t set_gpio;<br>-<br>- /* Southbridge GPIOs. */<br>- /* Set the LPC device statically. */<br>- dev = PCI_DEV(0x0, 0x1f, 0x0);<br>-<br>- /* Set the value for GPIO base address register and enable GPIO. */<br>- pci_write_config32(dev, GPIO_BASE, (ICH_IO_BASE_ADDR | 1));<br>- pci_write_config8(dev, GPIO_CNTL, 0x10);<br>-<br>- /* Set GPIO23 to high, this enables the LAN controller. */<br>- udelay(10);<br>- set_gpio = inl(ICH_IO_BASE_ADDR + 0x0c);<br>- set_gpio |= 1 << 23;<br>- outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);<br>-<br>- /* Disable AC97 Modem */<br>- pci_write_config8(dev, 0xf2, 0x40);<br>-<br>- /* Super I/O GPIOs. */<br>- dev = PME_DEV;<br>- port = dev >> 8;<br>-<br>- /* Enter the configuration state. */<br>- outb(0x55, port);<br>- pnp_set_logical_device(dev);<br>- pnp_set_enable(dev, 0);<br>- pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);<br>- pnp_set_enable(dev, 1);<br>-<br>- /* GP21 - LED_RED */<br>- outl(0x01, PME_IO_BASE_ADDR + 0x2c);<br>-<br>- /* GP30 - FAN2_TACH */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x33);<br>-<br>- /* GP31 - FAN1_TACH */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x34);<br>-<br>- /* GP32 - FAN2_CTRL */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x35);<br>-<br>- /* GP33 - FAN1_CTRL */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x36);<br>-<br>- /* GP34 - AUD_MUTE_OUT_R */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x37);<br>-<br>- /* GP36 - KBRST */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x39);<br>-<br>- /* GP37 - A20GATE */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x3a);<br>-<br>- /* GP42 - GPIO_PME_OUT */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x3d);<br>-<br>- /* GP50 - SER2_RI */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x3f);<br>-<br>- /* GP51 - SER2_DCD */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x40);<br>-<br>- /* GP52 - SER2_RX */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x41);<br>-<br>- /* GP53 - SER2_TX */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x42);<br>-<br>- /* GP55 - SER2_RTS */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x44);<br>-<br>- /* GP56 - SER2_CTS */<br>- outl(0x05, PME_IO_BASE_ADDR + 0x45);<br>-<br>- /* GP57 - SER2_DTR */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x46);<br>-<br>- /* GP60 - LED_GREEN */<br>- outl(0x01, PME_IO_BASE_ADDR + 0x47);<br>-<br>- /* GP61 - LED_YELLOW */<br>- outl(0x01, PME_IO_BASE_ADDR + 0x48);<br>-<br>- /* GP3 */<br>- outl(0xc0, PME_IO_BASE_ADDR + 0x4d);<br>-<br>- /* GP4 */<br>- outl(0x04, PME_IO_BASE_ADDR + 0x4e);<br>-<br>- /* FAN1 */<br>- outl(0x01, PME_IO_BASE_ADDR + 0x56);<br>-<br>- /* FAN2 */<br>- outl(0x01, PME_IO_BASE_ADDR + 0x57);<br>-<br>- /* Fan Control */<br>- outl(0x50, PME_IO_BASE_ADDR + 0x58);<br>-<br>- /* Fan1 Tachometer */<br>- outl(0xff, PME_IO_BASE_ADDR + 0x59);<br>-<br>- /* Fan2 Tachometer */<br>- outl(0xff, PME_IO_BASE_ADDR + 0x5a);<br>-<br>- /* LED1 */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x5d);<br>-<br>- /* LED2 */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x5e);<br>-<br>- /* Keyboard Scan Code */<br>- outl(0x00, PME_IO_BASE_ADDR + 0x5f);<br>-<br>- /* Exit the configuration state. */<br>- outb(0xaa, port);<br>-}<br>diff --git a/src/mainboard/thomson/ip1000/irq_tables.c b/src/mainboard/thomson/ip1000/irq_tables.c<br>deleted file mode 100644<br>index e99adfc..0000000<br>--- a/src/mainboard/thomson/ip1000/irq_tables.c<br>+++ /dev/null<br>@@ -1,46 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE, /* u32 signature */<br>- PIRQ_VERSION, /* u16 version */<br>- 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */<br>- 0x00, /* Where the interrupt router lies (bus) */<br>- (0x1f << 3)|0x0, /* Where the interrupt router lies (dev) */<br>- 0, /* IRQs devoted exclusively to PCI usage */<br>- 0x8086, /* Vendor */<br>- 0x24c0, /* Device */<br>- 0, /* Miniport data */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */<br>- 0x07, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */<br>- {<br>- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */<br>- {0x00,(0x02 << 3)|0x0, {{0x60, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IGD VGA */<br>- {0x00,(0x1d << 3)|0x0, {{0x60, 0x0ef8}, {0x63, 0x0ef8}, {0x62, 0x0ef8}, {0x6b, 0x00ef8}}, 0x0, 0x0}, /* [A] USB1, [B] USB2, [C] USB3, [D] EHCI */<br>- {0x00,(0x1f << 3)|0x0, {{0x62, 0x0ef8}, {0x61, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] IDE, [B] SMBUS, [B] AUDIO, [B] MODEM */<br>- {0x01,(0x08 << 3)|0x0, {{0x68, 0x0ef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, /* [A] ETHERNET */<br>- {0x01,(0x00 << 3)|0x0, {{0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x0ef8}, {0x63, 0x00ef8}}, 0x1, 0x0}, /* PCI SLOT 1 */<br>- {0x01,(0x01 << 3)|0x0, {{0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x0ef8}, {0x62, 0x00ef8}}, 0x2, 0x0}, /* PCI SLOT 2 */<br>- {0x01,(0x02 << 3)|0x0, {{0x62, 0x0ef8}, {0x63, 0x0ef8}, {0x60, 0x0ef8}, {0x61, 0x00ef8}}, 0x3, 0x0}, /* PCI SLOT 3 */<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c<br>deleted file mode 100644<br>index bdcc1fa..0000000<br>--- a/src/mainboard/thomson/ip1000/mainboard.c<br>+++ /dev/null<br>@@ -1,97 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org><br>- * Copyright (C) 2010 Stefan Reinauer <stepan@openbios.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <delay.h><br>-#include <drivers/intel/gma/int15.h><br>-#include <arch/io.h><br>-#include <arch/interrupt.h><br>-<br>-// setting the bit disables the led.<br>-#define PARPORT_GPIO_LED_GREEN (1 << 0)<br>-#define PARPORT_GPIO_LED_ORANGE (1 << 1)<br>-#define PARPORT_GPIO_LED_RED (1 << 2)<br>-#define PARPORT_GPIO_IR_PORT (1 << 6)<br>-<br>-static u8 get_parport_gpio(void)<br>-{<br>- return inb(0x378);<br>-}<br>-<br>-static void set_parport_gpio(u8 gpios)<br>-{<br>- outb(gpios, 0x378);<br>-}<br>-<br>-static void parport_gpios(void)<br>-{<br>- u8 pp_gpios = get_parport_gpio();<br>-<br>- /* disable red led */<br>- pp_gpios |= PARPORT_GPIO_LED_RED;<br>- set_parport_gpio(pp_gpios);<br>-<br>- pp_gpios = get_parport_gpio();<br>-<br>- printk(BIOS_DEBUG, "IP1000 GPIOs:\n");<br>- printk(BIOS_DEBUG, " GPIO mask: %02x\n", pp_gpios);<br>- printk(BIOS_DEBUG, " green led: %s\n",<br>- (pp_gpios & PARPORT_GPIO_LED_GREEN) ? "off" : "on");<br>- printk(BIOS_DEBUG, " orange led: %s\n",<br>- (pp_gpios & PARPORT_GPIO_LED_ORANGE) ? "off" : "on");<br>- printk(BIOS_DEBUG, " red led: %s\n",<br>- (pp_gpios & PARPORT_GPIO_LED_RED) ? "off" : "on");<br>- printk(BIOS_DEBUG, " IR port: %s\n",<br>- (pp_gpios & PARPORT_GPIO_IR_PORT) ? "off" : "on");<br>-}<br>-<br>-static void flash_gpios(void)<br>-{<br>- u8 manufacturer_id = read8((u8 *)0xffbc0000);<br>- u8 device_id = read8((u8 *)0xffbc0001);<br>-<br>- if ((manufacturer_id == 0x20) &&<br>- ((device_id == 0x2c) || (device_id == 0x2d))) {<br>- printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n",<br>- (device_id == 0x2c)?'4':'8');<br>- u8 fgpi = read8((u8 *)0xffbc0100);<br>- printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n",<br>- (fgpi & (1 << 0)) ? 'X' : ' ',<br>- (fgpi & (1 << 1)) ? 'X' : ' ',<br>- (fgpi & (1 << 2)) ? 'X' : ' ',<br>- (fgpi & (1 << 3)) ? 'X' : ' ',<br>- (fgpi & (1 << 4)) ? 'X' : ' ');<br>- } else {<br>- printk(BIOS_DEBUG, "No ST M50FW040/M50FW080 flash, don't read FGPI.\n");<br>- }<br>-}<br>-<br>-static void mainboard_init(device_t dev)<br>-{<br>- parport_gpios();<br>- flash_gpios();<br>-}<br>-<br>-static void mainboard_enable(device_t dev)<br>-{<br>- dev->ops->init = mainboard_init;<br>- install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);<br>-}<br>-<br>-struct chip_operations mainboard_ops = {<br>- .enable_dev = mainboard_enable,<br>-};<br>diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c<br>deleted file mode 100644<br>index 9ad1225..0000000<br>--- a/src/mainboard/thomson/ip1000/romstage.c<br>+++ /dev/null<br>@@ -1,114 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <stdlib.h><br>-#include <device/pci_def.h><br>-#include <arch/io.h><br>-#include <device/pnp_def.h><br>-#include <console/console.h><br>-#include <lib.h><br>-#include <superio/smsc/smscsuperio/smscsuperio.h><br>-#include <northbridge/intel/i82830/raminit.h><br>-#include "northbridge/intel/i82830/memory_initialized.c"<br>-#include <southbridge/intel/i82801dx/i82801dx.h><br>-#include "southbridge/intel/i82801dx/reset.c"<br>-#include <cpu/x86/bist.h><br>-#include <cpu/intel/romstage.h><br>-#include "spd_table.h"<br>-#include "gpio.c"<br>-#include "southbridge/intel/i82801dx/tco_timer.c"<br>-<br>-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)<br>-<br>-/**<br>- * The onboard 64MB PC133 memory does not have a SPD EEPROM so the<br>- * values have to be set manually, the SO-DIMM socket is located in<br>- * socket0 (0x50/DIMM0), and the onboard memory is located in socket1<br>- * (0x51/DIMM1).<br>- */<br>-static inline int spd_read_byte(unsigned device, unsigned address)<br>-{<br>- int i;<br>-<br>- if (device == DIMM0) {<br>- return smbus_read_byte(device, address);<br>- } else if (device == DIMM1) {<br>- for (i = 0; i < ARRAY_SIZE(spd_table); i++) {<br>- if (spd_table[i].address == address)<br>- return spd_table[i].data;<br>- }<br>- return 0xFF; /* Return 0xFF when address is not found. */<br>- } else {<br>- return 0xFF; /* Return 0xFF on any failures. */<br>- }<br>-}<br>-<br>-#include "northbridge/intel/i82830/raminit.c"<br>-<br>-/**<br>- * Setup mainboard specific registers pre raminit.<br>- */<br>-static void mb_early_setup(void)<br>-{<br>- /* - Hub Interface to PCI Bridge Registers - */<br>- /* 12-Clock Retry Enable */<br>- pci_write_config16(PCI_DEV(0, 0x1e, 0), 0x50, 0x1402);<br>- /* Master Latency Timer Count */<br>- pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);<br>- /* I/O Address Base */<br>- pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1c, 0xf0);<br>-<br>- /* - LPC Interface Bridge Registers - */<br>- /* Delayed Transaction Enable */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xd0, 0x00000002);<br>- /* Disable the TCO Timer system reboot feature */<br>- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd4, 0x02);<br>- /* CPU Frequency Strap */<br>- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xd5, 0x02);<br>- /* ACPI base address and enable Resource Indicator */<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, (PMBASE_ADDR | 1));<br>- /* Enable the SMBUS */<br>- enable_smbus();<br>- /* ACPI Enable */<br>- pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10);<br>-}<br>-<br>-void mainboard_romstage_entry(unsigned long bist)<br>-{<br>- if (bist == 0) {<br>- if (memory_initialized())<br>- hard_reset();<br>- }<br>-<br>- /* Set southbridge and superio gpios */<br>- mb_gpio_init();<br>-<br>- smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>- console_init();<br>-<br>- /* Halt if there was a built in self test failure. */<br>- report_bist_failure(bist);<br>-<br>- /* disable TCO timers */<br>- i82801dx_halt_tco_timer();<br>-<br>- /* Setup mainboard specific registers */<br>- mb_early_setup();<br>-<br>- /* Initialize memory */<br>- sdram_initialize();<br>-}<br>diff --git a/src/mainboard/thomson/ip1000/smihandler.c b/src/mainboard/thomson/ip1000/smihandler.c<br>deleted file mode 100644<br>index a8a7aca..0000000<br>--- a/src/mainboard/thomson/ip1000/smihandler.c<br>+++ /dev/null<br>@@ -1,25 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <console/console.h><br>-#include <cpu/x86/smm.h><br>-<br>-int mainboard_io_trap_handler(int smif)<br>-{<br>- printk(BIOS_DEBUG, "MAINBOARD IO TRAP HANDLER!\n");<br>- return 1;<br>-}<br>diff --git a/src/mainboard/thomson/ip1000/spd_table.h b/src/mainboard/thomson/ip1000/spd_table.h<br>deleted file mode 100644<br>index 1de05ed..0000000<br>--- a/src/mainboard/thomson/ip1000/spd_table.h<br>+++ /dev/null<br>@@ -1,46 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <spd.h><br>-<br>-#if IS_ENABLED(CONFIG_ONBOARD_MEMORY_64MB)<br>-<br>-#define DENSITY 0x10<br>-<br>-#elif IS_ENABLED(CONFIG_ONBOARD_MEMORY_128MB)<br>-<br>-#define DENSITY 0x20<br>-<br>-#endif<br>-<br>-struct spd_entry {<br>- unsigned int address;<br>- unsigned int data;<br>-};<br>-<br>-/*<br>- * The onboard 64MB PC133 memory does not have an SPD EEPROM so the values<br>- * have to be set manually, the onboard memory is located in socket1 (0x51).<br>- */<br>-const struct spd_entry spd_table [] = {<br>- {SPD_MEMORY_TYPE, 0x04}, /* (Fundamental) memory type */<br>- {SPD_NUM_COLUMNS, 0x09}, /* Number of column address bits */<br>- {SPD_NUM_DIMM_BANKS, 0x01}, /* Number of module rows (banks) */<br>- {SPD_MODULE_DATA_WIDTH_LSB, 0x40}, /* Module data width (LSB) */<br>- {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 0x75}, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) */<br>- {SPD_ACCESS_TIME_FROM_CLOCK, 0x54}, /* SDRAM access time from clock (highest CAS latency), CAS access time (Tac, tCAC) */<br>- {SPD_DENSITY_OF_EACH_ROW_ON_MODULE, DENSITY}, /* Density of each row on module */<br>-};<br>diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig<br>deleted file mode 100644<br>index d0bee8f..0000000<br>--- a/src/northbridge/intel/i82830/Kconfig<br>+++ /dev/null<br>@@ -1,30 +0,0 @@<br>-config NORTHBRIDGE_INTEL_I82830<br>- bool<br>- select NO_MMCONF_SUPPORT<br>- select HAVE_DEBUG_RAM_SETUP<br>- select LATE_CBMEM_INIT<br>- select UDELAY_IO<br>-<br>-choice<br>- prompt "Onboard graphics"<br>- default I830_VIDEO_MB_8MB<br>- depends on NORTHBRIDGE_INTEL_I82830<br>-<br>-config I830_VIDEO_MB_OFF<br>- bool "Disabled, 0KB"<br>-config I830_VIDEO_MB_512KB<br>- bool "Enabled, 512KB"<br>-config I830_VIDEO_MB_1MB<br>- bool "Enabled, 1MB"<br>-config I830_VIDEO_MB_8MB<br>- bool "Enabled, 8MB"<br>-<br>-endchoice<br>-<br>-config VIDEO_MB<br>- int<br>- default 0 if I830_VIDEO_MB_OFF<br>- default 512 if I830_VIDEO_MB_512KB<br>- default 1 if I830_VIDEO_MB_1MB<br>- default 8 if I830_VIDEO_MB_8MB<br>- depends on NORTHBRIDGE_INTEL_I82830<br>diff --git a/src/northbridge/intel/i82830/Makefile.inc b/src/northbridge/intel/i82830/Makefile.inc<br>deleted file mode 100644<br>index ebbae81..0000000<br>--- a/src/northbridge/intel/i82830/Makefile.inc<br>+++ /dev/null<br>@@ -1,8 +0,0 @@<br>-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I82830),y)<br>-<br>-ramstage-y += northbridge.c<br>-ramstage-y += vga.c<br>-<br>-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c<br>-<br>-endif<br>diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h<br>deleted file mode 100644<br>index a4b0a86..0000000<br>--- a/src/northbridge/intel/i82830/i82830.h<br>+++ /dev/null<br>@@ -1,52 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef NORTHBRIDGE_INTEL_I82830_I82830_H<br>-#define NORTHBRIDGE_INTEL_I82830_I82830_H<br>-<br>-#define RRBAR 0x48 /* Register Range Base Address (0x00000000) */<br>-#define GCC0 0x50 /* GMCH Control #0 (0xa072) */<br>-#define GCC1 0x52 /* GMCH Control #1 (0x0000) */<br>-#define FDHC 0x58 /* Fixed DRAM Hole Control (0x00) */<br>-#define PAM0 0x59 /* Programmable Attribute Map #0 (0x00) */<br>-#define PAM1 0x5a /* Programmable Attribute Map #1 (0x00) */<br>-#define PAM2 0x5b /* Programmable Attribute Map #2 (0x00) */<br>-#define PAM3 0x5c /* Programmable Attribute Map #3 (0x00) */<br>-#define PAM4 0x5d /* Programmable Attribute Map #4 (0x00) */<br>-#define PAM5 0x5e /* Programmable Attribute Map #5 (0x00) */<br>-#define PAM6 0x5f /* Programmable Attribute Map #6 (0x00) */<br>-#define DRB 0x60 /* DRAM Row Boundary #0 (0x00) */<br>-#define DRB1 0x61 /* DRAM Row Boundary #1 (0x00) */<br>-#define DRB2 0x62 /* DRAM Row Boundary #2 (0x00) */<br>-#define DRB3 0x63 /* DRAM Row Boundary #3 (0x00) */<br>-#define DRA 0x70 /* DRAM Row Attribute #0 (0xff) */<br>-#define DRA1 0x71 /* DRAM Row Attribute #1 (0xff) */<br>-#define DRT 0x78 /* DRAM Timing (0x00000010) */<br>-#define DRC 0x7c /* DRAM Controller Mode #0 (0x00000000) */<br>-#define DRC1 0x7d /* DRAM Controller Mode #1 (0x00000000) */<br>-#define DRC2 0x7e /* DRAM Controller Mode #2 (0x00000000) */<br>-#define DRC3 0x7f /* DRAM Controller Mode #3 (0x00000000) */<br>-#define DTC 0x8c /* DRAM Throttling Control (0x00000000) */<br>-#define SMRAM 0x90 /* System Management RAM Control (0x02) */<br>-#define ESMRAMC 0x91 /* Extended System Management RAM Control Reg. (0x38) */<br>-#define ERRSTS 0x92 /* Error Status (0x0000) */<br>-#define ERRCMD 0x94 /* Error Command (0x0000) */<br>-#define BUFF_SC 0xec /* System Memory Buffer Strength Control (0x00000000) */<br>-#define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */<br>-#define APSIZE 0xb4 /* Aperture Size (0x00) */<br>-#define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */<br>-<br>-#endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */<br>diff --git a/src/northbridge/intel/i82830/memory_initialized.c b/src/northbridge/intel/i82830/memory_initialized.c<br>deleted file mode 100644<br>index 7ccc1a6..0000000<br>--- a/src/northbridge/intel/i82830/memory_initialized.c<br>+++ /dev/null<br>@@ -1,26 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-<br>-#include "i82830.h"<br>-#define NB_DEV PCI_DEV(0, 0, 0)<br>-<br>-static inline int memory_initialized(void)<br>-{<br>- u32 drc;<br>- drc = pci_read_config32(NB_DEV, DRC);<br>- return (drc & (1<<29));<br>-}<br>diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c<br>deleted file mode 100644<br>index ce9a3fb..0000000<br>--- a/src/northbridge/intel/i82830/northbridge.c<br>+++ /dev/null<br>@@ -1,130 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <cbmem.h><br>-#include <cpu/cpu.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include "i82830.h"<br>-<br>-static void northbridge_init(device_t dev)<br>-{<br>- printk(BIOS_SPEW, "Northbridge init\n");<br>-}<br>-<br>-static struct device_operations northbridge_operations = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = northbridge_init,<br>- .enable = 0,<br>- .ops_pci = 0,<br>-};<br>-<br>-static const struct pci_driver northbridge_driver __pci_driver = {<br>- .ops = &northbridge_operations,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x3575,<br>-};<br>-<br>-static void pci_domain_set_resources(device_t dev)<br>-{<br>- device_t mc_dev;<br>- int igd_memory = 0;<br>- uint64_t uma_memory_base = 0, uma_memory_size = 0;<br>-<br>- mc_dev = dev->link_list->children;<br>- if (!mc_dev)<br>- return;<br>-<br>- unsigned long tomk, tomk_stolen;<br>- int idx;<br>-<br>- if (CONFIG_VIDEO_MB == 512) {<br>- igd_memory = (CONFIG_VIDEO_MB);<br>- printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10);<br>- } else {<br>- igd_memory = (CONFIG_VIDEO_MB * 1024);<br>- printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10);<br>- }<br>-<br>- /* Get the value of the highest DRB. This tells the end of<br>- * the physical memory. The units are ticks of 32MB<br>- * i.e. 1 means 32MB.<br>- */<br>- tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15;<br>- tomk_stolen = tomk - igd_memory;<br>-<br>- /* For reserving UMA memory in the memory map */<br>- uma_memory_base = tomk_stolen * 1024ULL;<br>- uma_memory_size = igd_memory * 1024ULL;<br>- printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk_stolen);<br>-<br>- /* Report the memory regions. */<br>- idx = 10;<br>- ram_resource(dev, idx++, 0, 640);<br>- ram_resource(dev, idx++, 768, tomk - 768);<br>- uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10);<br>-<br>- assign_resources(dev->link_list);<br>-<br>- set_late_cbmem_top(tomk_stolen * 1024);<br>-}<br>-<br>-static struct device_operations pci_domain_ops = {<br>- .read_resources = pci_domain_read_resources,<br>- .set_resources = pci_domain_set_resources,<br>- .enable_resources = NULL,<br>- .init = NULL,<br>- .scan_bus = pci_domain_scan_bus,<br>- .ops_pci_bus = pci_bus_default_ops,<br>-};<br>-<br>-static void cpu_bus_init(device_t dev)<br>-{<br>- initialize_cpus(dev->link_list);<br>-}<br>-<br>-static struct device_operations cpu_bus_ops = {<br>- .read_resources = DEVICE_NOOP,<br>- .set_resources = DEVICE_NOOP,<br>- .enable_resources = DEVICE_NOOP,<br>- .init = cpu_bus_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-static void enable_dev(struct device *dev)<br>-{<br>- struct device_path;<br>-<br>- /* Set the operations if it is a special bus type. */<br>- if (dev->path.type == DEVICE_PATH_DOMAIN) {<br>- dev->ops = &pci_domain_ops;<br>- } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {<br>- dev->ops = &cpu_bus_ops;<br>- }<br>-}<br>-<br>-struct chip_operations northbridge_intel_i82830_ops = {<br>- CHIP_NAME("Intel 82830 Northbridge")<br>- .enable_dev = enable_dev,<br>-};<br>diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c<br>deleted file mode 100644<br>index e0f2c6e..0000000<br>--- a/src/northbridge/intel/i82830/raminit.c<br>+++ /dev/null<br>@@ -1,508 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- *<br>- */<br>-<br>-#include <spd.h><br>-#include <delay.h><br>-#include "lib/debug.c"<br>-#include "i82830.h"<br>-<br>-/*-----------------------------------------------------------------------------<br>-Macros and definitions.<br>------------------------------------------------------------------------------*/<br>-<br>-/* Debugging macros. */<br>-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>-#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x)<br>-#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))<br>-#else<br>-#define PRINTK_DEBUG(x...)<br>-#define DUMPNORTH()<br>-#endif<br>-<br>-/* DRC[10:8] - Refresh Mode Select (RMS).<br>- * 0x0 for Refresh Disabled (Self Refresh)<br>- * 0x1 for Refresh interval 15.6 us for 133MHz<br>- * 0x2 for Refresh interval 7.8 us for 133MHz<br>- * 0x7 for Refresh interval 128 Clocks. (Fast Refresh Mode)<br>- */<br>-#define RAM_COMMAND_REFRESH 0x1<br>-<br>-/* DRC[6:4] - SDRAM Mode Select (SMS). */<br>-#define RAM_COMMAND_SELF_REFRESH 0x0<br>-#define RAM_COMMAND_NOP 0x1<br>-#define RAM_COMMAND_PRECHARGE 0x2<br>-#define RAM_COMMAND_MRS 0x3<br>-#define RAM_COMMAND_CBR 0x6<br>-#define RAM_COMMAND_NORMAL 0x7<br>-<br>-/* DRC[29] - Initialization Complete (IC). */<br>-#define RAM_COMMAND_IC 0x1<br>-<br>-/*-----------------------------------------------------------------------------<br>-DIMM-initialization functions.<br>------------------------------------------------------------------------------*/<br>-<br>-static void do_ram_command(u32 command)<br>-{<br>- u32 reg32;<br>-<br>- /* Configure the RAM command. */<br>- reg32 = pci_read_config32(NORTHBRIDGE, DRC);<br>- /* Clear bits 29, 10-8, 6-4. */<br>- reg32 &= 0xdffff88f;<br>- reg32 |= command << 4;<br>- PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32);<br>- pci_write_config32(NORTHBRIDGE, DRC, reg32);<br>-}<br>-<br>-static void ram_read32(u8 dimm_start, u32 offset)<br>-{<br>- u32 reg32, base_addr = 32 * 1024 * 1024 * dimm_start;<br>- if (offset == 0x55aa55aa) {<br>- reg32 = read32((u32 *)base_addr);<br>- PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);<br>- PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", base_addr, offset);<br>- write32((u32 *)base_addr, offset);<br>- reg32 = read32((u32 *)base_addr);<br>- PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);<br>- } else {<br>- PRINTK_DEBUG(" to 0x%08x\n", base_addr + offset);<br>- read32((u32 *)(base_addr + offset));<br>- }<br>-}<br>-<br>-static void initialize_dimm_rows(void)<br>-{<br>- int i, row;<br>- u8 dimm_start, dimm_end;<br>- unsigned device;<br>-<br>- dimm_start = 0;<br>-<br>- for (row = 0; row < (DIMM_SOCKETS * 2); row++) {<br>-<br>- switch (row) {<br>- case 0:<br>- device = DIMM0;<br>- break;<br>- case 1:<br>- device = DIMM0;<br>- break;<br>- case 2:<br>- device = DIMM0 + 1;<br>- break;<br>- case 3:<br>- device = DIMM0 + 1;<br>- break;<br>- }<br>-<br>- dimm_end = pci_read_config8(NORTHBRIDGE, DRB + row);<br>-<br>- if (dimm_end > dimm_start) {<br>- printk(BIOS_DEBUG, "Initializing SDRAM Row %u\n", row);<br>-<br>- /* NOP command */<br>- PRINTK_DEBUG(" NOP\n");<br>- do_ram_command(RAM_COMMAND_NOP);<br>- ram_read32(dimm_start, 0);<br>- udelay(200);<br>-<br>- /* Pre-charge all banks (at least 200 us after NOP) */<br>- PRINTK_DEBUG(" Pre-charging all banks\n");<br>- do_ram_command(RAM_COMMAND_PRECHARGE);<br>- ram_read32(dimm_start, 0);<br>- udelay(1);<br>-<br>- /* 8 CBR refreshes (Auto Refresh) */<br>- PRINTK_DEBUG(" 8 CBR refreshes\n");<br>- for (i = 0; i < 8; i++) {<br>- do_ram_command(RAM_COMMAND_CBR);<br>- ram_read32(dimm_start, 0);<br>- udelay(1);<br>- }<br>-<br>- /* MRS command */<br>- /* TODO: Set offset 0x1d0 according to DRT values */<br>- PRINTK_DEBUG(" MRS\n");<br>- do_ram_command(RAM_COMMAND_MRS);<br>- ram_read32(dimm_start, 0x1d0);<br>- udelay(2);<br>-<br>- /* Set GMCH-M Mode Select bits back to NORMAL operation mode */<br>- PRINTK_DEBUG(" Normal operation mode\n");<br>- do_ram_command(RAM_COMMAND_NORMAL);<br>- ram_read32(dimm_start, 0);<br>- udelay(1);<br>-<br>- /* Perform a dummy memory read/write cycle */<br>- PRINTK_DEBUG(" Performing dummy read/write\n");<br>- ram_read32(dimm_start, 0x55aa55aa);<br>- udelay(1);<br>- }<br>- /* Set the start of the next DIMM. */<br>- dimm_start = dimm_end;<br>- }<br>-}<br>-<br>-/*-----------------------------------------------------------------------------<br>-DIMM-independent configuration functions.<br>------------------------------------------------------------------------------*/<br>-<br>-struct dimm_size {<br>- unsigned int side1;<br>- unsigned int side2;<br>-};<br>-<br>-static struct dimm_size spd_get_dimm_size(unsigned device)<br>-{<br>- struct dimm_size sz;<br>- int i, module_density, dimm_banks;<br>- sz.side1 = 0;<br>- module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);<br>- dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS);<br>-<br>- /* Find the size of side1. */<br>- /* Find the larger value. The larger value is always side1. */<br>- for (i = 512; i >= 0; i >>= 1) {<br>- if ((module_density & i) == i) {<br>- sz.side1 = i;<br>- break;<br>- }<br>- }<br>-<br>- /* Set to 0 in case it's single sided. */<br>- sz.side2 = 0;<br>-<br>- /* Test if it's a dual-sided DIMM. */<br>- if (dimm_banks > 1) {<br>- /* Test to see if there's a second value, if so it's asymmetrical. */<br>- if (module_density != i) {<br>- /* Find the second value, picking up where we left off. */<br>- /* i >>= 1 done initially to make sure we don't get the same value again. */<br>- for (i >>= 1; i >= 0; i >>= 1) {<br>- if (module_density == (sz.side1 | i)) {<br>- sz.side2 = i;<br>- break;<br>- }<br>- }<br>- /* If not, it's symmetrical */<br>- } else {<br>- sz.side2 = sz.side1;<br>- }<br>- }<br>-<br>- /* SPD byte 31 is the memory size divided by 4 so we<br>- * need to multiply by 4 to get the total size.<br>- */<br>- sz.side1 *= 4;<br>- sz.side2 *= 4;<br>- return sz;<br>-}<br>-<br>-static void set_dram_row_boundaries(void)<br>-{<br>- int i, value, drb1, drb2;<br>-<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- struct dimm_size sz;<br>- unsigned device;<br>- device = DIMM0 + i;<br>- drb1 = 0;<br>- drb2 = 0;<br>-<br>- /* First check if a DIMM is actually present. */<br>- if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {<br>- printk(BIOS_DEBUG, "Found DIMM in slot %u\n", i);<br>- sz = spd_get_dimm_size(device);<br>- printk(BIOS_DEBUG, " DIMM is %uMB on side 1\n", sz.side1);<br>- printk(BIOS_DEBUG, " DIMM is %uMB on side 2\n", sz.side2);<br>-<br>- /* - Memory compatibility checks - */<br>-<br>- /* Test for PC133 (i82830 only supports PC133) */<br>- /* PC133 SPD9 - cycle time is always 75 */<br>- if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) {<br>- printk(BIOS_ERR, "SPD9 DIMM Is Not PC133 Compatable\n");<br>- die("HALT\n");<br>- }<br>- /* PC133 SPD10 - access time is always 54 */<br>- if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) {<br>- printk(BIOS_ERR, "SPD10 DIMM Is Not PC133 Compatable\n");<br>- die("HALT\n");<br>- }<br>-<br>- /* The i82830 only supports a symmetrical dual-sided dimms<br>- * and can't handle DIMMs smaller than 32MB per<br>- * side or larger than 256MB per side.<br>- */<br>- if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {<br>- printk(BIOS_ERR, "This northbridge only supports\n");<br>- printk(BIOS_ERR, "symmetrical dual-sided DIMMs\n");<br>- printk(BIOS_ERR, "booting as a single-sided DIMM\n");<br>- sz.side2 = 0;<br>- }<br>- if ((sz.side1 < 32)) {<br>- printk(BIOS_ERR, "DIMMs smaller than 32MB per side\n");<br>- printk(BIOS_ERR, "are not supported on this northbridge\n");<br>- die("HALT\n");<br>- }<br>-<br>- if ((sz.side1 > 256)) {<br>- printk(BIOS_ERR, "DIMMs larger than 256MB per side\n");<br>- printk(BIOS_ERR, "are not supported on this northbridge\n");<br>- die("HALT\n");<br>- }<br>- /* - End Memory compatibility checks - */<br>-<br>- /* We need to divide size by 32 to set up the<br>- * DRB registers.<br>- */<br>- if (sz.side1)<br>- drb1 = sz.side1 / 32;<br>- if (sz.side2)<br>- drb2 = sz.side2 / 32;<br>- } else {<br>- printk(BIOS_DEBUG, "No DIMM found in slot %u\n", i);<br>-<br>- /* If there's no DIMM in the slot, set value to 0. */<br>- drb1 = 0;<br>- drb2 = 0;<br>- }<br>- /* Set the value for DRAM Row Boundary Registers */<br>- if (i == 0) {<br>- pci_write_config8(NORTHBRIDGE, DRB, drb1);<br>- pci_write_config8(NORTHBRIDGE, DRB + 1, drb1 + drb2);<br>- PRINTK_DEBUG(" DRB 0x%02x has been set to 0x%02x\n", DRB, drb1);<br>- PRINTK_DEBUG(" DRB1 0x%02x has been set to 0x%02x\n", DRB + 1, drb1 + drb2);<br>- } else if (i == 1) {<br>- value = pci_read_config8(NORTHBRIDGE, DRB + 1);<br>- pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1);<br>- pci_write_config8(NORTHBRIDGE, DRB + 3, value + drb1 + drb2);<br>- PRINTK_DEBUG(" DRB2 0x%02x has been set to 0x%02x\n", DRB + 2, value + drb1);<br>- PRINTK_DEBUG(" DRB3 0x%02x has been set to 0x%02x\n", DRB + 3, value + drb1 + drb2);<br>-<br>- /* We need to set the highest DRB value to 0x64 and 0x65.<br>- * These are supposed to be "Reserved" but memory will<br>- * not initialize properly if we don't.<br>- */<br>- value = pci_read_config8(NORTHBRIDGE, DRB + 3);<br>- pci_write_config8(NORTHBRIDGE, DRB + 4, value);<br>- pci_write_config8(NORTHBRIDGE, DRB + 5, value);<br>- }<br>- }<br>-}<br>-<br>-static void set_dram_row_attributes(void)<br>-{<br>- int i, dra, col, width, value;<br>-<br>- for (i = 0; i < DIMM_SOCKETS; i++) {<br>- unsigned device;<br>- device = DIMM0 + i;<br>-<br>- /* First check if a DIMM is actually present. */<br>- if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {<br>- PRINTK_DEBUG("Found DIMM in slot %u\n", i);<br>-<br>- dra = 0x00;<br>-<br>- /* columns */<br>- col = spd_read_byte(device, SPD_NUM_COLUMNS);<br>-<br>- /* data width */<br>- width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);<br>-<br>- /* calculate page size in bits */<br>- value = ((1 << col) * width);<br>-<br>- /* convert to Kilobytes */<br>- dra = ((value / 8) >> 10);<br>-<br>- /* # of banks of DIMM (single or double sided) */<br>- value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);<br>-<br>- if (value == 1) {<br>- if (dra == 2) {<br>- dra = 0xF0; /* 2KB */<br>- } else if (dra == 4) {<br>- dra = 0xF1; /* 4KB */<br>- } else if (dra == 8) {<br>- dra = 0xF2; /* 8KB */<br>- } else if (dra == 16) {<br>- dra = 0xF3; /* 16KB */<br>- } else {<br>- printk(BIOS_ERR, "Page size not supported\n");<br>- die("HALT\n");<br>- }<br>- } else if (value == 2) {<br>- if (dra == 2) {<br>- dra = 0x00; /* 2KB */<br>- } else if (dra == 4) {<br>- dra = 0x11; /* 4KB */<br>- } else if (dra == 8) {<br>- dra = 0x22; /* 8KB */<br>- } else if (dra == 16) {<br>- dra = 0x33; /* 16KB */<br>- } else {<br>- printk(BIOS_ERR, "Page size not supported\n");<br>- die("HALT\n");<br>- }<br>- } else {<br>- printk(BIOS_ERR, "# of banks of DIMM not supported\n");<br>- die("HALT\n");<br>- }<br>-<br>- } else {<br>- PRINTK_DEBUG("No DIMM found in slot %u\n", i);<br>-<br>- /* If there's no DIMM in the slot, set dra value to 0xFF. */<br>- dra = 0xFF;<br>- }<br>-<br>- /* Set the value for DRAM Row Attribute Registers */<br>- pci_write_config8(NORTHBRIDGE, DRA + i, dra);<br>- PRINTK_DEBUG(" DRA 0x%02x has been set to 0x%02x\n", DRA + i, dra);<br>- }<br>-}<br>-<br>-static void set_dram_timing(void)<br>-{<br>- /* Set the value for DRAM Timing Register */<br>- /* TODO: Configure the value according to SPD values. */<br>- pci_write_config32(NORTHBRIDGE, DRT, 0x00000010);<br>-}<br>-<br>-static void set_dram_buffer_strength(void)<br>-{<br>- /* TODO: This needs to be set according to the DRAM tech<br>- * (x8, x16, or x32). Argh, Intel provides no docs on this!<br>- * Currently, it needs to be pulled from the output of<br>- * lspci -xxx Rx92<br>- */<br>-<br>- /* Set the value for System Memory Buffer Strength Control Registers */<br>- pci_write_config32(NORTHBRIDGE, BUFF_SC, 0xFC9B491B);<br>-}<br>-<br>-/*-----------------------------------------------------------------------------<br>-Public interface.<br>------------------------------------------------------------------------------*/<br>-<br>-static void sdram_set_registers(void)<br>-{<br>- printk(BIOS_DEBUG, "Setting initial SDRAM registers....\n");<br>-<br>- /* Calculate the value for DRT DRAM Timing Register */<br>- set_dram_timing();<br>-<br>- /* Setup System Memory Buffer Strength Control Registers */<br>- set_dram_buffer_strength();<br>-<br>- /* Setup DRAM Row Boundary Registers */<br>- set_dram_row_boundaries();<br>-<br>- /* Setup DRAM Row Attribute Registers */<br>- set_dram_row_attributes();<br>-<br>- printk(BIOS_DEBUG, "Initial SDRAM registers have been set.\n");<br>-}<br>-<br>-static void northbridge_set_registers(void)<br>-{<br>- u16 value;<br>- int igd_memory = 0;<br>-<br>- printk(BIOS_DEBUG, "Setting initial Northbridge registers....\n");<br>-<br>- /* Set the value for Fixed DRAM Hole Control Register */<br>- pci_write_config8(NORTHBRIDGE, FDHC, 0x00);<br>-<br>- /* Set the value for Programmable Attribute Map Registers<br>- * Ideally, this should be R/W for as many ranges as possible.<br>- */<br>- pci_write_config8(NORTHBRIDGE, PAM0, 0x30);<br>- pci_write_config8(NORTHBRIDGE, PAM1, 0x33);<br>- pci_write_config8(NORTHBRIDGE, PAM2, 0x33);<br>- pci_write_config8(NORTHBRIDGE, PAM3, 0x33);<br>- pci_write_config8(NORTHBRIDGE, PAM4, 0x33);<br>- pci_write_config8(NORTHBRIDGE, PAM5, 0x33);<br>- pci_write_config8(NORTHBRIDGE, PAM6, 0x33);<br>-<br>- /* Set the value for System Management RAM Control Register */<br>- pci_write_config8(NORTHBRIDGE, SMRAM, 0x02);<br>-<br>- /* Set the value for GMCH Control Register #0 */<br>- pci_write_config16(NORTHBRIDGE, GCC0, 0xA072);<br>-<br>- /* Set the value for Aperture Base Configuration Register */<br>- pci_write_config32(NORTHBRIDGE, APBASE, 0x00000008);<br>-<br>- /* Set the value for GMCH Control Register #1 */<br>- switch (CONFIG_VIDEO_MB) {<br>- case 512: /* 512K of memory */<br>- igd_memory = 0x2;<br>- break;<br>- case 1: /* 1M of memory */<br>- igd_memory = 0x3;<br>- break;<br>- case 8: /* 8M of memory */<br>- igd_memory = 0x4;<br>- break;<br>- default: /* No memory */<br>- pci_write_config16(NORTHBRIDGE, GCC1, 0x0002);<br>- igd_memory = 0x0;<br>- }<br>-<br>- value = pci_read_config16(NORTHBRIDGE, GCC1);<br>- value |= igd_memory << 4;<br>- value |= 1; // 64MB aperture<br>- pci_write_config16(NORTHBRIDGE, GCC1, value);<br>-<br>- printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n");<br>-}<br>-<br>-static void sdram_initialize(void)<br>-{<br>- u32 reg32;<br>-<br>- /* Setup Initial SDRAM Registers */<br>- sdram_set_registers();<br>-<br>- /* Wait until power/voltages and clocks are stable (200us). */<br>- udelay(200);<br>-<br>- /* Initialize each row of memory one at a time */<br>- initialize_dimm_rows();<br>-<br>- /* Enable Refresh */<br>- PRINTK_DEBUG("Enabling Refresh\n");<br>- reg32 = pci_read_config32(NORTHBRIDGE, DRC);<br>- reg32 |= (RAM_COMMAND_REFRESH << 8);<br>- pci_write_config32(NORTHBRIDGE, DRC, reg32);<br>-<br>- /* Set initialization complete */<br>- PRINTK_DEBUG("Setting initialization complete\n");<br>- reg32 = pci_read_config32(NORTHBRIDGE, DRC);<br>- reg32 |= (RAM_COMMAND_IC << 29);<br>- pci_write_config32(NORTHBRIDGE, DRC, reg32);<br>-<br>- /* Setup Initial Northbridge Registers */<br>- northbridge_set_registers();<br>-<br>- PRINTK_DEBUG("Northbridge following SDRAM init:\n");<br>- DUMPNORTH();<br>-}<br>diff --git a/src/northbridge/intel/i82830/raminit.h b/src/northbridge/intel/i82830/raminit.h<br>deleted file mode 100644<br>index 6b51db1..0000000<br>--- a/src/northbridge/intel/i82830/raminit.h<br>+++ /dev/null<br>@@ -1,26 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef NORTHBRIDGE_INTEL_I82830_RAMINIT_H<br>-#define NORTHBRIDGE_INTEL_I82830_RAMINIT_H<br>-<br>-/* 82830 Northbridge PCI device */<br>-#define NORTHBRIDGE PCI_DEV(0, 0, 0)<br>-<br>-/* The 82830 supports max. 2 dual-sided SO-DIMMs. */<br>-#define DIMM_SOCKETS 2<br>-<br>-#endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */<br>diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c<br>deleted file mode 100644<br>index 569e62e..0000000<br>--- a/src/northbridge/intel/i82830/smihandler.c<br>+++ /dev/null<br>@@ -1,387 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2010 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <types.h><br>-#include <compiler.h><br>-#include <string.h><br>-#include <arch/io.h><br>-#include <console/console.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/x86/smm.h><br>-#include <device/pci_def.h><br>-#include "i82830.h"<br>-<br>-extern unsigned char *mbi;<br>-extern u32 mbi_len;<br>-<br>-// #define DEBUG_SMI_I82830<br>-<br>-/* If YABEL is enabled and it's not running at 0x00000000, we have to add some<br>- * offset to all our mbi object memory accesses<br>- */<br>-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && !CONFIG_YABEL_DIRECTHW<br>-#define OBJ_OFFSET CONFIG_YABEL_VIRTMEM_LOCATION<br>-#else<br>-#define OBJ_OFFSET 0x00000<br>-#endif<br>-<br>-/* I830M */<br>-#define SMRAM 0x90<br>-#define D_OPEN (1 << 6)<br>-#define D_CLS (1 << 5)<br>-#define D_LCK (1 << 4)<br>-#define G_SMRANE (1 << 3)<br>-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))<br>-<br>-<br>-typedef struct {<br>- u32 mhid;<br>- u32 function;<br>- u32 retsts;<br>- u32 rfu;<br>-} __packed banner_id_t;<br>-<br>-#define MSH_OK 0x0000<br>-#define MSH_OK_RESTART 0x0001<br>-#define MSH_FWH_ERR 0x00ff<br>-#define MSH_IF_BAD_ID 0x0100<br>-#define MSH_IF_BAD_FUNC 0x0101<br>-#define MSH_IF_MBI_CORRUPT 0x0102<br>-#define MSH_IF_BAD_HANDLE 0x0103<br>-#define MSH_ALRDY_ATCHED 0x0104<br>-#define MSH_NOT_ATCHED 0x0105<br>-#define MSH_IF 0x0106<br>-#define MSH_IF_INVADDR 0x0107<br>-#define MSH_IF_UKN_TYPE 0x0108<br>-#define MSH_IF_NOT_FOUND 0x0109<br>-#define MSH_IF_NO_KEY 0x010a<br>-#define MSH_IF_BUF_SIZE 0x010b<br>-#define MSH_IF_NOT_PENDING 0x010c<br>-<br>-#ifdef DEBUG_SMI_I82830<br>-static void<br>-dump(u8 * addr, u32 len)<br>-{<br>- printk(BIOS_DEBUG, "\n%s(%p, %x):\n", __func__, addr, len);<br>- while (len) {<br>- unsigned int tmpCnt = len;<br>- unsigned char x;<br>- if (tmpCnt > 8)<br>- tmpCnt = 8;<br>- printk(BIOS_DEBUG, "\n%p: ", addr);<br>- // print hex<br>- while (tmpCnt--) {<br>- x = *addr++;<br>- printk(BIOS_DEBUG, "%02x ", x);<br>- }<br>- tmpCnt = len;<br>- if (tmpCnt > 8)<br>- tmpCnt = 8;<br>- len -= tmpCnt;<br>- //reset addr ptr to print ascii<br>- addr = addr - tmpCnt;<br>- // print ascii<br>- while (tmpCnt--) {<br>- x = *addr++;<br>- if ((x < 32) || (x >= 127)) {<br>- //non-printable char<br>- x = '.';<br>- }<br>- printk(BIOS_DEBUG, "%c", x);<br>- }<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-#endif<br>-<br>-typedef struct {<br>- banner_id_t banner;<br>- u16 versionmajor;<br>- u16 versionminor;<br>- u32 smicombuffersize;<br>-} __packed version_t;<br>-<br>-typedef struct {<br>- u16 header_id;<br>- u16 attributes;<br>- u16 size;<br>- u8 name_len;<br>- u8 reserved;<br>- u32 type;<br>- u32 header_ext;<br>- u8 name[0];<br>-} __packed mbi_header_t;<br>-<br>-typedef struct {<br>- banner_id_t banner;<br>- u64 handle;<br>- u32 objnum;<br>- mbi_header_t header;<br>-} __packed obj_header_t;<br>-<br>-typedef struct {<br>- banner_id_t banner;<br>- u64 handle;<br>- u32 objnum;<br>- u32 start;<br>- u32 numbytes;<br>- u32 buflen;<br>- u32 buffer;<br>-} __packed get_object_t;<br>-<br>-static void mbi_call(u8 subf, banner_id_t *banner_id)<br>-{<br>-#ifdef DEBUG_SMI_I82830<br>- printk(BIOS_DEBUG, "MBI\n");<br>- printk(BIOS_DEBUG, "|- sub function %x\n", subf);<br>- printk(BIOS_DEBUG, "|- banner id @ %x\n", (u32)banner_id);<br>- printk(BIOS_DEBUG, "| |- mhid %x\n", banner_id->mhid);<br>- printk(BIOS_DEBUG, "| |- function %x\n", banner_id->function);<br>- printk(BIOS_DEBUG, "| |- return status %x\n", banner_id->retsts);<br>- printk(BIOS_DEBUG, "| |- rfu %x\n", banner_id->rfu);<br>-#endif<br>-<br>- switch(banner_id->function) {<br>- case 0x0001: {<br>- version_t *version;<br>- printk(BIOS_DEBUG, "|- MBI_QueryInterface\n");<br>- version = (version_t *)banner_id;<br>- version->banner.retsts = MSH_OK;<br>- version->versionmajor = 1;<br>- version->versionminor = 3;<br>- version->smicombuffersize = 0x1000;<br>- break;<br>- }<br>- case 0x0002:<br>- printk(BIOS_DEBUG, "|- MBI_Attach\n");<br>- printk(BIOS_DEBUG, "| |- Not Implemented!\n");<br>- break;<br>- case 0x0003:<br>- printk(BIOS_DEBUG, "|- MBI_Detach\n");<br>- printk(BIOS_DEBUG, "| |- Not Implemented!\n");<br>- break;<br>- case 0x0201: {<br>- obj_header_t *obj_header = (obj_header_t *)banner_id;<br>- mbi_header_t *mbi_header = NULL;<br>- printk(BIOS_DEBUG, "|- MBI_GetObjectHeader\n");<br>- printk(BIOS_DEBUG, "| |- objnum = %d\n", obj_header->objnum);<br>-<br>- int i, count = 0;<br>- obj_header->banner.retsts = MSH_IF_NOT_FOUND;<br>-<br>- for (i = 0; i < mbi_len;) {<br>- int len;<br>-<br>- if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {<br>- i+=16;<br>- continue;<br>- }<br>-<br>- mbi_header = (mbi_header_t *)&mbi[i];<br>- len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);<br>-<br>- if (obj_header->objnum == count) {<br>-#ifdef DEBUG_SMI_I82830<br>- if (mbi_header->name_len == 0xff) {<br>- printk(BIOS_DEBUG, "| |- corrupt.\n");<br>- break;<br>- }<br>-#endif<br>- int headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);<br>-#ifdef DEBUG_SMI_I82830<br>- printk(BIOS_DEBUG, "| |- headerlen = %d\n", headerlen);<br>-#endif<br>- memcpy(&obj_header->header, mbi_header, headerlen);<br>- obj_header->banner.retsts = MSH_OK;<br>- printk(BIOS_DEBUG, "| |- MBI module '");<br>- int j;<br>- for (j = 0; j < mbi_header->name_len && mbi_header->name[j]; j++)<br>- printk(BIOS_DEBUG, "%c", mbi_header->name[j]);<br>- printk(BIOS_DEBUG, "' found.\n");<br>-#ifdef DEBUG_SMI_I82830<br>- dump((u8 *)banner_id, sizeof(obj_header_t) + ALIGN(mbi_header->name_len, 16));<br>-#endif<br>- break;<br>- }<br>- i += len;<br>- count++;<br>- }<br>- if (obj_header->banner.retsts == MSH_IF_NOT_FOUND)<br>- printk(BIOS_DEBUG, "| |- MBI object #%d not found.\n", obj_header->objnum);<br>- break;<br>- }<br>- case 0x0203: {<br>- get_object_t *getobj = (get_object_t *)banner_id;<br>- mbi_header_t *mbi_header = NULL;<br>- printk(BIOS_DEBUG, "|- MBI_GetObject\n");<br>-#ifdef DEBUG_SMI_I82830<br>- printk(BIOS_DEBUG, "| |- handle = %016Lx\n", getobj->handle);<br>-#endif<br>- printk(BIOS_DEBUG, "| |- objnum = %d\n", getobj->objnum);<br>- printk(BIOS_DEBUG, "| |- start = %x\n", getobj->start);<br>- printk(BIOS_DEBUG, "| |- numbytes = %x\n", getobj->numbytes);<br>- printk(BIOS_DEBUG, "| |- buflen = %x\n", getobj->buflen);<br>- printk(BIOS_DEBUG, "| |- buffer = %x\n", getobj->buffer);<br>-<br>- int i, count = 0;<br>- getobj->banner.retsts = MSH_IF_NOT_FOUND;<br>-<br>- for (i = 0; i< mbi_len;) {<br>- int headerlen, objectlen;<br>-<br>- if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) {<br>- i+=16;<br>- continue;<br>- }<br>-<br>- mbi_header = (mbi_header_t *)&mbi[i];<br>- headerlen = ALIGN(sizeof(mbi_header) + ALIGN(mbi_header->name_len, 16), 16);<br>- objectlen = ALIGN((mbi_header->size * 16), 16);<br>-<br>- if (getobj->objnum == count) {<br>- printk(BIOS_DEBUG, "| |- len = %x\n", headerlen + objectlen);<br>-<br>- memcpy((void *)(getobj->buffer + OBJ_OFFSET),<br>- ((char *)mbi_header) + headerlen, (objectlen > getobj->buflen) ? getobj->buflen : objectlen);<br>-<br>- getobj->banner.retsts = MSH_OK;<br>-#ifdef DEBUG_SMI_I82830<br>- dump((u8 *)banner_id, sizeof(*getobj));<br>- dump((u8 *)getobj->buffer + OBJ_OFFSET, objectlen);<br>-#endif<br>- break;<br>- }<br>- i += (headerlen + objectlen);<br>- count++;<br>- }<br>- if (getobj->banner.retsts == MSH_IF_NOT_FOUND)<br>- printk(BIOS_DEBUG, "MBI module %d not found.\n", getobj->objnum);<br>- break;<br>- }<br>- default:<br>- printk(BIOS_DEBUG, "|- function %x\n", banner_id->function);<br>- printk(BIOS_DEBUG, "| |- Unknown Function!\n");<br>- break;<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>- //dump(banner_id, 0x20);<br>-}<br>-<br>-#define SMI_IFC_SUCCESS 1<br>-#define SMI_IFC_FAILURE_GENERIC 0<br>-#define SMI_IFC_FAILURE_INVALID 2<br>-#define SMI_IFC_FAILURE_CRITICAL 4<br>-#define SMI_IFC_FAILURE_NONCRITICAL 6<br>-<br>-#define PC10 0x10<br>-#define PC11 0x11<br>-#define PC12 0x12<br>-#define PC13 0x13<br>-<br>-static void smi_interface_call(void)<br>-{<br>- u8 *mmio = (u8 *)pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);<br>- // mmio &= 0xfff80000;<br>- // printk(BIOS_DEBUG, "mmio=%x\n", mmio);<br>- u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);<br>-<br>- if (!(swsmi & 1))<br>- return;<br>-<br>- swsmi &= ~(1 << 0); // clear SMI toggle<br>-<br>- switch ((swsmi>>1) & 0xf) {<br>- case 0:<br>- printk(BIOS_DEBUG, "Interface Function Presence Test.\n");<br>- swsmi = 0;<br>- swsmi &= ~(7 << 5); // Exit: Result<br>- swsmi |= (SMI_IFC_SUCCESS << 5);<br>- swsmi &= 0xff;<br>- swsmi |= (PC13 << 8);<br>- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);<br>- // write magic<br>- write32(mmio + 0x71428, 0x494e5443);<br>- return;<br>- case 4:<br>- printk(BIOS_DEBUG, "Get BIOS Data.\n");<br>- printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);<br>- break;<br>- case 5:<br>- printk(BIOS_DEBUG, "Call MBI Functions.\n");<br>- mbi_call(swsmi >> 8, (banner_id_t *)((read32(mmio + 0x71428) & 0x000fffff) + OBJ_OFFSET) );<br>- // swsmi = 0x0000;<br>- swsmi &= ~(7 << 5); // Exit: Result<br>- swsmi |= (SMI_IFC_SUCCESS << 5);<br>- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);<br>- return;<br>- case 6:<br>- printk(BIOS_DEBUG, "System BIOS Callbacks.\n");<br>- printk(BIOS_DEBUG, "swsmi=%04x\n", swsmi);<br>- break;<br>- default:<br>- printk(BIOS_DEBUG, "Unknown SMI interface call %04x\n", swsmi);<br>- break;<br>- }<br>-<br>- swsmi &= ~(7 << 5); // Exit: Result<br>- swsmi |= (SMI_IFC_FAILURE_CRITICAL << 7);<br>- pci_write_config16(PCI_DEV(0, 0x02, 0), 0xe0, swsmi);<br>-}<br>-<br>-/**<br>- * @brief read and clear ERRSTS<br>- * @return ERRSTS register<br>- */<br>-static u16 reset_err_status(void)<br>-{<br>- u16 reg16;<br>-<br>- reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), ERRSTS);<br>- /* set status bits are cleared by writing 1 to them */<br>- pci_write_config16(PCI_DEV(0, 0x00, 0), ERRSTS, reg16);<br>-<br>- return reg16;<br>-}<br>-<br>-static void dump_err_status(u32 errsts)<br>-{<br>- printk(BIOS_DEBUG, "ERRSTS: ");<br>- if (errsts & (1 << 12)) printk(BIOS_DEBUG, "MBI ");<br>- if (errsts & (1 << 9)) printk(BIOS_DEBUG, "LCKF ");<br>- if (errsts & (1 << 8)) printk(BIOS_DEBUG, "DTF ");<br>- if (errsts & (1 << 5)) printk(BIOS_DEBUG, "UNSC ");<br>- if (errsts & (1 << 4)) printk(BIOS_DEBUG, "OOGF ");<br>- if (errsts & (1 << 3)) printk(BIOS_DEBUG, "IAAF ");<br>- if (errsts & (1 << 2)) printk(BIOS_DEBUG, "ITTEF ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>- u16 errsts;<br>-<br>- /* We need to clear the SMI status registers, or we won't see what's<br>- * happening in the following calls.<br>- */<br>- errsts = reset_err_status();<br>- if (errsts & (1 << 12)) {<br>- smi_interface_call();<br>- } else {<br>- if (errsts)<br>- dump_err_status(errsts);<br>- }<br>-<br>-}<br>diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c<br>deleted file mode 100644<br>index 20c9d0a..0000000<br>--- a/src/northbridge/intel/i82830/vga.c<br>+++ /dev/null<br>@@ -1,87 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2009 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <cbfs.h><br>-#include <x86emu/x86emu.h><br>-<br>-static void vga_init(device_t dev)<br>-{<br>- printk(BIOS_INFO, "Starting Graphics Initialization\n");<br>- size_t mbi_len;<br>- void *mbi = cbfs_boot_map_with_leak("mbi.bin", CBFS_TYPE_MBI, &mbi_len);<br>-<br>- if (mbi && mbi_len) {<br>- /* The GDT or coreboot table is going to live here. But<br>- * a long time after we relocated the GNVS, so this is<br>- * not troublesome.<br>- */<br>- *(u32 *)0x500 = (u32)mbi;<br>- *(u32 *)0x504 = (u32)mbi_len;<br>- outb(0xeb, 0xb2);<br>- }<br>-<br>- pci_dev_init(dev);<br>- printk(BIOS_INFO, "Graphics Initialization Complete\n");<br>-<br>- /* Enable TV-Out */<br>-#if IS_ENABLED(CONFIG_PCI_OPTION_ROM_RUN_YABEL)<br>-#define PIPE_A_CRT (1 << 0)<br>-#define PIPE_A_LFP (1 << 1)<br>-#define PIPE_A_TV (1 << 3)<br>-#define PIPE_B_CRT (1 << 8)<br>-#define PIPE_B_TV (1 << 10)<br>- printk(BIOS_DEBUG, "Enabling TV-Out\n");<br>- void runInt10(void);<br>- X86_AX = 0x5f64;<br>- X86_BX = 0x0001; // Set Display Device, force execution<br>- X86_CX = PIPE_A_CRT | PIPE_A_TV;<br>- // M.x86.R_CX = PIPE_B_TV;<br>- runInt10();<br>- switch (X86_AX) {<br>- case 0x005f:<br>- printk(BIOS_DEBUG, "... failed.\n");<br>- break;<br>- case 0x015f:<br>- printk(BIOS_DEBUG, "... ok.\n");<br>- break;<br>- default:<br>- printk(BIOS_DEBUG, "... not supported.\n");<br>- break;<br>- }<br>-#endif<br>-}<br>-<br>-static const struct device_operations vga_operations = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = vga_init,<br>- .scan_bus = 0,<br>- .enable = 0,<br>- .ops_pci = 0,<br>-};<br>-<br>-static const struct pci_driver vga_driver __pci_driver = {<br>- .ops = &vga_operations,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x3577,<br>-};<br>diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig<br>deleted file mode 100644<br>index 35e597a..0000000<br>--- a/src/southbridge/intel/i82801dx/Kconfig<br>+++ /dev/null<br>@@ -1,38 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2008-2009 coresystems GmbH<br>-##<br>-## This program is free software; you can redistribute it and/or<br>-## modify it under the terms of the GNU General Public License as<br>-## published by the Free Software Foundation; version 2 of<br>-## the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-config SOUTHBRIDGE_INTEL_I82801DX<br>- bool<br>- select ACPI_INTEL_HARDWARE_SLEEP_VALUES<br>- select SOUTHBRIDGE_INTEL_COMMON<br>- select IOAPIC<br>- select HAVE_HARD_RESET<br>- select HAVE_SMI_HANDLER<br>- select HAVE_USBDEBUG<br>- select SOUTHBRIDGE_INTEL_COMMON<br>- select SOUTHBRIDGE_INTEL_COMMON_SMBUS<br>-<br>-if SOUTHBRIDGE_INTEL_I82801DX<br>-<br>-config EHCI_BAR<br>- hex<br>- default 0xfef00000<br>-<br>-config BOOTBLOCK_SOUTHBRIDGE_INIT<br>- string<br>- default "southbridge/intel/i82801dx/bootblock.c"<br>-<br>-endif<br>diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc<br>deleted file mode 100644<br>index c514883..0000000<br>--- a/src/southbridge/intel/i82801dx/Makefile.inc<br>+++ /dev/null<br>@@ -1,35 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2008-2009 coresystems GmbH<br>-##<br>-## This program is free software; you can redistribute it and/or<br>-## modify it under the terms of the GNU General Public License as<br>-## published by the Free Software Foundation; version 2 of<br>-## the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801DX),y)<br>-<br>-ramstage-y += i82801dx.c<br>-ramstage-y += ac97.c<br>-ramstage-y += ide.c<br>-ramstage-y += lpc.c<br>-#ramstage-y += pci.c<br>-ramstage-y += usb.c<br>-ramstage-y += usb2.c<br>-<br>-ramstage-y += reset.c<br>-<br>-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c<br>-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S<br>-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c<br>-<br>-romstage-y += early_smbus.c<br>-<br>-endif<br>diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c<br>deleted file mode 100644<br>index 3ed83b7..0000000<br>--- a/src/southbridge/intel/i82801dx/ac97.c<br>+++ /dev/null<br>@@ -1,279 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <arch/io.h><br>-#include <delay.h><br>-#include "i82801dx.h"<br>-<br>-#define NAMBAR 0x10<br>-#define MASTER_VOL 0x02<br>-#define PAGING 0x24<br>-#define EXT_AUDIO 0x28<br>-#define FUNC_SEL 0x66<br>-#define INFO_IO 0x68<br>-#define CONNECTOR 0x6a<br>-#define VENDOR_ID1 0x7c<br>-#define VENDOR_ID2 0x7e<br>-#define SEC_VENDOR_ID1 0xfc<br>-#define SEC_VENDOR_ID2 0xfe<br>-<br>-#define NABMBAR 0x14<br>-#define GLOB_CNT 0x2c<br>-#define GLOB_STA 0x30<br>-#define CAS 0x34<br>-<br>-#define MMBAR 0x10<br>-#define EXT_MODEM_ID1 0x3c<br>-#define EXT_MODEM_ID2 0xbc<br>-<br>-#define MBAR 0x14<br>-#define SEC_CODEC 0x40<br>-<br>-<br>-/* FIXME. This table is probably mainboard specific */<br>-static u16 ac97_function[16*2][4] = {<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) },<br>- { (1 << 5), (2 << 11), (1 << 10), (3 << 13) }<br>-};<br>-<br>-static u16 nabmbar;<br>-static u16 nambar;<br>-<br>-static int ac97_semaphore(void)<br>-{<br>- int timeout;<br>- u8 reg8;<br>-<br>- timeout = 0xffff;<br>- do {<br>- reg8 = inb(nabmbar + CAS);<br>- timeout--;<br>- } while ((reg8 & 1) && timeout);<br>- if (! timeout) {<br>- printk(BIOS_DEBUG, "Timeout!\n");<br>- }<br>-<br>- return (!timeout);<br>-}<br>-<br>-static void init_cnr(void)<br>-{<br>- // TODO<br>-}<br>-<br>-static void program_sigid(struct device *dev, u32 id)<br>-{<br>- pci_write_config32(dev, 0x2c, id);<br>-}<br>-<br>-static void ac97_audio_init(struct device *dev)<br>-{<br>- u16 reg16;<br>- u32 reg32;<br>- int i;<br>-<br>- printk(BIOS_DEBUG, "Initializing AC'97 Audio.\n");<br>-<br>- /* top 16 bits are zero, so don't read them */<br>- nabmbar = pci_read_config16(dev, NABMBAR) & 0xfffe;<br>- nambar = pci_read_config16(dev, NAMBAR) & 0xfffe;<br>-<br>- reg16 = inw(nabmbar + GLOB_CNT);<br>- reg16 |= (1 << 1); /* Remove AC_RESET# */<br>- outw(reg16, nabmbar + GLOB_CNT);<br>-<br>- /* Wait 600ms. Ouch. */<br>- udelay(600 * 1000);<br>-<br>- init_cnr();<br>-<br>- /* Detect Primary AC'97 Codec */<br>- reg32 = inl(nabmbar + GLOB_STA);<br>- if ((reg32 & ((1 << 28) | (1 << 9) | (1 << 8))) == 0) {<br>- /* Primary Codec not found */<br>- printk(BIOS_DEBUG, "No primary codec. Disabling AC'97 Audio.\n");<br>- return;<br>- }<br>-<br>- ac97_semaphore();<br>-<br>- /* Detect if codec is programmable */<br>- outw(0x8000, nambar + MASTER_VOL);<br>- ac97_semaphore();<br>- if (inw(nambar + MASTER_VOL) != 0x8000) {<br>- printk(BIOS_DEBUG, "Codec not programmable. Disabling AC'97 Audio.\n");<br>- return;<br>- }<br>-<br>- /* Program Vendor IDs */<br>- reg32 = inw(nambar + VENDOR_ID1);<br>- reg32 <<= 16;<br>- reg32 |= (u16)inw(nambar + VENDOR_ID2);<br>-<br>- program_sigid(dev, reg32);<br>-<br>- /* Is Codec AC'97 2.3 compliant? */<br>- reg16 = inw(nambar + EXT_AUDIO);<br>- /* [11:10] = 10b -> AC'97 2.3 */<br>- if ((reg16 & 0x0c00) != 0x0800) {<br>- /* No 2.3 Codec. We're done */<br>- return;<br>- }<br>-<br>- /* Select Page 1 */<br>- reg16 = inw(nambar + PAGING);<br>- reg16 &= 0xfff0;<br>- reg16 |= 0x0001;<br>- outw(reg16, nambar + PAGING);<br>-<br>- for (i = 0x0a * 2; i > 0; i--) {<br>- outw(i, nambar + FUNC_SEL);<br>-<br>- /* Function could not be selected. Next one */<br>- if (inw(nambar + FUNC_SEL) != i)<br>- continue;<br>-<br>- reg16 = inw(nambar + INFO_IO);<br>-<br>- /* Function Information present? */<br>- if (!(reg16 & (1 << 0)))<br>- continue;<br>-<br>- /* Function Information valid? */<br>- if (!(reg16 & (1 << 4)))<br>- continue;<br>-<br>- /* Program Buffer Delay [9:5] */<br>- reg16 &= 0x03e0;<br>- reg16 |= ac97_function[i][0];<br>-<br>- /* Program Gain [15:11] */<br>- reg16 |= ac97_function[i][1];<br>-<br>- /* Program Inversion [10] */<br>- reg16 |= ac97_function[i][2];<br>-<br>- outw(reg16, nambar + INFO_IO);<br>-<br>- /* Program Connector / Jack Location */<br>- reg16 = inw(nambar + CONNECTOR);<br>- reg16 &= 0x1fff;<br>- reg16 |= ac97_function[i][3];<br>- outw(reg16, nambar + CONNECTOR);<br>- }<br>-}<br>-<br>-static void ac97_modem_init(struct device *dev)<br>-{<br>- u16 reg16;<br>- u32 reg32;<br>- u16 mmbar, mbar;<br>-<br>- mmbar = pci_read_config16(dev, MMBAR) & 0xfffe;<br>- mbar = pci_read_config16(dev, MBAR) & 0xfffe;<br>-<br>- reg16 = inw(mmbar + EXT_MODEM_ID1);<br>- if ((reg16 & 0xc000) != 0xc000 ) {<br>- if (reg16 & (1 << 0)) {<br>- reg32 = inw(mmbar + VENDOR_ID2);<br>- reg32 <<= 16;<br>- reg32 |= (u16)inw(mmbar + VENDOR_ID1);<br>- program_sigid(dev, reg32);<br>- return;<br>- }<br>- }<br>-<br>- /* Secondary codec? */<br>- reg16 = inw(mbar + SEC_CODEC);<br>- if ((reg16 & (1 << 9)) == 0)<br>- return;<br>-<br>- reg16 = inw(mmbar + EXT_MODEM_ID2);<br>- if ((reg16 & 0xc000) == 0x4000) {<br>- if (reg16 & (1 << 0)) {<br>- reg32 = inw(mmbar + SEC_VENDOR_ID2);<br>- reg32 <<= 16;<br>- reg32 |= (u16)inw(mmbar + SEC_VENDOR_ID1);<br>- program_sigid(dev, reg32);<br>- return;<br>- }<br>- }<br>-}<br>-<br>-static struct device_operations ac97_audio_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .enable = i82801dx_enable,<br>- .init = ac97_audio_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-static struct device_operations ac97_modem_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .enable = i82801dx_enable,<br>- .init = ac97_modem_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-/* 82801DB/DBL/DBM (ICH4/ICH4-L/ICH4-M) */<br>-static const struct pci_driver i82801db_ac97_audio __pci_driver = {<br>- .ops = &ac97_audio_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_AUDIO,<br>-};<br>-<br>-static const struct pci_driver i82801db_ac97_modem __pci_driver = {<br>- .ops = &ac97_modem_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82801DB_AC97_MODEM,<br>-};<br>diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c<br>deleted file mode 100644<br>index 8ae419d..0000000<br>--- a/src/southbridge/intel/i82801dx/bootblock.c<br>+++ /dev/null<br>@@ -1,21 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-<br>-static void bootblock_southbridge_init(void)<br>-{<br>- /* Set FWH IDs for 2 MB flash part. */<br>- if (CONFIG_ROM_SIZE == 0x200000)<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111);<br>-}<br>diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h<br>deleted file mode 100644<br>index f77413d..0000000<br>--- a/src/southbridge/intel/i82801dx/chip.h<br>+++ /dev/null<br>@@ -1,40 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2004 Eric Biederman<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef I82801DX_CHIP_H<br>-#define I82801DX_CHIP_H<br>-<br>-struct southbridge_intel_i82801dx_config {<br>- int enable_usb;<br>- int enable_native_ide;<br>- /**<br>- * Interrupt Routing configuration<br>- * If bit7 is 1, the interrupt is disabled.<br>- */<br>- uint8_t pirqa_routing;<br>- uint8_t pirqb_routing;<br>- uint8_t pirqc_routing;<br>- uint8_t pirqd_routing;<br>- uint8_t pirqe_routing;<br>- uint8_t pirqf_routing;<br>- uint8_t pirqg_routing;<br>- uint8_t pirqh_routing;<br>-<br>- uint8_t ide0_enable;<br>- uint8_t ide1_enable;<br>-};<br>-<br>-#endif /* I82801DX_CHIP_H */<br>diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c<br>deleted file mode 100644<br>index fabb58b..0000000<br>--- a/src/southbridge/intel/i82801dx/early_smbus.c<br>+++ /dev/null<br>@@ -1,44 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2004 Ronald G. Minnich<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <device/pci_def.h><br>-#include <console/console.h><br>-#include <southbridge/intel/common/smbus.h><br>-<br>-#include "i82801dx.h"<br>-<br>-void enable_smbus(void)<br>-{<br>- pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3);<br>-<br>- printk(BIOS_DEBUG, "SMBus controller enabled\n");<br>- /* set smbus iobase */<br>- pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);<br>- /* Set smbus enable */<br>- pci_write_config8(dev, 0x40, 0x01);<br>- /* Set smbus iospace enable */<br>- pci_write_config16(dev, 0x4, 0x01);<br>- /* Disable interrupt generation */<br>- outb(0, SMBUS_IO_BASE + SMBHSTCTL);<br>- /* clear any lingering errors, so the transaction will run */<br>- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);<br>-}<br>-<br>-int smbus_read_byte(unsigned int device, unsigned int address)<br>-{<br>- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);<br>-}<br>diff --git a/src/southbridge/intel/i82801dx/i82801dx.c b/src/southbridge/intel/i82801dx/i82801dx.c<br>deleted file mode 100644<br>index a4eb048..0000000<br>--- a/src/southbridge/intel/i82801dx/i82801dx.c<br>+++ /dev/null<br>@@ -1,82 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2004 Ron G. Minnich<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include "i82801dx.h"<br>-<br>-void i82801dx_enable(device_t dev)<br>-{<br>- unsigned int index = 0;<br>- uint8_t bHasDisableBit = 0;<br>- uint16_t cur_disable_mask, new_disable_mask;<br>-<br>-// all 82801dbm devices are in bus 0<br>- unsigned int devfn = PCI_DEVFN(0x1f, 0); // lpc<br>- device_t lpc_dev = dev_find_slot(0, devfn); // 0<br>- if (!lpc_dev)<br>- return;<br>-<br>- // Calculate disable bit position for specified device:function<br>- // NOTE: For ICH-4, only the following devices can be disabled:<br>- // D31: F0, F1, F3, F5, F6,<br>- // D29: F0, F1, F2, F7<br>-<br>- if (PCI_SLOT(dev->path.pci.devfn) == 31) {<br>- index = PCI_FUNC(dev->path.pci.devfn);<br>-<br>- switch (index) {<br>- case 0:<br>- case 1:<br>- case 3:<br>- case 5:<br>- case 6:<br>- bHasDisableBit = 1;<br>- break;<br>-<br>- default:<br>- break;<br>- };<br>-<br>- if (index == 0)<br>- index = 14; // D31:F0 bit is an exception<br>-<br>- } else if (PCI_SLOT(dev->path.pci.devfn) == 29) {<br>- index = 8 + PCI_FUNC(dev->path.pci.devfn);<br>-<br>- if ((PCI_FUNC(dev->path.pci.devfn) < 3)<br>- || (PCI_FUNC(dev->path.pci.devfn) == 7))<br>- bHasDisableBit = 1;<br>- }<br>-<br>- if (bHasDisableBit) {<br>- cur_disable_mask = pci_read_config16(lpc_dev, FUNC_DIS);<br>- new_disable_mask = cur_disable_mask & ~(1 << index); // enable it<br>- if (!dev->enabled) {<br>- new_disable_mask |= (1 << index); // disable it<br>- }<br>- if (new_disable_mask != cur_disable_mask) {<br>- pci_write_config16(lpc_dev, FUNC_DIS, new_disable_mask);<br>- }<br>- }<br>-}<br>-<br>-struct chip_operations southbridge_intel_i82801dx_ops = {<br>- CHIP_NAME("Intel ICH4/ICH4-M (82801Dx) Series Southbridge")<br>- .enable_dev = i82801dx_enable,<br>-};<br>diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h<br>deleted file mode 100644<br>index 14ca28f..0000000<br>--- a/src/southbridge/intel/i82801dx/i82801dx.h<br>+++ /dev/null<br>@@ -1,197 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2004 Ron G. Minnich<br>- * Copyright (C) 2004 Eric Biederman<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* the problem: we have 82801dbm support in fb1, and 82801er in fb2.<br>- * fb1 code is what we want, fb2 structure is needed however.<br>- * so we need to get fb1 code for 82801dbm into fb2 structure.<br>- */<br>-/* What I did: took the 80801er stuff from fb2, verify it against the<br>- * db stuff in fb1, and made sure it was right.<br>- */<br>-<br>-#ifndef I82801DX_H<br>-#define I82801DX_H<br>-<br>-#include <arch/acpi.h><br>-<br>-#if !defined(__ASSEMBLER__)<br>-#if !defined(__SIMPLE_DEVICE__)<br>-#include "chip.h"<br>-extern void i82801dx_enable(device_t dev);<br>-#else<br>-void enable_smbus(void);<br>-int smbus_read_byte(unsigned device, unsigned address);<br>-#endif<br>-#endif<br>-<br>-#define DEBUG_PERIODIC_SMIS 0<br>-<br>-#define MAINBOARD_POWER_OFF 0<br>-#define MAINBOARD_POWER_ON 1<br>-#define MAINBOARD_POWER_KEEP 2<br>-<br>-#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL<br>-#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON<br>-#endif<br>-<br>-/*<br>- * 000 = Non-combined. P0 is primary master. P1 is secondary master.<br>- * 001 = Non-combined. P0 is secondary master. P1 is primary master.<br>- * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary;<br>- * Primary IDE channel disabled.<br>- * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary.<br>- * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary<br>- * slave; Secondary IDE channel disabled.<br>- * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master.<br>- */<br>-/* PCI Configuration Space (D31:F1) */<br>-#define IDE_TIM_PRI 0x40 /* IDE timings, primary */<br>-#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */<br>-<br>-/* IDE_TIM bits */<br>-#define IDE_DECODE_ENABLE (1 << 15)<br>-<br>-<br>-<br>-#define PCI_DMA_CFG 0x90<br>-#define SERIRQ_CNTL 0x64<br>-#define GEN_CNTL 0xd0<br>-#define GEN_STS 0xd4<br>-#define RTC_CONF 0xd8<br>-#define GEN_PMCON_3 0xa4<br>-<br>-#define PCICMD 0x04<br>-#define PMBASE 0x40<br>-#define PMBASE_ADDR 0x0400<br>-#define DEFAULT_PMBASE PMBASE_ADDR<br>-#define ACPI_CNTL 0x44<br>-#define ACPI_EN (1 << 4)<br>-#define BIOS_CNTL 0x4E<br>-#define GPIO_BASE 0x58<br>-#define GPIO_CNTL 0x5C<br>-#define GPIOBASE_ADDR 0x0500<br>-#define PIRQA_ROUT 0x60<br>-#define PIRQB_ROUT 0x61<br>-#define PIRQC_ROUT 0x62<br>-#define PIRQD_ROUT 0x63<br>-#define PIRQE_ROUT 0x68<br>-#define PIRQF_ROUT 0x69<br>-#define PIRQG_ROUT 0x6A<br>-#define PIRQH_ROUT 0x6B<br>-#define COM_DEC 0xE0<br>-#define LPC_EN 0xE6<br>-#define FUNC_DIS 0xF2<br>-<br>-/* 1e f0 244e */<br>-<br>-#define CMD 0x04<br>-#define SBUS_NUM 0x19<br>-#define SUB_BUS_NUM 0x1A<br>-#define SMLT 0x1B<br>-#define IOBASE 0x1C<br>-#define IOLIM 0x1D<br>-#define MEMBASE 0x20<br>-#define MEMLIM 0x22<br>-#define CNF 0x50<br>-#define MTT 0x70<br>-#define PCI_MAST_STS 0x82<br>-<br>-#define RTC_FAILED (1 <<2)<br>-<br>-<br>-#define SMBUS_IO_BASE 0x1000<br>-<br>-#define PM1_STS 0x00<br>-#define WAK_STS (1 << 15)<br>-#define PCIEXPWAK_STS (1 << 14)<br>-#define PRBTNOR_STS (1 << 11)<br>-#define RTC_STS (1 << 10)<br>-#define PWRBTN_STS (1 << 8)<br>-#define GBL_STS (1 << 5)<br>-#define BM_STS (1 << 4)<br>-#define TMROF_STS (1 << 0)<br>-#define PM1_EN 0x02<br>-#define PCIEXPWAK_DIS (1 << 14)<br>-#define RTC_EN (1 << 10)<br>-#define PWRBTN_EN (1 << 8)<br>-#define GBL_EN (1 << 5)<br>-#define TMROF_EN (1 << 0)<br>-#define PM1_CNT 0x04<br>-#define GBL_RLS (1 << 2)<br>-#define BM_RLD (1 << 1)<br>-#define SCI_EN (1 << 0)<br>-#define PM1_TMR 0x08<br>-#define PROC_CNT 0x10<br>-#define LV2 0x14<br>-#define LV3 0x15<br>-#define LV4 0x16<br>-#define PM2_CNT 0x20 // mobile only<br>-#define GPE0_STS 0x28<br>-#define PME_B0_STS (1 << 13)<br>-#define USB3_STS (1 << 12)<br>-#define PME_STS (1 << 11)<br>-#define BATLOW_STS (1 << 10)<br>-#define GST_STS (1 << 9)<br>-#define RI_STS (1 << 8)<br>-#define SMB_WAK_STS (1 << 7)<br>-#define TCOSCI_STS (1 << 6)<br>-#define AC97_STS (1 << 5)<br>-#define USB2_STS (1 << 4)<br>-#define USB1_STS (1 << 3)<br>-#define SWGPE_STS (1 << 2)<br>-#define HOT_PLUG_STS (1 << 1)<br>-#define THRM_STS (1 << 0)<br>-#define GPE0_EN 0x2c<br>-#define PME_B0_EN (1 << 13)<br>-#define PME_EN (1 << 11)<br>-#define SMI_EN 0x30<br>-#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology<br>-#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic<br>-#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic<br>-#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS<br>-#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al)<br>-#define MCSMI_EN (1 << 11) // Trap microcontroller range access<br>-#define BIOS_RLS (1 << 7) // asserts SCI on bit set<br>-#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set<br>-#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI#<br>-#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI#<br>-#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic<br>-#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit<br>-#define EOS (1 << 1) // End of SMI (deassert SMI#)<br>-#define GBL_SMI_EN (1 << 0) // SMI# generation at all?<br>-#define SMI_STS 0x34<br>-#define ALT_GP_SMI_EN 0x38<br>-#define ALT_GP_SMI_STS 0x3a<br>-#define GPE_CNTL 0x42<br>-#define DEVACT_STS 0x44<br>-#define SS_CNT 0x50<br>-#define C3_RES 0x54<br>-<br>-#define TCOBASE 0x60 /* TCO Base Address Register */<br>-#define TCO1_CNT 0x08 /* TCO1 Control Register */<br>-<br>-#define GEN_PMCON_1 0xa0<br>-#define GEN_PMCON_2 0xa2<br>-#define GEN_PMCON_3 0xa4<br>-<br>-/* GEN_PMCON_3 bits */<br>-#define RTC_BATTERY_DEAD (1 << 2)<br>-#define RTC_POWER_FAILED (1 << 1)<br>-#define SLEEP_AFTER_POWER_FAIL (1 << 0)<br>-<br>-#endif /* I82801DX_H */<br>diff --git a/src/southbridge/intel/i82801dx/ide.c b/src/southbridge/intel/i82801dx/ide.c<br>deleted file mode 100644<br>index 51e2c89..0000000<br>--- a/src/southbridge/intel/i82801dx/ide.c<br>+++ /dev/null<br>@@ -1,78 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2004 Ronald G. Minnich<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include "i82801dx.h"<br>-<br>-typedef struct southbridge_intel_i82801dx_config config_t;<br>-<br>-static void ide_init(struct device *dev)<br>-{<br>- /* Get the chip configuration */<br>- config_t *config = dev->chip_info;<br>-<br>- /* Enable IDE devices so the Linux IDE driver will work. */<br>- uint16_t ideTimingConfig;<br>-<br>- ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);<br>- ideTimingConfig &= ~IDE_DECODE_ENABLE;<br>- if (!config || config->ide0_enable) {<br>- /* Enable primary IDE interface. */<br>- ideTimingConfig |= IDE_DECODE_ENABLE;<br>- printk(BIOS_DEBUG, "IDE0: Primary IDE interface is enabled\n");<br>- } else {<br>- printk(BIOS_INFO, "IDE0: Primary IDE interface is disabled\n");<br>- }<br>- pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);<br>-<br>- ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);<br>- ideTimingConfig &= ~IDE_DECODE_ENABLE;<br>- if (!config || config->ide1_enable) {<br>- /* Enable secondary IDE interface. */<br>- ideTimingConfig |= IDE_DECODE_ENABLE;<br>- printk(BIOS_DEBUG, "IDE1: Secondary IDE interface is enabled\n");<br>- } else {<br>- printk(BIOS_INFO, "IDE1: Secondary IDE interface is disabled\n");<br>- }<br>- pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);<br>-}<br>-<br>-static struct device_operations ide_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = ide_init,<br>- .scan_bus = 0,<br>- .enable = i82801dx_enable,<br>-};<br>-<br>-/* 82801DB */<br>-static const struct pci_driver i82801db_ide __pci_driver = {<br>- .ops = &ide_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x24cb,<br>-};<br>-<br>-/* 82801DBM */<br>-static const struct pci_driver i82801dbm_ide __pci_driver = {<br>- .ops = &ide_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = 0x24ca,<br>-};<br>diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c<br>deleted file mode 100644<br>index 3502c8b..0000000<br>--- a/src/southbridge/intel/i82801dx/lpc.c<br>+++ /dev/null<br>@@ -1,351 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2003 Linux Networx<br>- * Copyright (C) 2004 SuSE Linux AG<br>- * Copyright (C) 2004 Tyan Computer<br>- * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <pc80/mc146818rtc.h><br>-#include <pc80/isa-dma.h><br>-#include <arch/io.h><br>-#include <arch/ioapic.h><br>-#include "i82801dx.h"<br>-<br>-#define NMI_OFF 0<br>-<br>-typedef struct southbridge_intel_i82801dx_config config_t;<br>-<br>-/**<br>- * Enable ACPI I/O range.<br>- *<br>- * @param dev PCI device with ACPI and PM BAR's<br>- */<br>-static void i82801dx_enable_acpi(struct device *dev)<br>-{<br>- /* Set ACPI base address (I/O space). */<br>- pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));<br>-<br>- /* Enable ACPI I/O range decode and ACPI power management. */<br>- pci_write_config8(dev, ACPI_CNTL, ACPI_EN);<br>-}<br>-<br>-/**<br>- * Set miscellanous static southbridge features.<br>- *<br>- * @param dev PCI device with I/O APIC control registers<br>- */<br>-static void i82801dx_enable_ioapic(struct device *dev)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = pci_read_config32(dev, GEN_CNTL);<br>- reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */<br>- reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */<br>- reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */<br>- reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */<br>- pci_write_config32(dev, GEN_CNTL, reg32);<br>- printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32);<br>-<br>- set_ioapic_id(VIO_APIC_VADDR, 0x02);<br>-<br>- /*<br>- * Select Boot Configuration register (0x03) and<br>- * use Processor System Bus (0x01) to deliver interrupts.<br>- */<br>- io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);<br>-}<br>-<br>-static void i82801dx_enable_serial_irqs(struct device *dev)<br>-{<br>- /* Set packet length and toggle silent mode bit. */<br>- pci_write_config8(dev, SERIRQ_CNTL,<br>- (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));<br>- pci_write_config8(dev, SERIRQ_CNTL,<br>- (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));<br>-}<br>-<br>-static void i82801dx_pirq_init(device_t dev)<br>-{<br>- /* Get the chip configuration */<br>- config_t *config = dev->chip_info;<br>-<br>- pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);<br>- pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);<br>- pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);<br>- pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);<br>- pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);<br>- pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);<br>- pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);<br>- pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);<br>-}<br>-<br>-static void i82801dx_power_options(device_t dev)<br>-{<br>- u8 reg8;<br>- u16 reg16, pmbase;<br>- u32 reg32;<br>- const char *state;<br>-<br>- int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;<br>- int nmi_option;<br>-<br>- /* Which state do we want to goto after g3 (power restored)?<br>- * 0 == S0 Full On<br>- * 1 == S5 Soft Off<br>- *<br>- * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.<br>- */<br>- pwr_on = MAINBOARD_POWER_ON;<br>- get_option(&pwr_on, "power_on_after_fail");<br>-<br>- reg8 = pci_read_config8(dev, GEN_PMCON_3);<br>- reg8 &= 0xfe;<br>- switch (pwr_on) {<br>- case MAINBOARD_POWER_OFF:<br>- reg8 |= 1;<br>- state = "off";<br>- break;<br>- case MAINBOARD_POWER_ON:<br>- reg8 &= ~1;<br>- state = "on";<br>- break;<br>- case MAINBOARD_POWER_KEEP:<br>- reg8 &= ~1;<br>- state = "state keep";<br>- break;<br>- default:<br>- state = "undefined";<br>- }<br>-<br>- reg8 &= ~(1 << 3); /* minimum asssertion is 1 to 2 RTCCLK */<br>-<br>- pci_write_config8(dev, GEN_PMCON_3, reg8);<br>- printk(BIOS_INFO, "Set power %s after power failure.\n", state);<br>-<br>- /* Set up NMI on errors. */<br>- reg8 = inb(0x61);<br>- reg8 &= 0x0f; /* Higher Nibble must be 0 */<br>- reg8 &= ~(1 << 3); /* IOCHK# NMI Enable */<br>- // reg8 &= ~(1 << 2); /* PCI SERR# Enable */<br>- reg8 |= (1 << 2); /* PCI SERR# Disable for now */<br>- outb(reg8, 0x61);<br>-<br>- reg8 = inb(0x70);<br>- nmi_option = NMI_OFF;<br>- get_option(&nmi_option, "nmi");<br>- if (nmi_option) {<br>- printk(BIOS_INFO, "NMI sources enabled.\n");<br>- reg8 &= ~(1 << 7); /* Set NMI. */<br>- } else {<br>- printk(BIOS_INFO, "NMI sources disabled.\n");<br>- reg8 |= ( 1 << 7); /* Disable NMI. */<br>- }<br>- outb(reg8, 0x70);<br>-<br>- /* Set SMI# rate down and enable CPU_SLP# */<br>- reg16 = pci_read_config16(dev, GEN_PMCON_1);<br>- reg16 &= ~(3 << 0); // SMI# rate 1 minute<br>- reg16 |= (1 << 5); // CPUSLP_EN Desktop only<br>- pci_write_config16(dev, GEN_PMCON_1, reg16);<br>-<br>- pmbase = pci_read_config16(dev, 0x40) & 0xfffe;<br>-<br>- /* Set up power management block and determine sleep mode */<br>- reg32 = inl(pmbase + 0x04); // PM1_CNT<br>-<br>- reg32 &= ~(7 << 10); // SLP_TYP<br>- reg32 |= (1 << 0); // SCI_EN<br>- outl(reg32, pmbase + 0x04);<br>-}<br>-<br>-static void gpio_init(device_t dev)<br>-{<br>- /* This should be done in romstage.c already */<br>- pci_write_config32(dev, GPIO_BASE, (GPIOBASE_ADDR | 1));<br>- pci_write_config8(dev, GPIO_CNTL, 0x10);<br>-}<br>-<br>-static void i82801dx_rtc_init(struct device *dev)<br>-{<br>- u8 reg8;<br>- u32 reg32;<br>- int rtc_failed;<br>-<br>- reg8 = pci_read_config8(dev, GEN_PMCON_3);<br>- rtc_failed = reg8 & RTC_BATTERY_DEAD;<br>- if (rtc_failed) {<br>- reg8 &= ~(1 << 1); /* Preserve the power fail state. */<br>- pci_write_config8(dev, GEN_PMCON_3, reg8);<br>- }<br>- reg32 = pci_read_config32(dev, GEN_STS);<br>- rtc_failed |= reg32 & (1 << 2);<br>- cmos_init(rtc_failed);<br>-<br>- /* Enable access to the upper 128 byte bank of CMOS RAM. */<br>- pci_write_config8(dev, RTC_CONF, 0x04);<br>-}<br>-<br>-static void i82801dx_lpc_route_dma(struct device *dev, u8 mask)<br>-{<br>- u16 reg16;<br>- int i;<br>-<br>- reg16 = pci_read_config16(dev, PCI_DMA_CFG);<br>- reg16 &= 0x300;<br>- for (i = 0; i < 8; i++) {<br>- if (i == 4)<br>- continue;<br>- reg16 |= ((mask & (1 << i)) ? 3 : 1) << (i * 2);<br>- }<br>- pci_write_config16(dev, PCI_DMA_CFG, reg16);<br>-}<br>-<br>-static void i82801dx_lpc_decode_en(device_t dev)<br>-{<br>- /* Decode 0x3F8-0x3FF (COM1) for COMA port, 0x2F8-0x2FF (COM2) for COMB.<br>- * LPT decode defaults to 0x378-0x37F and 0x778-0x77F.<br>- * Floppy decode defaults to 0x3F0-0x3F5, 0x3F7.<br>- * We also need to set the value for LPC I/F Enables Register.<br>- */<br>- pci_write_config8(dev, COM_DEC, 0x10);<br>- pci_write_config16(dev, LPC_EN, 0x300F);<br>-}<br>-<br>-/* ICH4 does not mention HPET in the docs, but<br>- * all ICH3 and ICH4 do have HPETs built in.<br>- */<br>-static void enable_hpet(struct device *dev)<br>-{<br>- u32 reg32, hpet, val;<br>-<br>- /* Set HPET base address and enable it */<br>- printk(BIOS_DEBUG, "Enabling HPET at 0x%x\n", CONFIG_HPET_ADDRESS);<br>- reg32 = pci_read_config32(dev, GEN_CNTL);<br>- /*<br>- * Bit 17 is HPET enable bit.<br>- * Bit 16:15 control the HPET base address.<br>- */<br>- reg32 &= ~(3 << 15); /* Clear it */<br>-<br>- hpet = CONFIG_HPET_ADDRESS >> 12;<br>- hpet &= 0x3;<br>-<br>- reg32 |= (hpet << 15);<br>- reg32 |= (1 << 17); /* Enable HPET. */<br>- pci_write_config32(dev, GEN_CNTL, reg32);<br>-<br>- /* Check to see whether it took */<br>- reg32 = pci_read_config32(dev, GEN_CNTL);<br>- val = reg32 >> 15;<br>- val &= 0x7;<br>-<br>- if ((val & 0x4) && (hpet == (val & 0x3))) {<br>- printk(BIOS_INFO, "HPET enabled at 0x%x\n", CONFIG_HPET_ADDRESS);<br>- } else {<br>- printk(BIOS_WARNING, "HPET was not enabled correctly\n");<br>- reg32 &= ~(1 << 17); /* Clear Enable */<br>- pci_write_config32(dev, GEN_CNTL, reg32);<br>- }<br>-}<br>-<br>-static void lpc_init(struct device *dev)<br>-{<br>- /* Set the value for PCI command register. */<br>- pci_write_config16(dev, PCI_COMMAND, 0x000f);<br>-<br>- i82801dx_enable_acpi(dev);<br>- /* IO APIC initialization. */<br>- i82801dx_enable_ioapic(dev);<br>-<br>- i82801dx_enable_serial_irqs(dev);<br>-<br>- /* Setup the PIRQ. */<br>- i82801dx_pirq_init(dev);<br>-<br>- /* Setup power options. */<br>- i82801dx_power_options(dev);<br>-<br>- /* Set the state of the GPIO lines. */<br>- gpio_init(dev);<br>-<br>- /* Initialize the real time clock. */<br>- i82801dx_rtc_init(dev);<br>-<br>- /* Route DMA. */<br>- i82801dx_lpc_route_dma(dev, 0xff);<br>-<br>- /* Initialize ISA DMA. */<br>- isa_dma_init();<br>-<br>- /* Setup decode ports and LPC I/F enables. */<br>- i82801dx_lpc_decode_en(dev);<br>-<br>- /* Initialize the High Precision Event Timers */<br>- enable_hpet(dev);<br>-}<br>-<br>-static void i82801dx_lpc_read_resources(device_t dev)<br>-{<br>- struct resource *res;<br>-<br>- /* Get the normal PCI resources of this device. */<br>- pci_dev_read_resources(dev);<br>-<br>- /* Add an extra subtractive resource for both memory and I/O. */<br>- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));<br>- res->base = 0;<br>- res->size = 0x1000;<br>- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |<br>- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-<br>- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));<br>- res->base = 0xff800000;<br>- res->size = 0x00800000; /* 8 MB for flash */<br>- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |<br>- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-<br>- res = new_resource(dev, 3); /* IOAPIC */<br>- res->base = IO_APIC_ADDR;<br>- res->size = 0x00001000;<br>- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;<br>-}<br>-<br>-static struct device_operations lpc_ops = {<br>- .read_resources = i82801dx_lpc_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = lpc_init,<br>- .scan_bus = scan_lpc_bus,<br>- .enable = i82801dx_enable,<br>-};<br>-<br>-/* 82801DB/DBL */<br>-static const struct pci_driver lpc_driver_db __pci_driver = {<br>- .ops = &lpc_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82801DB_LPC,<br>-};<br>-<br>-/* 82801DBM */<br>-static const struct pci_driver lpc_driver_dbm __pci_driver = {<br>- .ops = &lpc_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82801DBM_LPC,<br>-};<br>diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h<br>deleted file mode 100644<br>index bdc6b45..0000000<br>--- a/src/southbridge/intel/i82801dx/nvs.h<br>+++ /dev/null<br>@@ -1,135 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <compiler.h><br>-<br>-typedef struct {<br>- /* Miscellaneous */<br>- u16 osys; /* 0x00 - Operating System */<br>- u8 smif; /* 0x02 - SMI function call ("TRAP") */<br>- u8 prm0; /* 0x03 - SMI function call parameter */<br>- u8 prm1; /* 0x04 - SMI function call parameter */<br>- u8 scif; /* 0x05 - SCI function call (via _L00) */<br>- u8 prm2; /* 0x06 - SCI function call parameter */<br>- u8 prm3; /* 0x07 - SCI function call parameter */<br>- u8 lckf; /* 0x08 - Global Lock function for EC */<br>- u8 prm4; /* 0x09 - Lock function parameter */<br>- u8 prm5; /* 0x0a - Lock function parameter */<br>- u32 p80d; /* 0x0b - Debug port (IO 0x80) value */<br>- u8 lids; /* 0x0f - LID state (open = 1) */<br>- u8 pwrs; /* 0x10 - Power state (AC = 1) */<br>- u8 dbgs; /* 0x11 - Debug state */<br>- u8 linx; /* 0x12 - Linux OS */<br>- u8 dckn; /* 0x13 - PCIe docking state */<br>- /* Thermal policy */<br>- u8 actt; /* 0x14 - active trip point */<br>- u8 psvt; /* 0x15 - passive trip point */<br>- u8 tc1v; /* 0x16 - passive trip point TC1 */<br>- u8 tc2v; /* 0x17 - passive trip point TC2 */<br>- u8 tspv; /* 0x18 - passive trip point TSP */<br>- u8 crtt; /* 0x19 - critical trip point */<br>- u8 dtse; /* 0x1a - Digital Thermal Sensor enable */<br>- u8 dts1; /* 0x1b - DT sensor 1 */<br>- u8 dts2; /* 0x1c - DT sensor 2 */<br>- u8 rsvd2;<br>- /* Battery Support */<br>- u8 bnum; /* 0x1e - number of batteries */<br>- u8 b0sc, b1sc, b2sc; /* 0x1f-0x21 - stored capacity */<br>- u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */<br>- u8 rsvd3[3];<br>- /* Processor Identification */<br>- u8 apic; /* 0x28 - APIC enabled */<br>- u8 mpen; /* 0x29 - MP capable/enabled */<br>- u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */<br>- u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */<br>- u8 ppcm; /* 0x2c - Max. PPC state */<br>- u8 rsvd4[5];<br>- /* Super I/O & CMOS config */<br>- u8 natp; /* 0x32 - SIO type */<br>- u8 cmap; /* 0x33 - */<br>- u8 cmbp; /* 0x34 - */<br>- u8 lptp; /* 0x35 - LPT port */<br>- u8 fdcp; /* 0x36 - Floppy Disk Controller */<br>- u8 rfdv; /* 0x37 - */<br>- u8 hotk; /* 0x38 - Hot Key */<br>- u8 rtcf;<br>- u8 util;<br>- u8 acin;<br>- /* Integrated Graphics Device */<br>- u8 igds; /* 0x3c - IGD state */<br>- u8 tlst; /* 0x3d - Display Toggle List Pointer */<br>- u8 cadl; /* 0x3e - currently attached devices */<br>- u8 padl; /* 0x3f - previously attached devices */<br>- u16 cste; /* 0x40 - current display state */<br>- u16 nste; /* 0x42 - next display state */<br>- u16 sste; /* 0x44 - set display state */<br>- u8 ndid; /* 0x46 - number of device ids */<br>- u32 did[5]; /* 0x47 - 5b device id 1..5 */<br>- u8 rsvd5[0x9];<br>- /* Backlight Control */<br>- u8 blcs; /* 0x64 - Backlight Control possible */<br>- u8 brtl;<br>- u8 odds;<br>- u8 rsvd6[0x7];<br>- /* Ambient Light Sensors*/<br>- u8 alse; /* 0x6e - ALS enable */<br>- u8 alaf;<br>- u8 llow;<br>- u8 lhih;<br>- u8 rsvd7[0x6];<br>- /* EMA */<br>- u8 emae; /* 0x78 - EMA enable */<br>- u16 emap;<br>- u16 emal;<br>- u8 rsvd8[0x5];<br>- /* MEF */<br>- u8 mefe; /* 0x82 - MEF enable */<br>- u8 rsvd9[0x9];<br>- /* TPM support */<br>- u8 tpmp; /* 0x8c - TPM */<br>- u8 tpme;<br>- u8 rsvd10[8];<br>- /* SATA */<br>- u8 gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */<br>- u8 gtf1[7];<br>- u8 gtf2[7];<br>- u8 idem;<br>- u8 idet;<br>- u8 rsvd11[7];<br>- /* IGD OpRegion (not implemented yet) */<br>- u32 aslb; /* 0xb4 - IGD OpRegion Base Address */<br>- u8 ibtt;<br>- u8 ipat;<br>- u8 itvf;<br>- u8 itvm;<br>- u8 ipsc;<br>- u8 iblc;<br>- u8 ibia;<br>- u8 issc;<br>- u8 i409;<br>- u8 i509;<br>- u8 i609;<br>- u8 i709;<br>- u8 idmm;<br>- u8 idms;<br>- u8 if1e;<br>- u8 hvco;<br>- u32 nxd[8];<br>- u8 rsvd12[8];<br>- /* Mainboard specific */<br>- u8 dock; /* 0xf0 - Docking Status */<br>- u8 bten;<br>- u8 rsvd13[14];<br>-} __packed global_nvs_t;<br>diff --git a/src/southbridge/intel/i82801dx/pci.c b/src/southbridge/intel/i82801dx/pci.c<br>deleted file mode 100644<br>index c062c85..0000000<br>--- a/src/southbridge/intel/i82801dx/pci.c<br>+++ /dev/null<br>@@ -1,54 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2004 Ronald G. Minnich<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include "i82801dx.h"<br>-<br>-static void pci_init(struct device *dev)<br>-{<br>- /* Enable pci error detecting */<br>- uint32_t dword;<br>- /* System error enable */<br>- dword = pci_read_config32(dev, 0x04);<br>- dword |= (1 << 8); /* SERR# Enable */<br>- dword |= (1 << 6); /* Parity Error Response */<br>- pci_write_config32(dev, 0x04, dword);<br>-}<br>-<br>-static struct device_operations pci_ops = {<br>- .read_resources = pci_bus_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_bus_enable_resources,<br>- .init = pci_init,<br>- .scan_bus = pci_scan_bridge,<br>-};<br>-<br>-/* 82801DB */<br>-static const struct pci_driver pci_driver_db __pci_driver = {<br>- .ops = &pci_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82801DB_PCI,<br>-};<br>-<br>-/* 82801DBM/DBL */<br>-static const struct pci_driver pci_driver_dbm __pci_driver = {<br>- .ops = &pci_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82801DBM_PCI,<br>-};<br>diff --git a/src/southbridge/intel/i82801dx/reset.c b/src/southbridge/intel/i82801dx/reset.c<br>deleted file mode 100644<br>index 1839ad6..0000000<br>--- a/src/southbridge/intel/i82801dx/reset.c<br>+++ /dev/null<br>@@ -1,23 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2004 Ronald G. Minnich<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <reset.h><br>-<br>-void do_hard_reset(void)<br>-{<br>- /* Try rebooting through port 0xcf9 */<br>- outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);<br>-}<br>diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c<br>deleted file mode 100644<br>index 945fcf2..0000000<br>--- a/src/southbridge/intel/i82801dx/smi.c<br>+++ /dev/null<br>@@ -1,371 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-<br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <console/console.h><br>-#include <arch/acpi.h><br>-#include <arch/io.h><br>-#include <cpu/cpu.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/x86/smm.h><br>-#include <string.h><br>-#include "i82801dx.h"<br>-<br>-/* I945 */<br>-#define SMRAM 0x90<br>-#define D_OPEN (1 << 6)<br>-#define D_CLS (1 << 5)<br>-#define D_LCK (1 << 4)<br>-#define G_SMRAME (1 << 3)<br>-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))<br>-<br>-/* While we read PMBASE dynamically in case it changed, let's<br>- * initialize it with a sane value<br>- */<br>-static u16 pmbase = PMBASE_ADDR;<br>-<br>-/**<br>- * @brief read and clear PM1_STS<br>- * @return PM1_STS register<br>- */<br>-static u16 reset_pm1_status(void)<br>-{<br>- u16 reg16;<br>-<br>- reg16 = inw(pmbase + PM1_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outw(reg16, pmbase + PM1_STS);<br>-<br>- return reg16;<br>-}<br>-<br>-static void dump_pm1_status(u16 pm1_sts)<br>-{<br>- printk(BIOS_DEBUG, "PM1_STS: ");<br>- if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");<br>- if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");<br>- if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");<br>- if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");<br>- if (pm1_sts & (1 << 8)) printk(BIOS_DEBUG, "PWRBTN ");<br>- if (pm1_sts & (1 << 5)) printk(BIOS_DEBUG, "GBL ");<br>- if (pm1_sts & (1 << 4)) printk(BIOS_DEBUG, "BM ");<br>- if (pm1_sts & (1 << 0)) printk(BIOS_DEBUG, "TMROF ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-/**<br>- * @brief read and clear SMI_STS<br>- * @return SMI_STS register<br>- */<br>-static u32 reset_smi_status(void)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = inl(pmbase + SMI_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32, pmbase + SMI_STS);<br>-<br>- return reg32;<br>-}<br>-<br>-static void dump_smi_status(u32 smi_sts)<br>-{<br>- printk(BIOS_DEBUG, "SMI_STS: ");<br>- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");<br>- if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");<br>- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");<br>- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");<br>- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");<br>- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");<br>- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");<br>- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");<br>- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");<br>- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");<br>- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");<br>- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");<br>- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");<br>- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");<br>- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");<br>- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");<br>- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");<br>- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");<br>- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");<br>- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-<br>-/**<br>- * @brief read and clear GPE0_STS<br>- * @return GPE0_STS register<br>- */<br>-static u32 reset_gpe0_status(void)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = inl(pmbase + GPE0_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32, pmbase + GPE0_STS);<br>-<br>- return reg32;<br>-}<br>-<br>-static void dump_gpe0_status(u32 gpe0_sts)<br>-{<br>- int i;<br>- printk(BIOS_DEBUG, "GPE0_STS: ");<br>- for (i=31; i>= 16; i--) {<br>- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));<br>- }<br>- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");<br>- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");<br>- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");<br>- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");<br>- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");<br>- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");<br>- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");<br>- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");<br>- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");<br>- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");<br>- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");<br>- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");<br>- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");<br>- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-<br>-/**<br>- * @brief read and clear ALT_GP_SMI_STS<br>- * @return ALT_GP_SMI_STS register<br>- */<br>-static u16 reset_alt_gp_smi_status(void)<br>-{<br>- u16 reg16;<br>-<br>- reg16 = inl(pmbase + ALT_GP_SMI_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg16, pmbase + ALT_GP_SMI_STS);<br>-<br>- return reg16;<br>-}<br>-<br>-static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)<br>-{<br>- int i;<br>- printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");<br>- for (i=15; i>= 0; i--) {<br>- if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-<br>-<br>-/**<br>- * @brief read and clear TCOx_STS<br>- * @return TCOx_STS registers<br>- */<br>-static u32 reset_tco_status(void)<br>-{<br>- u32 tcobase = pmbase + 0x60;<br>- u32 reg32;<br>-<br>- reg32 = inl(tcobase + 0x04);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS<br>- if (reg32 & (1 << 18))<br>- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS<br>-<br>- return reg32;<br>-}<br>-<br>-<br>-static void dump_tco_status(u32 tco_sts)<br>-{<br>- printk(BIOS_DEBUG, "TCO_STS: ");<br>- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");<br>- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");<br>- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");<br>- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");<br>- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");<br>- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");<br>- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");<br>- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");<br>- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");<br>- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");<br>- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");<br>- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");<br>- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-<br>-<br>-/**<br>- * @brief Set the EOS bit<br>- */<br>-static void smi_set_eos(void)<br>-{<br>- u8 reg8;<br>-<br>- reg8 = inb(pmbase + SMI_EN);<br>- reg8 |= EOS;<br>- outb(reg8, pmbase + SMI_EN);<br>-}<br>-<br>-extern uint8_t smm_relocation_start, smm_relocation_end;<br>-static void *default_smm_area = NULL;<br>-<br>-static void smm_relocate(void)<br>-{<br>- u32 smi_en;<br>- u16 pm1_en;<br>-<br>- printk(BIOS_DEBUG, "Initializing SMM handler...");<br>-<br>- pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), 0x40) & 0xfffc;<br>- printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);<br>-<br>- smi_en = inl(pmbase + SMI_EN);<br>- if (smi_en & APMC_EN) {<br>- printk(BIOS_INFO, "SMI# handler already enabled?\n");<br>- return;<br>- }<br>-<br>- default_smm_area = backup_default_smm_area();<br>-<br>- /* copy the SMM relocation code */<br>- memcpy((void *)0x38000, &smm_relocation_start,<br>- &smm_relocation_end - &smm_relocation_start);<br>- wbinvd();<br>-<br>- printk(BIOS_DEBUG, "\n");<br>- dump_smi_status(reset_smi_status());<br>- dump_pm1_status(reset_pm1_status());<br>- dump_gpe0_status(reset_gpe0_status());<br>- dump_alt_gp_smi_status(reset_alt_gp_smi_status());<br>- dump_tco_status(reset_tco_status());<br>-<br>- /* Enable SMI generation:<br>- * - on TCO events<br>- * - on APMC writes (io 0xb2)<br>- * - on writes to SLP_EN (sleep states)<br>- * - on writes to GBL_RLS (bios commands)<br>- * No SMIs:<br>- * - on microcontroller writes (io 0x62/0x66)<br>- */<br>-<br>- smi_en = 0; /* reset SMI enables */<br>-<br>-#if 0<br>- smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;<br>-#endif<br>- smi_en |= TCO_EN;<br>- smi_en |= APMC_EN;<br>-#if DEBUG_PERIODIC_SMIS<br>- /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using<br>- * periodic SMIs.<br>- */<br>- smi_en |= PERIODIC_EN;<br>-#endif<br>- smi_en |= SLP_SMI_EN;<br>- smi_en |= BIOS_EN;<br>-<br>- /* The following need to be on for SMIs to happen */<br>- smi_en |= EOS | GBL_SMI_EN;<br>-<br>- outl(smi_en, pmbase + SMI_EN);<br>-<br>- pm1_en = 0;<br>- pm1_en |= PWRBTN_EN;<br>- pm1_en |= GBL_EN;<br>- outw(pm1_en, pmbase + PM1_EN);<br>-<br>- /**<br>- * There are several methods of raising a controlled SMI# via<br>- * software, among them:<br>- * - Writes to io 0xb2 (APMC)<br>- * - Writes to the Local Apic ICR with Delivery mode SMI.<br>- *<br>- * Using the local apic is a bit more tricky. According to<br>- * AMD Family 11 Processor BKDG no destination shorthand must be<br>- * used.<br>- * The whole SMM initialization is quite a bit hardware specific, so<br>- * I'm not too worried about the better of the methods at the moment<br>- */<br>-<br>- /* raise an SMI interrupt */<br>- printk(BIOS_SPEW, " ... raise SMI#\n");<br>- outb(0x00, 0xb2);<br>-}<br>-<br>-static void smm_install(void)<br>-{<br>- /* enable the SMM memory window */<br>- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,<br>- D_OPEN | G_SMRAME | C_BASE_SEG);<br>-<br>- /* copy the real SMM handler */<br>- memcpy((void *)0xa0000, _binary_smm_start,<br>- _binary_smm_end - _binary_smm_start);<br>- wbinvd();<br>-<br>- /* close the SMM memory window and enable normal SMM */<br>- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,<br>- G_SMRAME | C_BASE_SEG);<br>-}<br>-<br>-void smm_init(void)<br>-{<br>- /* Put SMM code to 0xa0000 */<br>- smm_install();<br>-<br>- /* Put relocation code to 0x38000 and relocate SMBASE */<br>- smm_relocate();<br>-<br>- /* We're done. Make sure SMIs can happen! */<br>- smi_set_eos();<br>-}<br>-<br>-void smm_init_completion(void)<br>-{<br>- restore_default_smm_area(default_smm_area);<br>-}<br>-<br>-void smm_lock(void)<br>-{<br>- /* LOCK the SMM memory window and enable normal SMM.<br>- * After running this function, only a full reset can<br>- * make the SMM registers writable again.<br>- */<br>- printk(BIOS_DEBUG, "Locking SMM.\n");<br>- pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,<br>- D_LCK | G_SMRAME | C_BASE_SEG);<br>-}<br>-<br>-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)<br>-{<br>- /* The GDT or coreboot table is going to live here. But a long time<br>- * after we relocated the GNVS, so this is not troublesome.<br>- */<br>- *(u32 *)0x500 = (u32)gnvs;<br>- *(u32 *)0x504 = (u32)tcg;<br>- *(u32 *)0x508 = (u32)smi1;<br>- outb(0xea, 0xb2);<br>-}<br>diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c<br>deleted file mode 100644<br>index 3a08daa..0000000<br>--- a/src/southbridge/intel/i82801dx/smihandler.c<br>+++ /dev/null<br>@@ -1,643 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <types.h><br>-#include <arch/io.h><br>-#include <console/console.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/x86/smm.h><br>-#include <device/pci_def.h><br>-#include "i82801dx.h"<br>-<br>-#define DEBUG_SMI<br>-<br>-/* I830M */<br>-#define SMRAM 0x90<br>-#define D_OPEN (1 << 6)<br>-#define D_CLS (1 << 5)<br>-#define D_LCK (1 << 4)<br>-#define G_SMRANE (1 << 3)<br>-#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))<br>-<br>-#include "nvs.h"<br>-<br>-/* While we read PMBASE dynamically in case it changed, let's<br>- * initialize it with a sane value<br>- */<br>-u16 pmbase = PMBASE_ADDR;<br>-u8 smm_initialized = 0;<br>-<br>-unsigned char *mbi = NULL;<br>-u32 mbi_len;<br>-u8 mbi_initialized = 0;<br>-<br>-/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located<br>- * by coreboot.<br>- */<br>-global_nvs_t *gnvs = (global_nvs_t *)0x0;<br>-void *tcg = (void *)0x0;<br>-void *smi1 = (void *)0x0;<br>-<br>-/**<br>- * @brief read and clear PM1_STS<br>- * @return PM1_STS register<br>- */<br>-static u16 reset_pm1_status(void)<br>-{<br>- u16 reg16;<br>-<br>- reg16 = inw(pmbase + PM1_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outw(reg16, pmbase + PM1_STS);<br>-<br>- return reg16;<br>-}<br>-<br>-static void dump_pm1_status(u16 pm1_sts)<br>-{<br>- printk(BIOS_SPEW, "PM1_STS: ");<br>- if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");<br>- if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");<br>- if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");<br>- if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");<br>- if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");<br>- if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");<br>- if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");<br>- if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");<br>- printk(BIOS_SPEW, "\n");<br>- int reg16 = inw(pmbase + PM1_EN);<br>- printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);<br>-}<br>-<br>-/**<br>- * @brief read and clear SMI_STS<br>- * @return SMI_STS register<br>- */<br>-static u32 reset_smi_status(void)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = inl(pmbase + SMI_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32, pmbase + SMI_STS);<br>-<br>- return reg32;<br>-}<br>-<br>-static void dump_smi_status(u32 smi_sts)<br>-{<br>- printk(BIOS_DEBUG, "SMI_STS: ");<br>- if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");<br>- if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");<br>- if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");<br>- if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");<br>- if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");<br>- if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");<br>- if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");<br>- if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");<br>- if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");<br>- if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");<br>- if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");<br>- if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");<br>- if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");<br>- if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");<br>- if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");<br>- if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");<br>- if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");<br>- if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");<br>- if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");<br>- if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-<br>-/**<br>- * @brief read and clear GPE0_STS<br>- * @return GPE0_STS register<br>- */<br>-static u32 reset_gpe0_status(void)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = inl(pmbase + GPE0_STS);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32, pmbase + GPE0_STS);<br>-<br>- return reg32;<br>-}<br>-<br>-static void dump_gpe0_status(u32 gpe0_sts)<br>-{<br>- int i;<br>- printk(BIOS_DEBUG, "GPE0_STS: ");<br>- for (i=31; i>= 16; i--) {<br>- if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));<br>- }<br>- if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");<br>- if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");<br>- if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");<br>- if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");<br>- if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");<br>- if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");<br>- if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");<br>- if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");<br>- if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");<br>- if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "AC97 ");<br>- if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");<br>- if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");<br>- if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "HOT_PLUG ");<br>- if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-<br>-/**<br>- * @brief read and clear TCOx_STS<br>- * @return TCOx_STS registers<br>- */<br>-static u32 reset_tco_status(void)<br>-{<br>- u32 tcobase = pmbase + 0x60;<br>- u32 reg32;<br>-<br>- reg32 = inl(tcobase + 0x04);<br>- /* set status bits are cleared by writing 1 to them */<br>- outl(reg32 & ~(1<<18), tcobase + 0x04); // Don't clear BOOT_STS before SECOND_TO_STS<br>- if (reg32 & (1 << 18))<br>- outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS<br>-<br>- return reg32;<br>-}<br>-<br>-<br>-static void dump_tco_status(u32 tco_sts)<br>-{<br>- printk(BIOS_DEBUG, "TCO_STS: ");<br>- if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");<br>- if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");<br>- if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");<br>- if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");<br>- if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");<br>- if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");<br>- if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");<br>- if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");<br>- if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");<br>- if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");<br>- if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");<br>- if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");<br>- if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-int southbridge_io_trap_handler(int smif)<br>-{<br>- switch (smif) {<br>- case 0x32:<br>- printk(BIOS_DEBUG, "OS Init\n");<br>- /* gnvs->smif:<br>- * On success, the IO Trap Handler returns 0<br>- * On failure, the IO Trap Handler returns a value != 0<br>- */<br>- gnvs->smif = 0;<br>- return 1; /* IO trap handled */<br>- }<br>-<br>- /* Not handled */<br>- return 0;<br>-}<br>-<br>-/**<br>- * @brief Set the EOS bit<br>- */<br>-void southbridge_smi_set_eos(void)<br>-{<br>- u8 reg8;<br>-<br>- reg8 = inb(pmbase + SMI_EN);<br>- reg8 |= EOS;<br>- outb(reg8, pmbase + SMI_EN);<br>-}<br>-<br>-static void busmaster_disable_on_bus(int bus)<br>-{<br>- int slot, func;<br>- unsigned int val;<br>- unsigned char hdr;<br>-<br>- for (slot = 0; slot < 0x20; slot++) {<br>- for (func = 0; func < 8; func++) {<br>- u32 reg32;<br>- pci_devfn_t dev = PCI_DEV(bus, slot, func);<br>-<br>- val = pci_read_config32(dev, PCI_VENDOR_ID);<br>-<br>- if (val == 0xffffffff || val == 0x00000000 ||<br>- val == 0x0000ffff || val == 0xffff0000)<br>- continue;<br>-<br>- /* Disable Bus Mastering for this one device */<br>- reg32 = pci_read_config32(dev, PCI_COMMAND);<br>- reg32 &= ~PCI_COMMAND_MASTER;<br>- pci_write_config32(dev, PCI_COMMAND, reg32);<br>-<br>- /* If this is a bridge, then follow it. */<br>- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);<br>- hdr &= 0x7f;<br>- if (hdr == PCI_HEADER_TYPE_BRIDGE ||<br>- hdr == PCI_HEADER_TYPE_CARDBUS) {<br>- unsigned int buses;<br>- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);<br>- busmaster_disable_on_bus((buses >> 8) & 0xff);<br>- }<br>- }<br>- }<br>-}<br>-<br>-<br>-static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>- u8 reg8;<br>- u32 reg32;<br>- u8 slp_typ;<br>- /* FIXME: the power state on boot should be read from<br>- * CMOS or even better from GNVS. Right now it's hard<br>- * coded at compile time.<br>- */<br>- u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;<br>-<br>- /* First, disable further SMIs */<br>- reg8 = inb(pmbase + SMI_EN);<br>- reg8 &= ~SLP_SMI_EN;<br>- outb(reg8, pmbase + SMI_EN);<br>-<br>- /* Figure out SLP_TYP */<br>- reg32 = inl(pmbase + PM1_CNT);<br>- printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);<br>- slp_typ = acpi_sleep_from_pm1(reg32);<br>-<br>- /* Next, do the deed.<br>- */<br>-<br>- switch (slp_typ) {<br>- case ACPI_S0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;<br>- case ACPI_S1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;<br>- case ACPI_S3:<br>- printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");<br>- /* Invalidate the cache before going to S3 */<br>- wbinvd();<br>- break;<br>- case ACPI_S4: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;<br>- case ACPI_S5:<br>- printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");<br>-<br>- outl(0, pmbase + GPE0_EN);<br>-<br>- /* Should we keep the power state after a power loss?<br>- * In case the setting is "ON" or "OFF" we don't have<br>- * to do anything. But if it's "KEEP" we have to switch<br>- * to "OFF" before entering S5.<br>- */<br>- if (s5pwr == MAINBOARD_POWER_KEEP) {<br>- reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);<br>- reg8 |= 1;<br>- pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);<br>- }<br>-<br>- /* also iterates over all bridges on bus 0 */<br>- busmaster_disable_on_bus(0);<br>- break;<br>- default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;<br>- }<br>-<br>- /* Write back to the SLP register to cause the originally intended<br>- * event again. We need to set BIT13 (SLP_EN) though to make the<br>- * sleep happen.<br>- */<br>- outl(reg32 | SLP_EN, pmbase + PM1_CNT);<br>-<br>- /* In most sleep states, the code flow of this function ends at<br>- * the line above. However, if we entered sleep state S1 and wake<br>- * up again, we will continue to execute code in this function.<br>- */<br>- reg32 = inl(pmbase + PM1_CNT);<br>- if (reg32 & SCI_EN) {<br>- /* The OS is not an ACPI OS, so we set the state to S0 */<br>- reg32 &= ~(SLP_EN | SLP_TYP);<br>- outl(reg32, pmbase + PM1_CNT);<br>- }<br>-}<br>-<br>-static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>- u32 pmctrl;<br>- u8 reg8;<br>-<br>- /* Emulate B2 register as the FADT / Linux expects it */<br>-<br>- reg8 = inb(APM_CNT);<br>- switch (reg8) {<br>- case APM_CNT_CST_CONTROL:<br>- /* Calling this function seems to cause<br>- * some kind of race condition in Linux<br>- * and causes a kernel oops<br>- */<br>- printk(BIOS_DEBUG, "C-state control\n");<br>- break;<br>- case APM_CNT_PST_CONTROL:<br>- /* Calling this function seems to cause<br>- * some kind of race condition in Linux<br>- * and causes a kernel oops<br>- */<br>- printk(BIOS_DEBUG, "P-state control\n");<br>- break;<br>- case APM_CNT_ACPI_DISABLE:<br>- pmctrl = inl(pmbase + PM1_CNT);<br>- pmctrl &= ~SCI_EN;<br>- outl(pmctrl, pmbase + PM1_CNT);<br>- printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");<br>- break;<br>- case APM_CNT_ACPI_ENABLE:<br>- pmctrl = inl(pmbase + PM1_CNT);<br>- pmctrl |= SCI_EN;<br>- outl(pmctrl, pmbase + PM1_CNT);<br>- printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");<br>- break;<br>- case APM_CNT_GNVS_UPDATE:<br>- if (smm_initialized) {<br>- printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");<br>- return;<br>- }<br>- gnvs = *(global_nvs_t **)0x500;<br>- tcg = *(void **)0x504;<br>- smi1 = *(void **)0x508;<br>- smm_initialized = 1;<br>- printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);<br>- break;<br>- case APM_CNT_MBI_UPDATE: // FIXME<br>- if (mbi_initialized) {<br>- printk(BIOS_DEBUG, "SMI#: mbi already registered!\n");<br>- return;<br>- }<br>- mbi = *(void **)0x500;<br>- mbi_len = *(u32 *)0x504;<br>- mbi_initialized = 1;<br>- printk(BIOS_DEBUG, "SMI#: Registered MBI at %p (%d bytes)\n", mbi, mbi_len);<br>- break;<br>-<br>- default:<br>- printk(BIOS_DEBUG, "SMI#: Unknown function APM_CNT=%02x\n", reg8);<br>- }<br>-}<br>-<br>-static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>- u16 pm1_sts;<br>-<br>- pm1_sts = reset_pm1_status();<br>- dump_pm1_status(pm1_sts);<br>-<br>- /* While OSPM is not active, poweroff immediately<br>- * on a power button event.<br>- */<br>- if (pm1_sts & PWRBTN_STS) {<br>- // power button pressed<br>- u32 reg32;<br>- reg32 = (7 << 10) | (1 << 13);<br>- outl(reg32, pmbase + PM1_CNT);<br>- }<br>-}<br>-<br>-static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>- u32 gpe0_sts;<br>-<br>- gpe0_sts = reset_gpe0_status();<br>- dump_gpe0_status(gpe0_sts);<br>-}<br>-<br>-static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>- u16 reg16;<br>- reg16 = inw(pmbase + ALT_GP_SMI_STS);<br>- outl(reg16, pmbase + ALT_GP_SMI_STS);<br>-<br>- reg16 &= inw(pmbase + ALT_GP_SMI_EN);<br>-<br>- mainboard_smi_gpi(reg16);<br>-<br>- if (reg16)<br>- printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);<br>-}<br>-<br>-static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = inl(pmbase + SMI_EN);<br>-<br>- /* Are periodic SMIs enabled? */<br>- if ((reg32 & MCSMI_EN) == 0)<br>- return;<br>-<br>- printk(BIOS_DEBUG, "Microcontroller SMI.\n");<br>-}<br>-<br>-<br>-<br>-static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>- u32 tco_sts;<br>-<br>- tco_sts = reset_tco_status();<br>-<br>- /* Any TCO event? */<br>- if (!tco_sts)<br>- return;<br>-<br>- if (tco_sts & (1 << 8)) { // BIOSWR<br>- u8 bios_cntl;<br>-<br>- bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);<br>-<br>- if (bios_cntl & 1) {<br>- /* BWE is RW, so the SMI was caused by a<br>- * write to BWE, not by a write to the BIOS<br>- */<br>-<br>- /* This is the place where we notice someone<br>- * is trying to tinker with the BIOS. We are<br>- * trying to be nice and just ignore it. A more<br>- * resolute answer would be to power down the<br>- * box.<br>- */<br>- printk(BIOS_DEBUG, "Switching back to RO\n");<br>- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));<br>- } /* No else for now? */<br>- } else if (tco_sts & (1 << 3)) { /* TIMEOUT */<br>- /* Handle TCO timeout */<br>- printk(BIOS_DEBUG, "TCO Timeout.\n");<br>- } else if (!tco_sts) {<br>- dump_tco_status(tco_sts);<br>- }<br>-}<br>-<br>-static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>- u32 reg32;<br>-<br>- reg32 = inl(pmbase + SMI_EN);<br>-<br>- /* Are periodic SMIs enabled? */<br>- if ((reg32 & PERIODIC_EN) == 0)<br>- return;<br>-<br>- printk(BIOS_DEBUG, "Periodic SMI.\n");<br>-}<br>-<br>-static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>-#define IOTRAP(x) (trap_sts & (1 << x))<br>-#if 0<br>- u32 trap_sts, trap_cycle;<br>- u32 data, mask = 0;<br>- int i;<br>-<br>- trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register<br>- RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR<br>-<br>- trap_cycle = RCBA32(0x1e10);<br>- for (i=16; i<20; i++) {<br>- if (trap_cycle & (1 << i))<br>- mask |= (0xff << ((i - 16) << 2));<br>- }<br>-<br>-<br>- /* IOTRAP(3) SMI function call */<br>- if (IOTRAP(3)) {<br>- if (gnvs && gnvs->smif)<br>- io_trap_handler(gnvs->smif); // call function smif<br>- return;<br>- }<br>-<br>- /* IOTRAP(2) currently unused<br>- * IOTRAP(1) currently unused */<br>-<br>- /* IOTRAP(0) SMIC */<br>- if (IOTRAP(0)) {<br>- if (!(trap_cycle & (1 << 24))) { // It's a write<br>- printk(BIOS_DEBUG, "SMI1 command\n");<br>- data = RCBA32(0x1e18);<br>- data &= mask;<br>- // if (smi1)<br>- // southbridge_smi_command(data);<br>- // return;<br>- }<br>- // Fall through to debug<br>- }<br>-<br>- printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);<br>- for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);<br>- printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);<br>- printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);<br>- printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");<br>-<br>- if (!(trap_cycle & (1 << 24))) {<br>- /* Write Cycle */<br>- data = RCBA32(0x1e18);<br>- printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data);<br>- }<br>-#endif<br>-#undef IOTRAP<br>-}<br>-<br>-typedef void (*smi_handler_t)(unsigned int node,<br>- smm_state_save_area_t *state_save);<br>-<br>-smi_handler_t southbridge_smi[32] = {<br>- NULL, // [0] reserved<br>- NULL, // [1] reserved<br>- NULL, // [2] BIOS_STS<br>- NULL, // [3] LEGACY_USB_STS<br>- southbridge_smi_sleep, // [4] SLP_SMI_STS<br>- southbridge_smi_apmc, // [5] APM_STS<br>- NULL, // [6] SWSMI_TMR_STS<br>- NULL, // [7] reserved<br>- southbridge_smi_pm1, // [8] PM1_STS<br>- southbridge_smi_gpe0, // [9] GPE0_STS<br>- southbridge_smi_gpi, // [10] GPI_STS<br>- southbridge_smi_mc, // [11] MCSMI_STS<br>- NULL, // [12] DEVMON_STS<br>- southbridge_smi_tco, // [13] TCO_STS<br>- southbridge_smi_periodic, // [14] PERIODIC_STS<br>- NULL, // [15] SERIRQ_SMI_STS<br>- NULL, // [16] SMBUS_SMI_STS<br>- NULL, // [17] LEGACY_USB2_STS<br>- NULL, // [18] INTEL_USB2_STS<br>- NULL, // [19] reserved<br>- NULL, // [20] PCI_EXP_SMI_STS<br>- southbridge_smi_monitor, // [21] MONITOR_STS<br>- NULL, // [22] reserved<br>- NULL, // [23] reserved<br>- NULL, // [24] reserved<br>- NULL, // [25] EL_SMI_STS<br>- NULL, // [26] SPI_STS<br>- NULL, // [27] reserved<br>- NULL, // [28] reserved<br>- NULL, // [29] reserved<br>- NULL, // [30] reserved<br>- NULL // [31] reserved<br>-};<br>-<br>-/**<br>- * @brief Interrupt handler for SMI#<br>- * @param node<br>- * @param state_save<br>- */<br>-void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)<br>-{<br>- int i, dump = 0;<br>- u32 smi_sts;<br>-<br>- /* Update global variable pmbase */<br>- pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;<br>-<br>- /* We need to clear the SMI status registers, or we won't see what's<br>- * happening in the following calls.<br>- */<br>- smi_sts = reset_smi_status();<br>-<br>- /* Filter all non-enabled SMI events */<br>- // FIXME Double check, this clears MONITOR<br>- // smi_sts &= inl(pmbase + SMI_EN);<br>-<br>- /* Call SMI sub handler for each of the status bits */<br>- for (i = 0; i < 31; i++) {<br>- if (smi_sts & (1 << i)) {<br>- if (southbridge_smi[i])<br>- southbridge_smi[i](node, state_save);<br>- else {<br>- printk(BIOS_DEBUG, "SMI_STS[%d] occurred, but no "<br>- "handler available.\n", i);<br>- dump = 1;<br>- }<br>- }<br>- }<br>-<br>- if (dump) {<br>- dump_smi_status(smi_sts);<br>- }<br>-<br>-}<br>diff --git a/src/southbridge/intel/i82801dx/tco_timer.c b/src/southbridge/intel/i82801dx/tco_timer.c<br>deleted file mode 100644<br>index e773fa4..0000000<br>--- a/src/southbridge/intel/i82801dx/tco_timer.c<br>+++ /dev/null<br>@@ -1,31 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org><br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-static void i82801dx_halt_tco_timer(void)<br>-{<br>- /* Set the LPC device statically. */<br>- pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x0);<br>-<br>- /* Temporarily set ACPI base address (I/O space). */<br>- pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));<br>-<br>- /* Enable ACPI I/O. */<br>- pci_write_config8(dev, ACPI_CNTL, 0x10);<br>-<br>- /* Halt the TCO timer, preventing SMI and automatic reboot */<br>- outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11),<br>- PMBASE_ADDR + TCOBASE + TCO1_CNT);<br>-}<br>diff --git a/src/southbridge/intel/i82801dx/usb.c b/src/southbridge/intel/i82801dx/usb.c<br>deleted file mode 100644<br>index 518f608..0000000<br>--- a/src/southbridge/intel/i82801dx/usb.c<br>+++ /dev/null<br>@@ -1,63 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2004 Ronald G. Minnich<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include "i82801dx.h"<br>-<br>-static void usb_init(struct device *dev)<br>-{<br>- u32 cmd;<br>- printk(BIOS_DEBUG, "USB: Setting up controller.. ");<br>- cmd = pci_read_config32(dev, PCI_COMMAND);<br>- pci_write_config32(dev, PCI_COMMAND,<br>- cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |<br>- PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);<br>- printk(BIOS_DEBUG, "done.\n");<br>-}<br>-<br>-static struct device_operations usb_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = usb_init,<br>- .scan_bus = 0,<br>- .enable = i82801dx_enable,<br>-};<br>-<br>-/* 82801DB/DBL/DBM USB1 */<br>-static const struct pci_driver usb_driver_1 __pci_driver = {<br>- .ops = &usb_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82801DB_USB1,<br>-};<br>-<br>-/* 82801DB/DBL/DBM USB2 */<br>-static const struct pci_driver usb_driver_2 __pci_driver = {<br>- .ops = &usb_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82801DB_USB2,<br>-};<br>-<br>-/* 82801DB/DBL/DBM USB3 */<br>-static const struct pci_driver usb_driver_3 __pci_driver = {<br>- .ops = &usb_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82801DB_USB3,<br>-};<br>diff --git a/src/southbridge/intel/i82801dx/usb2.c b/src/southbridge/intel/i82801dx/usb2.c<br>deleted file mode 100644<br>index dda3d95..0000000<br>--- a/src/southbridge/intel/i82801dx/usb2.c<br>+++ /dev/null<br>@@ -1,50 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2003 Tyan<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <device/pci_ehci.h><br>-#include "i82801dx.h"<br>-<br>-static void usb2_init(struct device *dev)<br>-{<br>- u32 cmd;<br>- printk(BIOS_DEBUG, "USB: Setting up controller.. ");<br>- cmd = pci_read_config32(dev, PCI_COMMAND);<br>- pci_write_config32(dev, PCI_COMMAND,<br>- cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |<br>- PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE);<br>- printk(BIOS_DEBUG, "done.\n");<br>-}<br>-<br>-static struct device_operations usb2_ops = {<br>- .read_resources = pci_ehci_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = usb2_init,<br>- .scan_bus = 0,<br>- .enable = i82801dx_enable,<br>-};<br>-<br>-/* 82801DB/DBM USB 2.0 */<br>-static const struct pci_driver usb2_driver __pci_driver = {<br>- .ops = &usb2_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82801DB_EHCI,<br>-};<br></pre><p>To view, visit <a href="https://review.coreboot.org/22032">change 22032</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/22032"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9 </div>
<div style="display:none"> Gerrit-Change-Number: 22032 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>