[coreboot-gerrit] Change in coreboot[master]: Intel e7505 board & chips: Remove - using LATE_CBMEM_INIT
Martin Roth (Code Review)
gerrit at coreboot.org
Sun Oct 15 23:19:19 CEST 2017
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22028
Change subject: Intel e7505 board & chips: Remove - using LATE_CBMEM_INIT
......................................................................
Intel e7505 board & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.8 branch.
chips:
cpu/intel/socket_mPGA604
northbridge/intel/e7505
southbridge/intel/i82870
Mainboards:
mainboard/aopen/dxplplusu
Change-Id: Ib6c8b3942b66bf43f7e1a42edf24cad32120c61d
Signed-off-by: Martin Roth <gaumless at gmail.com>
---
D src/cpu/intel/socket_mPGA604/Kconfig
D src/mainboard/aopen/dxplplusu/Kconfig
D src/mainboard/aopen/dxplplusu/Kconfig.name
D src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl
D src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl
D src/mainboard/aopen/dxplplusu/acpi/i82801db.asl
D src/mainboard/aopen/dxplplusu/acpi/p64h2.asl
D src/mainboard/aopen/dxplplusu/acpi/power.asl
D src/mainboard/aopen/dxplplusu/acpi/scsi.asl
D src/mainboard/aopen/dxplplusu/acpi/superio.asl
D src/mainboard/aopen/dxplplusu/acpi_tables.c
D src/mainboard/aopen/dxplplusu/board_info.txt
D src/mainboard/aopen/dxplplusu/bus.h
D src/mainboard/aopen/dxplplusu/devicetree.cb
D src/mainboard/aopen/dxplplusu/dsdt.asl
D src/mainboard/aopen/dxplplusu/fadt.c
D src/mainboard/aopen/dxplplusu/irq_tables.c
D src/mainboard/aopen/dxplplusu/romstage.c
D src/northbridge/intel/e7505/Kconfig
D src/northbridge/intel/e7505/Makefile.inc
D src/northbridge/intel/e7505/debug.c
D src/northbridge/intel/e7505/debug.h
D src/northbridge/intel/e7505/e7505.h
D src/northbridge/intel/e7505/northbridge.c
D src/northbridge/intel/e7505/raminit.c
D src/northbridge/intel/e7505/raminit.h
D src/southbridge/intel/i82870/82870.h
D src/southbridge/intel/i82870/Kconfig
D src/southbridge/intel/i82870/Makefile.inc
D src/southbridge/intel/i82870/ioapic.c
D src/southbridge/intel/i82870/pci_parity.c
D src/southbridge/intel/i82870/pcibridge.c
32 files changed, 0 insertions(+), 4,028 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/22028/1
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
deleted file mode 100644
index 94d6a09..0000000
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-config CPU_INTEL_SOCKET_MPGA604
- bool
-
-if CPU_INTEL_SOCKET_MPGA604
-
-config SOCKET_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_MODEL_F2X
- select CPU_INTEL_MODEL_F3X
- select CPU_INTEL_MODEL_F4X
- select MMX
- select SSE
- select UDELAY_TSC
- select SIPI_VECTOR_IN_ROM
-
-# mPGA604 are usually Intel Netburst CPUs which should have SSE2
-# but the ramtest.c code on the Dell S1850 seems to choke on
-# enabling it, so disable it for now.
-config SSE2
- bool
- default n
-
-config DCACHE_RAM_BASE
- hex
- default 0xfefc0000
-
-config DCACHE_RAM_SIZE
- hex
- default 0x4000
-
-endif # CPU_INTEL_SOCKET_MPGA604
diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig
deleted file mode 100644
index 0823161..0000000
--- a/src/mainboard/aopen/dxplplusu/Kconfig
+++ /dev/null
@@ -1,41 +0,0 @@
-if BOARD_AOPEN_DXPLPLUSU
-
-config BOARD_SPECIFIC_OPTIONS # dummy
- def_bool y
- select CPU_INTEL_SOCKET_MPGA604
- select NORTHBRIDGE_INTEL_E7505
- select SOUTHBRIDGE_INTEL_I82870
- select SOUTHBRIDGE_INTEL_I82801DX
- select SUPERIO_SMSC_LPC47M10X
-# select HAVE_PIRQ_TABLE
-# select PIRQ_ROUTE
- select UDELAY_TSC
- select HAVE_ACPI_TABLES
- select BOARD_ROMSIZE_KB_2048
-# select HW_SCRUBBER
-
-config MAINBOARD_DIR
- string
- default aopen/dxplplusu
-
-config MAINBOARD_PART_NUMBER
- string
- default "DXPL Plus-U"
-
-config IRQ_SLOT_COUNT
- int
- default 12
-
-config MAX_CPUS
- int
- default 4
-
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
- hex
- default 0x0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
- hex
- default 0x0
-
-endif # BOARD_AOPEN_DXPLPLUSU
diff --git a/src/mainboard/aopen/dxplplusu/Kconfig.name b/src/mainboard/aopen/dxplplusu/Kconfig.name
deleted file mode 100644
index 1310203..0000000
--- a/src/mainboard/aopen/dxplplusu/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_AOPEN_DXPLPLUSU
- bool "DXPL Plus-U"
diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl
deleted file mode 100644
index 566704b..0000000
--- a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Device (MBRS)
-{
- Name (_HID, EisaId ("PNP0C01"))
- Name (_UID, 0x01)
- Name (MSBF, ResourceTemplate ()
- {
- /* System memory */
- QWordMemory (ResourceProducer, PosDecode, MinFixed,
- MaxNotFixed, Prefetchable, ReadWrite,
- 0x0, 0x100000000, 0x400000000, 0x0, 0x0, ,, _Y1C,
- AddressRangeMemory, TypeStatic)
-
- /* Top Of Low Memory */
- Memory32 (ReadOnly, 0x0, 0x0, 0x1, 0x0, _Y1D)
-
- /* 640kB who wants more? */
- Memory32Fixed (ReadWrite, 0x0, 0xA0000, )
-
- /* 64k BIOS bootblock */
- Memory32Fixed (ReadOnly, 0xF0000, 0x10000,)
-
- /* ISA memory hole 15-16 MB ? */
- /* Memory32Fixed (ReadOnly, 0x100000, 0xF00000,) */
- /* ISA memory hole 14-15 MB ? */
- /* Memory32Fixed (ReadOnly, 0x100000, 0xE00000,) */
-
- /* Local APIC */
- Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000,)
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- CreateQWordField (MSBF, \_SB.MBRS._Y1C._MIN, MEML)
- CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM)
- CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM)
-
- And (\_SB.PCI0.RLAR, 0x03FF, Local1)
- Increment (Local1)
- If (LGreater (Local1, 0x40))
- {
- ShiftLeft (Local1, 0x1A, LELM)
- }
-
-
- CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00)
- CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01)
- CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2)
- And (\_SB.PCI0.TOLM, 0xF800, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Decrement (Local1)
- If (LGreater (Local1, 0x10))
- {
- Subtract (Local1, 0x0F, Local1)
- Store (ShiftLeft (Local1, 0x14), MEM2)
- Store (0x01000000, MS00)
- Store (MS00, MS01)
- }
-
- Return (MSBF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
-}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl
deleted file mode 100644
index 6ae2750..0000000
--- a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Name (PBRS, ResourceTemplate ()
-{
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100, ,, )
-
- /* System IO */
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0, 0x0, 0xffff, 0x0000, 0x10000, ,,, TypeStatic)
- IO (Decode16, 0x0CF8, 0x0CF8, 0x08, 0x08, )
-
- /* Video RAM */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, 0x000A0000, 0x000BFFFF,
- 0x00000000, 0x00020000, ,,, AddressRangeMemory, TypeStatic)
-
- /* Video ROM */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, 0x000C0000, 0x000C7FFF,
- 0x00000000, 0x00008000, ,,, AddressRangeMemory, TypeStatic)
-
- /* Option ROMs ? */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, 0x000C8000, 0x000DFFFF,
- 0x00000000, 0x00018000, ,,, AddressRangeMemory, TypeStatic)
-
- /* Top Of Lowmemory to IOAPIC */
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, 0x00000000, 0xFEBFFFFF,
- 0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic)
-})
-
-
-Method (_CRS, 0, NotSerialized)
-{
-
- /* Top Of Lowmemory to IOAPIC */
- CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML)
- CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH)
- CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM)
- And (\_SB.PCI0.TOLM, 0xF800, Local1)
- ShiftRight (Local1, 0x04, Local1)
- ShiftLeft (Local1, 0x14, MEML)
- Subtract (IO_APIC_ADDR, 0x01, MEMH)
- Subtract (IO_APIC_ADDR, MEML, LENM)
-
- Return (PBRS)
-}
-
-Method (_STA, 0, NotSerialized)
-{
- Return (0x0F)
-}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl
deleted file mode 100644
index 633007d..0000000
--- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-Device (USB0)
-{
- Name (_ADR, 0x001D0000)
- Name (_PRW, Package () { 0x03, 0x05 })
-
- OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
- Field (USBS, ByteAcc, NoLock, Preserve)
- {
- Offset (0xC4), URES, 8
- }
-}
-
-Device (USB1)
-{
- Name (_ADR, 0x001D0001)
- Name (_PRW, Package () { 0x04, 0x05 })
- OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
- Field (USBS, ByteAcc, NoLock, Preserve)
- {
- Offset (0xC4), URES, 8
- }
-}
-
-Device (USB2)
-{
- Name (_ADR, 0x001D0002)
- Name (_PRW, Package () { 0x0C, 0x05 })
- OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
- Field (USBS, ByteAcc, NoLock, Preserve)
- {
- Offset (0xC4), URES, 8
- }
-}
-
-Device (USB3)
-{
- Name (_ADR, 0x001D0007)
- Name (_PRW, Package () { 0x0D, 0x05 }) /* PME_B0_STS any 0:1d or 0:1f device */
- OperationRegion (USBS, PCI_Config, 0x00, 0x0100)
- Field (USBS, ByteAcc, NoLock, Preserve)
- {
- Offset (0xC4), URES, 8
- }
-}
-
-Device(PCI5)
-{
- Name (_ADR, 0x001E0000)
- Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
- Name (_PRT, Package() {
- Package() { 0x0003ffff, 0, 0, 20 },
- Package() { 0x0003ffff, 1, 0, 21 },
- Package() { 0x0003ffff, 2, 0, 22 },
- Package() { 0x0003ffff, 3, 0, 23 },
- })
-}
-
-Device (ICH0)
-{
- Name (_ADR, 0x001F0000)
- OperationRegion (D310, PCI_Config, 0x00, 0xFF)
- Field (D310, ByteAcc, NoLock, Preserve)
- {
- Offset (0x40), PBAR, 16,
- Offset (0x58), GBAR, 16,
- }
-
- OperationRegion (ACPI, SystemIO, 0x0400, 0xC0)
- Field (ACPI, ByteAcc, NoLock, Preserve)
- {
- Offset (0x00), PS1L,8, PS1H,8, PE1L,8, PE1H,8,
- Offset (0x28), GS0L,8, GS0H,8, GSPL,8, GSPH,8,
- Offset (0x2C), GE0L,8, GE0H,8, GEPL,8, GEPH,8,
- Offset (0xB8), GPLV,8
- }
-
- Name (MSBF, ResourceTemplate ()
- {
- /* IOAPIC 0 */
- Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,)
-
- IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO)
- IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO)
-
- /* 8254 legacy irq */
- IO (Decode16, 0x04D0, 0x04D0, 0x02, 0x02,)
-
- /* reset generator */
- IO (Decode16, 0x0092, 0x0092, 0x01, 0x01, )
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MIN, IOA1)
- CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MAX, IOA2)
- CreateByteField (MSBF, \_SB_.PCI0.ICH0.PMIO._LEN, IOAL)
-
- Store (PBAR, Local0)
- If ( Land(Local0, 0x01) )
- {
- And (Local0, 0xFFFE, Local0)
- Store (Local0, IOA1)
- Store (Local0, IOA2)
- Store (0x80, IOAL)
- } Else {
- Store (0x00, IOAL)
- }
-
- CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MIN, IOS1)
- CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MAX, IOS2)
- CreateByteField (MSBF, \_SB_.PCI0.ICH0.GPIO._LEN, IOSL)
-
- Store (GBAR, Local0)
- If ( Land(Local0, 0x01) ) {
- And (Local0, 0xFFFE, Local0)
- Store (Local0, IOS1)
- Store (Local0, IOS2)
- Store (0x40, IOSL)
- } Else {
- Store (0x00, IOSL)
- }
- Return (MSBF)
- }
-
- Device (FWH)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
-
-
- Name (MSBG, ResourceTemplate () {
- Memory32Fixed (ReadOnly, 0xFFF00000, 0x00080000,)
- Memory32Fixed (ReadOnly, 0xFFF80000, 0x00080000,)
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- Return (MSBG)
- }
- }
-
- Device (SMSC)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x02)
- #include "acpi/superio.asl"
- }
-
-}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl
deleted file mode 100644
index e3f2e5f..0000000
--- a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Interrupt routing for PCI 03:xx.x */
-
-/* I/O APIC id 0x3 */
-Device(PBIO)
-{
- Name (_HID, "ACPI000A")
- Name (_ADR, 0x001c0000)
-}
-
-/* PCI-X bridge */
-Device(P64B)
-{
- Name (_ADR, 0x001d0000)
- Name (_PRT, Package() {
- Package() { 0x0002ffff, 0, 0, 24 }, /* PCI-X slot 1 */
- Package() { 0x0002ffff, 1, 0, 25 },
- Package() { 0x0002ffff, 2, 0, 26 },
- Package() { 0x0002ffff, 3, 0, 27 },
- Package() { 0x0003ffff, 0, 0, 28 }, /* PCI-X slot 2 */
- Package() { 0x0003ffff, 1, 0, 29 },
- Package() { 0x0003ffff, 2, 0, 30 },
- Package() { 0x0003ffff, 3, 0, 31 },
- Package() { 0x0004ffff, 0, 0, 32 }, /* On-board GbE */
- })
-
- Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
- OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)
- Field (PBPC, ByteAcc, NoLock, Preserve)
- {
- Offset (0x3E), BCRL, 8, BCRH, 8
- }
-
-
- Device (ETH0)
- {
- Name (_ADR, 0x00040000)
- Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
- }
-}
-
-
-/* Interrupt routing for PCI 04:xx.x */
-
-/* I/O APIC id 0x4 */
-Device(PAIO)
-{
- Name (_HID, "ACPI000A")
- Name (_ADR, 0x001e0000)
-}
-
-/* PCI-X bridge */
-Device(P64A)
-{
- Name (_ADR, 0x001f0000)
- Name (_PRT, Package() {
- Package() { 0x0002ffff, 0, 0, 48 }, /* PCI-X slot 3 */
- Package() { 0x0002ffff, 1, 0, 49 },
- Package() { 0x0002ffff, 2, 0, 50 },
- Package() { 0x0002ffff, 3, 0, 51 },
- Package() { 0x0003ffff, 0, 0, 52 }, /* PCI-X slot 4 */
- Package() { 0x0003ffff, 1, 0, 53 },
- Package() { 0x0003ffff, 2, 0, 54 },
- Package() { 0x0003ffff, 3, 0, 55 },
- Package() { 0x0004ffff, 0, 0, 54 }, /* On-board SCSI, GSI not 56 ? */
- Package() { 0x0004ffff, 1, 0, 55 }, /* On-board SCSI, GSI not 57 */
- })
-
- Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */
- OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)
- Field (PBPC, ByteAcc, NoLock, Preserve)
- {
- Offset (0x3E), BCRL, 8, BCRH, 8
- }
-
- #include "acpi/scsi.asl"
-}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/power.asl b/src/mainboard/aopen/dxplplusu/acpi/power.asl
deleted file mode 100644
index 69c1d62..0000000
--- a/src/mainboard/aopen/dxplplusu/acpi/power.asl
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-/* Board powers on with button or PME# from on-board GbE wake-on-lan.
- * Board shuts down to S5/G2. Any other power management is untested.
- */
-
-Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
-Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 })
-Name (\_S3, Package () { 0x05, 0x05, 0x00, 0x00 })
-Name (\_S4, Package () { 0x06, 0x06, 0x00, 0x00 })
-Name (\_S5, Package () { 0x07, 0x07, 0x00, 0x00 })
-
-Scope (\_GPE)
-{
- Method (_L03, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.USB0, 0x02)
- }
- Method (_L04, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.USB1, 0x02)
- }
-
- /* WOL header */
- Method (_L08, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.PCI5, 0x02)
- Notify (\_SB.SLBT, 0x02)
- }
-
- /* PME# */
- Method (_L0B, 0, NotSerialized)
- {
-#if 1
- Notify (\_SB.LID0, 0x02)
-#else
- Notify (\_SB.PCI0.HLIB.P64B.ETH0, 0x02)
- Notify (\_SB.PCI0.HLIB.P64B, 0x02)
- Notify (\_SB.PCI0.HLIB.P64A, 0x02)
-#endif
- }
-
- Method (_L0C, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.USB2, 0x02)
- }
-
- /* PME_B0_STS# */
- Method (_L0D, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.USB3, 0x02)
- }
-}
-
-/* Clear power buttons */
-Method (\_INI, 0, NotSerialized)
-{
- Or (\_SB.PCI0.ICH0.PS1H, 0x09, \_SB.PCI0.ICH0.PS1H)
- Or (\_SB.PCI0.ICH0.PE1H, 0x01, \_SB.PCI0.ICH0.PE1H)
-}
-
-/* Prepare To Sleep */
-Method (\_PTS, 1, NotSerialized)
-{
- Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H)
- Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L)
-}
-
-/* System Wake */
-Method (\_WAK, 1, NotSerialized)
-{
- Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H)
- Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L)
-
- Return ( Package() { 0x0, 0x0 } )
-}
diff --git a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl
deleted file mode 100644
index e76deb7..0000000
--- a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* PCI-X devices 04:04.0 and 04:04.1 : AIC-7902W
- * U320 SCSI dual-channel controller
- */
-
-Device (SCS0)
-{
- Name (_ADR, 0x00040000)
- OperationRegion (SCSC, PCI_Config, 0x00, 0x0100)
- Field (SCSC, ByteAcc, NoLock, Preserve)
- {
- Offset (0x2C), SID, 32,
- Offset (0xE0), PMC, 8,
- Offset (0xFF), IDW, 8
- }
-}
-
-Device (SCS1)
-{
- Name (_ADR, 0x00040001)
- OperationRegion (SCSC, PCI_Config, 0x00, 0x0100)
- Field (SCSC, ByteAcc, NoLock, Preserve)
- {
- Offset (0x2C), SID, 32,
- Offset (0xE0), PMC, 8,
- Offset (0xFF), IDW, 8
- }
-}
-
-#if 0
-/* Set subsystem id for both SCSI devices.
- * It may require some delay on wake-up before this can be done.
- */
- Method ( )
- {
- Or (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS0.IDW)
- Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS0.SID)
- And (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS0.IDW)
-
- Or (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS1.IDW)
- Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS1.SID)
- And (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS1.IDW)
- }
-#endif
diff --git a/src/mainboard/aopen/dxplplusu/acpi/superio.asl b/src/mainboard/aopen/dxplplusu/acpi/superio.asl
deleted file mode 100644
index c042c32..0000000
--- a/src/mainboard/aopen/dxplplusu/acpi/superio.asl
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-/* SuperIO GPIO configuration via logical device 0x0A */
-
-Name (MSBF, ResourceTemplate ()
-{
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x80, _Y1B)
-})
-
-OperationRegion (LPC0, SystemIO, 0x0E00, 0x60)
-Field (LPC0, ByteAcc, NoLock, Preserve)
-{
- PME0, 8,
- Offset (0x02), PME2,8,
- Offset (0x04), PME4,8,
- Offset (0x0A), PMEA,8,
- Offset (0x23),
- GC10,8, GC11,8, GC12,8, GC13,8, GC14,8, GC15,8, GC16,8, GC17,8,
- GC20,8, GC21,8, GC22,8, GC23,8, GC24,8, GC25,8, GC26,8, GC27,8,
- GC30,8, GC31,8, GC32,8, GC33,8, GC34,8, GC35,8, GC36,8, GC37,8,
- GC40,8, GC41,8, GC42,8, GC43,8,
-
- Offset (0x3F),
- GC50,8, GC51,8, GC52,8, GC53,8, GC54,8, GC55,8, GC56,8, GC57,8,
- GC60,8, GC61,8,
-
- Offset (0x4B),
- GP_1,8, GP_2,8, GP_3,8, GP_4,8, GP_5,8, GP_6,8,
- Offset (0x56), FAN1,8,
- Offset (0x5D), LED1,8, LED2,8,
-}
-
-OperationRegion (SMC1, SystemIO, 0x2E, 0x02)
-Field (SMC1, ByteAcc, NoLock, Preserve)
-{
- INDX, 8, DATA, 8
-}
-
-IndexField (INDX, DATA, ByteAcc, NoLock, Preserve)
-{
- Offset (0x07), LDN, 8,
- Offset (0x22), PWRC, 8,
- Offset (0x30), ACTR, 8,
- Offset (0x60),
- IOAH, 8, IOAL, 8,
- IOBH, 8, IOBL, 8,
-
- Offset (0x70), INTR, 8,
- Offset (0x72), INT1, 8,
- Offset (0x74), DMCH, 8,
- Offset (0xB2), SPS1, 8, SPS2, 8,
- Offset (0xB8), D2TS, 8,
- Offset (0xF0), OPT1, 8, OPT2, 8, OPT3, 8,
- Offset (0xF4), WDTC, 8,
- Offset (0xF6), GP01, 8, GP02, 8, GP04, 8
-}
-
-Method (ECFG, 0, NotSerialized)
-{
- Store (0x55, INDX)
-}
-Method (XCFG, 0, NotSerialized)
-{
- Store (0xAA, INDX)
-}
-
-Method (_CRS, 0, NotSerialized)
-{
- CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MIN, IOM1)
- CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MAX, IOM2)
- CreateByteField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._LEN, IOML)
-
- ECFG ()
- Store (0x0A, \_SB.PCI0.ICH0.SMSC.LDN)
- Store (0x00, IOM1)
- Store (0x00, IOM2)
- Or (\_SB.PCI0.ICH0.SMSC.IOAH, IOM1, IOM1)
- ShiftLeft (IOM1, 0x08, IOM1)
- Or (\_SB.PCI0.ICH0.SMSC.IOAL, IOM1, IOM1)
- Store (IOM1, IOM2)
- If (LNotEqual (IOM1, 0x00))
- {
- Store (0x80, IOML)
- }
- XCFG ()
-
- Return (MSBF)
-}
-
-
-Method (_INI, 0, NotSerialized)
-{
- /* GPIO configuration */
- Store (0x00, GC10)
- Store (0x81, GC11)
- Store (0x00, GC17)
- Store (0x0c, GC21)
- Store (0x00, GC22)
- Store (0x04, GC27)
- Store (0x04, GC30)
- Store (0x01, GC31)
- Store (0x01, GC32)
- Store (0x01, GC33)
- Store (0x01, GC34) /* GPI password jumper */
- Store (0x01, GC35) /* GPI scsi enable jumper */
-#if 1
- Store (0x01, GC42) /* GPI */
-#else
- Store (0x84, GC42) /* nIO_PME */
-#endif
- Store (0x86, GC60) /* led 1 */
- Store (0x81, GC61) /* led 2 ?? */
-
- /* GPIO initial output levels */
- Store (GP_1, Local0)
- And( Local0, 0x7C, Local0)
- Or ( Local0, 0x81, Local0)
- Store (Local0, GP_1)
-
- Store (GP_2, Local0)
- And( Local0, 0xFE, Local0)
- Or ( Local0, 0x00, Local0)
- Store (Local0, GP_2)
-
- Store (GP_3, Local0)
- And( Local0, 0x7F, Local0)
- Or ( Local0, 0x80, Local0)
- Store (Local0, GP_3)
-
- Store (GP_4, Local0)
- And( Local0, 0x7F, Local0)
- Or ( Local0, 0x00, Local0)
- Store (Local0, GP_4)
-
- /* Power Led */
- Store (LED1, Local0)
- And( Local0, 0xfc, Local0)
- Or ( Local0, 0x01, Local0)
- Store (Local0, LED1)
-
-}
-
-Method (MLED, 1, NotSerialized)
-{
- If (LEqual (Arg0, 0x00))
- {
- Store (0x00, LED1)
- }
-
- If (LOr (LEqual (Arg0, 0x01), LEqual (Arg0, 0x02)))
- {
- Store (0x01, LED1)
- }
-
- If (LEqual (Arg0, 0x03))
- {
- Store (0x02, LED1)
- }
-
- If (LOr (LEqual (Arg0, 0x04), LEqual (Arg0, 0x05)))
- {
- Store (0x03, LED1)
- }
-}
diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c
deleted file mode 100644
index e2f4c23..0000000
--- a/src/mainboard/aopen/dxplplusu/acpi_tables.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Written by Stefan Reinauer <stepan at openbios.org>
- * (C) 2005 Stefan Reinauer
- * (C) 2005 Digital Design Corporation
- *
- * Ported to Intel XE7501DEVKIT by Agami Aruma
- * Ported to AOpen DXPL Plus-U by Kyösti Mälkki
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <assert.h>
-#include "bus.h"
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int irq_start = 0;
- device_t dev = 0;
- struct resource* res = NULL;
-
- /* SJM: Hard-code CPU LAPIC entries for now */
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7);
-
- /* Southbridge IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
- /* P64H2 Bus B IOAPIC */
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
- if (!dev)
- BUG(); /* Config.lb error? */
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
- /* P64H2 Bus A IOAPIC */
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
- if (!dev)
- BUG(); /* Config.lb error? */
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
-
- /* Map ISA IRQ 0 to IRQ 2 */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
-
- /* IRQ9 differs from ISA standard - ours is active high, level-triggered */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
-
- return current;
-}
diff --git a/src/mainboard/aopen/dxplplusu/board_info.txt b/src/mainboard/aopen/dxplplusu/board_info.txt
deleted file mode 100644
index 4e50628..0000000
--- a/src/mainboard/aopen/dxplplusu/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: server
-Board URL: ftp://ftp.aopen.com/pub/server/motherboard/dxplpu/manual/dxplpu-ol-e.pdf
-ROM package: PLCC
-ROM protocol: FWH
-ROM socketed: y
-Flashrom support: y
diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h
deleted file mode 100644
index 965b8b7..0000000
--- a/src/mainboard/aopen/dxplplusu/bus.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef DXPLPLUSU_BUS_H_INCLUDED
-#define DXPLPLUSU_BUS_H_INCLUDED
-
-/* These were determined by seeing how coreboot enumerates the various
- * PCI (and PCI-like) buses on the board.
- */
-
-#define PCI_BUS_ROOT 0
-#define PCI_BUS_AGP 1 /* AGP */
-#define PCI_BUS_E7501_HI_B 2 /* P64H2#1 */
-#define PCI_BUS_P64H2_B 3 /* P64H2#1 bus B */
-#define PCI_BUS_P64H2_A 4 /* P64H2#1 bus A */
-#define PCI_BUS_ICH4 5 /* ICH4 */
-
-/* IOAPIC addresses determined by coreboot enumeration. */
-/* Someday add functions to get APIC IDs and versions from the chips themselves. */
-
-#define IOAPIC_ICH4 2
-#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 */
-#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 */
-
-#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */
-
-#endif
diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb
deleted file mode 100644
index bc80e87..0000000
--- a/src/mainboard/aopen/dxplplusu/devicetree.cb
+++ /dev/null
@@ -1,85 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
-##
-## This program is free software; you can redistribute it and/or
-## modify it under the terms of the GNU General Public License as
-## published by the Free Software Foundation; version 2 of
-## the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-chip northbridge/intel/e7505
-
- device cpu_cluster 0 on
- chip cpu/intel/socket_mPGA604
- device lapic 0 on end
- device lapic 6 on end
- end
- end
-
- device domain 0 on
- device pci 0.0 on end # Chipset host controller
- device pci 0.1 on end # Host RASUM controller
- device pci 2.0 on # Hub interface B
- chip southbridge/intel/i82870 # P64H2
- device pci 1c.0 on end # IOAPIC - bus B
- device pci 1d.0 on end # Hub to PCI-B bridge
- device pci 1e.0 on end # IOAPIC - bus A
- device pci 1f.0 on end # Hub to PCI-A bridge
- end
- end
- device pci 4.0 off end # (undocumented)
- device pci 6.0 off end # (undocumented)
- chip southbridge/intel/i82801dx
- device pci 1d.0 on end # USB UHCI
- device pci 1d.1 on end # USB UHCI
- device pci 1d.2 on end # USB UHCI
- device pci 1d.7 on end # USB EHCI
- device pci 1e.0 on # Hub to PCI bridge
- device pci 2.0 off end
- end
- device pci 1f.0 on # LPC bridge
- chip superio/smsc/lpc47m10x
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.3 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.7 off # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # Keyboard interrupt
- irq 0x72 = 12 # Mouse interrupt
- end
- device pnp 2e.a on # ACPI
- io 0x60 = 0x0e00
- end
- end
- end
- device pci 1f.1 on end # IDE
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- device pci 1f.3 on end # SMBus
- device pci 1f.5 on end # AC97 Audio
- device pci 1f.6 off end # AC97 Modem
- end # SB
- end # PCI domain
-end
diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl
deleted file mode 100644
index 0fec68c..0000000
--- a/src/mainboard/aopen/dxplplusu/dsdt.asl
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/ioapic.h>
-
-DefinitionBlock(
- "dsdt.aml",
- "DSDT",
- 0x04, // DSDT revision: ACPI v4.0
- "COREv4", // OEM id
- "COREBOOT", // OEM table id
- 0x20111103 // OEM revision
-) {
-
-Scope(\_SB)
-{
- Device(PCI0) {
- Name (_HID, EISAID("PNP0A03"))
- Name (_ADR, 0x00)
- Name (_PRT, Package() {
- Package() { 0x001dffff, 0, 0, 16 },
- Package() { 0x001dffff, 1, 0, 19 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 23 },
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 17 },
- })
-
- #include "acpi/e7505_sec.asl"
-
- OperationRegion (I750, PCI_Config, 0x00, 0x0100)
- Field (I750, ByteAcc, NoLock, Preserve)
- {
- Offset (0xC4),
- TOLM, 16, /* Top of Low Memory */
- RBAR, 16, /* REMAP_BASE */
- RLAR, 16 /* REMAP_LIMIT */
- }
- }
-
- #include "acpi/e7505_pri.asl"
-
-
- Device (PWBT)
- {
- Name (_HID, EisaId ("PNP0C0C"))
- Name (_PRW, Package () { 0x08, 0x05 })
- }
-
- Device (SLBT)
- {
- Name (_HID, EisaId ("PNP0C0E"))
- Name (_PRW, Package () { 0x0B, 0x05 })
- }
-
- Device (LID0)
- {
- Name (_HID, EisaId ("PNP0C0D"))
- Name (_PRW, Package () { 0x0B, 0x05 })
- }
-
-}
-
-Scope(\_SB.PCI0)
-{
-
- Device(PCI1)
- {
- Name (_ADR, 0x00010000)
- Name (_PRT, Package() {
- Package() { 0x0000ffff, 0, 0, 16 },
- Package() { 0x0000ffff, 1, 0, 17 },
- })
- }
-
- Device(HLIB)
- {
- Name (_ADR, 0x00020000)
- Name (_PRT, Package() {
- Package() { 0x001dffff, 0, 0, 18 },
- Package() { 0x001dffff, 1, 0, 18 },
- Package() { 0x001dffff, 2, 0, 18 },
- Package() { 0x001dffff, 3, 0, 18 },
- Package() { 0x001fffff, 0, 0, 18 },
- Package() { 0x001fffff, 1, 0, 18 },
- Package() { 0x001fffff, 2, 0, 18 },
- Package() { 0x001fffff, 3, 0, 18 },
- })
-
- #include "acpi/p64h2.asl"
- }
-
- #include "acpi/i82801db.asl"
-}
-
-#include "acpi/power.asl"
-
-}
diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c
deleted file mode 100644
index 418d547..0000000
--- a/src/mainboard/aopen/dxplplusu/fadt.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <device/pci.h>
-#include <arch/acpi.h>
-
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT 0x0 /* ACPI mode only */
-#define CST_CONTROL 0x85
-#define PST_CONTROL 0x0
-#define ACPI_DISABLE 0xAA
-#define ACPI_ENABLE 0x55
-#define S4_BIOS 0x77
-#define GNVS_UPDATE 0xea
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
- acpi_header_t *header = &(fadt->header);
- u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
-
- memset((void *) fadt, 0, sizeof(acpi_fadt_t));
- memcpy(header->signature, "FACP", 4);
- header->length = sizeof(acpi_fadt_t);
- header->revision = 4;
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
- header->asl_compiler_revision = 1;
-
- fadt->firmware_ctrl = (unsigned long) facs;
- fadt->dsdt = (unsigned long) dsdt;
- fadt->model = 1;
- fadt->preferred_pm_profile = 0; /* PM_MOBILE; */
-
- fadt->sci_int = 0x9;
- fadt->smi_cmd = APM_CNT;
- fadt->acpi_enable = ACPI_ENABLE;
- fadt->acpi_disable = ACPI_DISABLE;
- fadt->s4bios_req = S4_BIOS;
- fadt->pstate_cnt = PST_CONTROL;
-
- fadt->pm1a_evt_blk = pmbase;
- fadt->pm1b_evt_blk = 0x0;
- fadt->pm1a_cnt_blk = pmbase + 0x4;
- fadt->pm1b_cnt_blk = 0x0;
- fadt->pm2_cnt_blk = 0x0;
- fadt->pm_tmr_blk = pmbase + 0x8;
- fadt->gpe0_blk = pmbase + 0x28;
- fadt->gpe1_blk = 0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- /* XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) */
- fadt->pm2_cnt_len = 0;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 8;
- fadt->gpe1_blk_len = 0;
- fadt->gpe1_base = 0;
- fadt->cst_cnt = 0; /* CST_CONTROL; */
- fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = 85;
- fadt->flush_size = 1024;
- fadt->flush_stride = 16;
- fadt->duty_offset = 1;
- fadt->duty_width = 0;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
- fadt->century = 0x00;
- fadt->iapc_boot_arch = 0x03;
-
- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
-
- fadt->reset_reg.space_id = 0;
- fadt->reset_reg.bit_width = 0;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0x0;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 0;
- fadt->x_firmware_ctl_l = (unsigned long)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (unsigned long)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pmbase;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 0;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 0;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = 0x0;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 64;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = pmbase + 0x28;
- fadt->x_gpe0_blk.addrh = 0x0;
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 0;
- fadt->x_gpe1_blk.bit_offset = 0;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum =
- acpi_checksum((void *) fadt, header->length);
-}
diff --git a/src/mainboard/aopen/dxplplusu/irq_tables.c b/src/mainboard/aopen/dxplplusu/irq_tables.c
deleted file mode 100644
index 8d9298b..0000000
--- a/src/mainboard/aopen/dxplplusu/irq_tables.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include "bus.h"
-
-#define UNUSED_INTERRUPT {0, 0}
-#define PIRQ_A 0x60
-#define PIRQ_B 0x61
-#define PIRQ_C 0x62
-#define PIRQ_D 0x63
-#define PIRQ_E 0x68
-#define PIRQ_F 0x69
-#define PIRQ_G 0x6A
-#define PIRQ_H 0x6B
-
-static const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Size of this struct in bytes */
- 0, /* PCI bus number on which the interrupt router resides */
- PCI_DEVFN(31, 0), /* PCI device/function number of the interrupt router */
- 0, /* PCI-exclusive IRQ bitmap */
- PCI_VENDOR_ID_INTEL, /* Vendor ID of compatible PCI interrupt router */
- PCI_DEVICE_ID_INTEL_82801DB_LPC, /* Device ID of compatible PCI interrupt router */
- 0, /* Additional miniport information */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* Reserved, must be zero */
- 0xB1, /* Checksum of the entire structure (causes 8-bit sum == 0) */
- {
- /* NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space */
- /* This was determined from linux-2.6.11/arch/i386/pci/irq.c */
- /* bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 */
- /* ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 */
- /* Not sure why IRQ9 isn't routable (inherited from Tyan S2735) */
-
- /* INTA# INTB# INTC# INTD# */
- /* bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu */
-
- {PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, /* IDE / SMBus */
- {PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, /* USB 1.1 */
-
- {PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
- {PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
- {PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, /* GbE */
-
- {PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
- {PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},
- {PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, /* SCSI */
-
- {PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, /* 32-bit slot */
-
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c
deleted file mode 100644
index f79d3d3..0000000
--- a/src/mainboard/aopen/dxplplusu/romstage.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <stdlib.h>
-#include <console/console.h>
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-
-#include <southbridge/intel/i82801dx/i82801dx.h>
-#include <northbridge/intel/e7505/raminit.h>
-
-#include <device/pnp_def.h>
-#include <superio/smsc/lpc47m10x/lpc47m10x.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1)
-
-int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-void mainboard_romstage_entry(unsigned long bist)
-{
- static const struct mem_controller memctrl[] = {
- {
- .d0 = PCI_DEV(0, 0, 0),
- .d0f1 = PCI_DEV(0, 0, 1),
- .channel0 = { 0x50, 0x52, 0, 0 },
- .channel1 = { 0x51, 0x53, 0, 0 },
- },
- };
-
- /* Get the serial port running and print a welcome banner */
- lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- /* If this is a warm boot, some initialization can be skipped */
- if (!e7505_mch_is_ready()) {
- enable_smbus();
-
- /* The real MCH initialisation. */
- e7505_mch_init(memctrl);
-
- /*
- * ECC scrub invalidates cache, so all stack in CAR
- * is lost. Only return addresses from main() and
- * scrub_ecc() are recovered to stack via xmm0-xmm3.
- */
-#if IS_ENABLED(CONFIG_HW_SCRUBBER)
-#if !IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)
- unsigned long ret_addr = (unsigned long)((unsigned long*)&bist - 1);
- e7505_mch_scrub_ecc(ret_addr);
-#endif
-#endif
-
- /* Hook for post ECC scrub settings and debug. */
- e7505_mch_done(memctrl);
- }
-
- printk(BIOS_DEBUG, "SDRAM is up.\n");
-}
diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
deleted file mode 100644
index 702ba1c..0000000
--- a/src/northbridge/intel/e7505/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2012 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config NORTHBRIDGE_INTEL_E7505
- bool
-
-if NORTHBRIDGE_INTEL_E7505
-
-config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
- def_bool y
- select NO_MMCONF_SUPPORT
- select HAVE_DEBUG_RAM_SETUP
- select LATE_CBMEM_INIT
-
-config HW_SCRUBBER
- bool
- default n
-
-endif
diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc
deleted file mode 100644
index 89a5b8c..0000000
--- a/src/northbridge/intel/e7505/Makefile.inc
+++ /dev/null
@@ -1,7 +0,0 @@
-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y)
-
-ramstage-y += northbridge.c
-romstage-y += raminit.c
-romstage-y += debug.c
-
-endif
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
deleted file mode 100644
index e31106e..0000000
--- a/src/northbridge/intel/e7505/debug.c
+++ /dev/null
@@ -1,184 +0,0 @@
-
-#include <device/pci_def.h>
-#include <console/console.h>
-#include <stdlib.h>
-#include <arch/io.h>
-#include <spd.h>
-
-#include "raminit.h"
-#include "debug.h"
-
-/*
- * generic debug code, used by mainboard specific romstage.c
- *
- */
-
-void print_debug_pci_dev(unsigned dev)
-{
- printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
- (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);
-}
-
-void print_pci_devices(void)
-{
- pci_devfn_t dev;
- for (dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0xff, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- print_debug_pci_dev(dev);
- printk(BIOS_DEBUG, "\n");
- }
-}
-
-void dump_pci_device(unsigned dev)
-{
- int i;
- print_debug_pci_dev(dev);
-
- for (i = 0; i < 256; i++) {
- unsigned char val;
- if ((i & 0x0f) == 0)
- printk(BIOS_DEBUG, "\n%02x:",i);
- val = pci_read_config8(dev, i);
- printk(BIOS_DEBUG, " %02x", val);
- }
- printk(BIOS_DEBUG, "\n");
-}
-
-void dump_pci_devices(void)
-{
- pci_devfn_t dev;
- for (dev = PCI_DEV(0, 0, 0);
- dev <= PCI_DEV(0xff, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- dump_pci_device(dev);
- }
-}
-
-void dump_pci_devices_on_bus(unsigned busn)
-{
- pci_devfn_t dev;
- for (dev = PCI_DEV(busn, 0, 0);
- dev <= PCI_DEV(busn, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- dump_pci_device(dev);
- }
-}
-
-void dump_spd_registers(const struct mem_controller *ctrl)
-{
- int i;
- printk(BIOS_DEBUG, "\n");
- for (i = 0; i < 4; i++) {
- unsigned device;
- device = ctrl->channel0[i];
- if (device) {
- int j;
- printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
- for (j = 0; j < 128; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0)
- printk(BIOS_DEBUG, "\n%02x: ", j);
- status = spd_read_byte(device, j);
- if (status < 0) {
- break;
- }
- byte = status & 0xff;
- printk(BIOS_DEBUG, "%02x ", byte);
- }
- printk(BIOS_DEBUG, "\n");
- }
- device = ctrl->channel1[i];
- if (device) {
- int j;
- printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
- for (j = 0; j < 128; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0)
- printk(BIOS_DEBUG, "\n%02x: ", j);
- status = spd_read_byte(device, j);
- if (status < 0) {
- break;
- }
- byte = status & 0xff;
- printk(BIOS_DEBUG, "%02x ", byte);
- }
- printk(BIOS_DEBUG, "\n");
- }
- }
-}
-void dump_smbus_registers(void)
-{
- unsigned device;
- printk(BIOS_DEBUG, "\n");
- for (device = 1; device < 0x80; device++) {
- int j;
- if ( spd_read_byte(device, 0) < 0 ) continue;
- printk(BIOS_DEBUG, "smbus: %02x", device);
- for (j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- status = spd_read_byte(device, j);
- if (status < 0) {
- break;
- }
- if ((j & 0xf) == 0)
- printk(BIOS_DEBUG, "\n%02x: ",j);
- byte = status & 0xff;
- printk(BIOS_DEBUG, "%02x ", byte);
- }
- printk(BIOS_DEBUG, "\n");
- }
-}
-
-void dump_io_resources(unsigned port)
-{
- int i;
- printk(BIOS_DEBUG, "%04x:\n", port);
- for (i = 0; i < 256; i++) {
- uint8_t val;
- if ((i & 0x0f) == 0)
- printk(BIOS_DEBUG, "%02x:", i);
- val = inb(port);
- printk(BIOS_DEBUG, " %02x",val);
- if ((i & 0x0f) == 0x0f) {
- printk(BIOS_DEBUG, "\n");
- }
- port++;
- }
-}
-
-void dump_mem(unsigned start, unsigned end)
-{
- unsigned i;
- printk(BIOS_DEBUG, "dump_mem:");
- for (i = start; i < end; i++) {
- if ((i & 0xf)==0)
- printk(BIOS_DEBUG, "\n%08x:", i);
- printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
- }
- printk(BIOS_DEBUG, "\n");
-}
diff --git a/src/northbridge/intel/e7505/debug.h b/src/northbridge/intel/e7505/debug.h
deleted file mode 100644
index 2b060e6..0000000
--- a/src/northbridge/intel/e7505/debug.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef E7505_DEBUG_H
-#define E7505_DEBUG_H
-
-void print_debug_pci_dev(unsigned dev);
-void print_pci_devices(void);
-void dump_pci_device(unsigned dev);
-void dump_pci_devices(void);
-void dump_pci_devices_on_bus(unsigned busn);
-void dump_spd_registers(const struct mem_controller *ctrl);
-void dump_smbus_registers(void);
-void dump_io_resources(unsigned port);
-void dump_mem(unsigned start, unsigned end);
-
-#endif
diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h
deleted file mode 100644
index 9c9171d..0000000
--- a/src/northbridge/intel/e7505/e7505.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2005 Digital Design Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * e7505.h: PCI configuration space for the Intel E7501 memory controller
- */
-
-#ifndef NORTHBRIDGE_INTEL_E7505_E7505_H
-#define NORTHBRIDGE_INTEL_E7505_E7505_H
-
-/************ D0:F0 ************/
-// Register offsets
-#define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */
-#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */
-
-#define PAM_0 0x59
-
-#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */
-#define DRB_ROW_1 0x61
-#define DRB_ROW_2 0x62
-#define DRB_ROW_3 0x63
-#define DRB_ROW_4 0x64
-#define DRB_ROW_5 0x65
-#define DRB_ROW_6 0x66
-#define DRB_ROW_7 0x67
-
-#define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */
-#define DRT 0x78 /* DRAM Timing register, 32 bit */
-#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */
-#define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */
-#define CKDIS 0x8C /* Clock disable register, 8 bit */
-#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */
-#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */
-#define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */
-#define SKPD 0xDE /* Scratchpad register, 16 bit */
-#define DVNP 0xE0 /* Device Not Present, 16 bit */
-#define MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */
-
-// CAS# Latency bits in the DRAM Timing (DRT) register
-#define DRT_CAS_2_5 (0<<4)
-#define DRT_CAS_2_0 (1<<4)
-#define DRT_CAS_MASK (3<<4)
-
-// Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register
-#define RAM_COMMAND_NOP (1<<4)
-#define RAM_COMMAND_PRECHARGE (2<<4)
-#define RAM_COMMAND_MRS (3<<4)
-#define RAM_COMMAND_EMRS (4<<4)
-#define RAM_COMMAND_CBR (6<<4)
-#define RAM_COMMAND_NORMAL (7<<4)
-
-#define DRC_DONE (1 << 29)
-
-// RCOMP Memory Map offsets
-// Conjecture based on apparent similarity between E7501 and 855PM
-// Intel doc. 252613-003 describes these for 855PM
-
-#define SMRCTL 0x20 /* System Memory RCOMP Control Register? */
-#define DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */
-#define CKESTR 0x31 /* Strength control for CKE signal group? */
-#define CSBSTR 0x32 /* Strength control for CS# signal group? */
-#define CKSTR 0x33 /* Strength control for CK signal group? */
-#define RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */
-
-/************ D0:F1 ************/
-// Register offsets
-#define FERR_GLOBAL 0x40 /* First global error register, 32 bits */
-#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */
-#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */
-#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */
-
-#endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
deleted file mode 100644
index f6e14d6..0000000
--- a/src/northbridge/intel/e7505/northbridge.c
+++ /dev/null
@@ -1,147 +0,0 @@
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <cpu/cpu.h>
-#include <stdlib.h>
-#include <string.h>
-#include "e7505.h"
-#include <cbmem.h>
-#include <arch/acpi.h>
-
-unsigned long acpi_fill_mcfg(unsigned long current)
-{
- /* Just a dummy */
- return current;
-}
-
-static void pci_domain_set_resources(device_t dev)
-{
- device_t mc_dev;
- uint32_t pci_tolm;
-
- pci_tolm = find_pci_tolm(dev->link_list);
- mc_dev = dev->link_list->children;
- if (mc_dev) {
- /* Figure out which areas are/should be occupied by RAM.
- * This is all computed in kilobytes and converted to/from
- * the memory controller right at the edges.
- * Having different variables in different units is
- * too confusing to get right. Kilobytes are good up to
- * 4 Terabytes of RAM...
- */
- uint16_t tolm_r, remapbase_r, remaplimit_r;
- unsigned long tomk, tolmk;
- unsigned long remapbasek, remaplimitk;
- int idx;
-
- /* Get the value of the highest DRB. This tells the end of
- * the physical memory. The units are ticks of 64MB
- * i.e. 1 means 64MB.
- */
- tomk = ((unsigned long)pci_read_config8(mc_dev, DRB_ROW_7)) << 16;
- /* Compute the top of Low memory */
- tolmk = pci_tolm >> 10;
- if (tolmk >= tomk) {
- /* The PCI hole does not overlap memory
- * we won't use the remap window.
- */
- tolmk = tomk;
- remapbasek = 0x3ff << 16;
- remaplimitk = 0 << 16;
- }
- else {
- /* The PCI memory hole overlaps memory
- * setup the remap window.
- */
- /* Find the bottom of the remap window
- * is it above 4G?
- */
- remapbasek = 4*1024*1024;
- if (tomk > remapbasek) {
- remapbasek = tomk;
- }
- /* Find the limit of the remap window */
- remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
- }
- /* Write the RAM configuration registers,
- * preserving the reserved bits.
- */
- tolm_r = pci_read_config16(mc_dev, TOLM);
- tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
- pci_write_config16(mc_dev, TOLM, tolm_r);
-
- remapbase_r = pci_read_config16(mc_dev, REMAPBASE);
- remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
- pci_write_config16(mc_dev, REMAPBASE, remapbase_r);
-
- remaplimit_r = pci_read_config16(mc_dev, REMAPLIMIT);
- remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
- pci_write_config16(mc_dev, REMAPLIMIT, remaplimit_r);
-
- /* Report the memory regions */
- idx = 10;
- ram_resource(dev, idx++, 0, 640);
- ram_resource(dev, idx++, 768, tolmk - 768);
- if (tomk > 4*1024*1024) {
- ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);
- }
- if (remaplimitk >= remapbasek) {
- ram_resource(dev, idx++, remapbasek,
- (remaplimitk + 64*1024) - remapbasek);
- }
-
- set_late_cbmem_top(tolmk * 1024);
- }
- assign_resources(dev->link_list);
-}
-
-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
-static struct pci_operations intel_pci_ops = {
- .set_subsystem = intel_set_subsystem,
-};
-
-static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
- .ops_pci = &intel_pci_ops,
- .ops_pci_bus = pci_bus_default_ops,
-};
-
-static void cpu_bus_init(device_t dev)
-{
- initialize_cpus(dev->link_list);
-}
-
-static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
-};
-
-static void enable_dev(struct device *dev)
-{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
-}
-
-struct chip_operations northbridge_intel_e7505_ops = {
- CHIP_NAME("Intel E7505 Northbridge")
- .enable_dev = enable_dev,
-};
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
deleted file mode 100644
index b38132a..0000000
--- a/src/northbridge/intel/e7505/raminit.c
+++ /dev/null
@@ -1,1926 +0,0 @@
-/* This was originally for the e7500, modified for e7501
- * The primary differences are that 7501 apparently can
- * support single channel RAM (i haven't tested),
- * CAS1.5 is no longer supported, The ECC scrubber
- * now supports a mode to zero RAM and init ECC in one step
- * and the undocumented registers at 0x80 require new
- * (undocumented) values determined by guesswork and
- * comparison w/ OEM BIOS values.
- * Steven James 02/06/2003
- */
-
-/* converted to C 6/2004 yhlu */
-
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <lib.h>
-#include <stdlib.h>
-#include <console/console.h>
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/cache.h>
-#include <cpu/x86/msr.h>
-#include <assert.h>
-#include <spd.h>
-#include <sdram_mode.h>
-#include <cbmem.h>
-
-#include "raminit.h"
-#include "e7505.h"
-#include "debug.h"
-
-/*-----------------------------------------------------------------------------
-Definitions:
------------------------------------------------------------------------------*/
-
-// Uncomment this to enable run-time checking of DIMM parameters
-// for dual-channel operation
-// Unfortunately the code seems to chew up several K of space.
-//#define VALIDATE_DIMM_COMPATIBILITY
-
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
-#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
-#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
-#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
-#define DUMPNORTH() dump_pci_device(MCHDEV)
-#else
-#define RAM_DEBUG_MESSAGE(x)
-#define RAM_DEBUG_HEX32(x)
-#define RAM_DEBUG_HEX8(x)
-#define DUMPNORTH()
-#endif
-
-#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
-#define SPD_ERROR "Error reading SPD info\n"
-
-#define MCHDEV PCI_DEV(0,0,0)
-#define RASDEV PCI_DEV(0,0,1)
-#define D060DEV PCI_DEV(0,6,0)
-
-// NOTE: This used to be 0x100000.
-// That doesn't work on systems where A20M# is asserted, because
-// attempts to access 0x1000NN end up accessing 0x0000NN.
-#define RCOMP_MMIO ((u8 *)0x200000)
-
-struct dimm_size {
- unsigned long side1;
- unsigned long side2;
-};
-
-static const uint32_t refresh_frequency[] = {
- /* Relative frequency (array value) of each E7501 Refresh Mode Select
- * (RMS) value (array index)
- * 0 == least frequent refresh (longest interval between refreshes)
- * [0] disabled -> 0
- * [1] 15.6 usec -> 2
- * [2] 7.8 usec -> 3
- * [3] 64 usec -> 1
- * [4] reserved -> 0
- * [5] reserved -> 0
- * [6] reserved -> 0
- * [7] 64 clocks -> 4
- */
- 0, 2, 3, 1, 0, 0, 0, 4
-};
-
-static const uint32_t refresh_rate_map[] = {
- /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode
- * Select values (array value)
- * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0
- * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and
- * 64 clock (481 ns) (7) refresh.
- * [0] == 15.625 us -> 15.6 us
- * [1] == 3.9 us -> 481 ns
- * [2] == 7.8 us -> 7.8 us
- * [3] == 31.3 us -> 15.6 us
- * [4] == 62.5 us -> 15.6 us
- * [5] == 125 us -> 64 us
- */
- 1, 7, 2, 1, 1, 3
-};
-
-#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)
-
-#ifdef VALIDATE_DIMM_COMPATIBILITY
-// SPD parameters that must match for dual-channel operation
-static const uint8_t dual_channel_parameters[] = {
- SPD_MEMORY_TYPE,
- SPD_MODULE_VOLTAGE,
- SPD_NUM_COLUMNS,
- SPD_NUM_ROWS,
- SPD_NUM_DIMM_BANKS,
- SPD_PRIMARY_SDRAM_WIDTH,
- SPD_NUM_BANKS_PER_SDRAM
-};
-#endif /* VALIDATE_DIMM_COMPATIBILITY */
-
- /* Comments here are remains of e7501 or even 855PM.
- * They might be partially (in)correct for e7505.
- */
-
- /* (DRAM Read Timing Control, if similar to 855PM?)
- * 0x80 - 0x81 documented differently for e7505
- * This register has something to do with CAS latencies,
- * possibly this is the real chipset control.
- * At 0x00 CAS latency 1.5 works.
- * At 0x06 CAS latency 2.5 works.
- * At 0x01 CAS latency 2.0 works.
- *
- * This is still undocumented in e7501, but with different values
- * CAS 2.0 values taken from Intel BIOS settings, others are a guess
- * and may be terribly wrong. Old values preserved as comments until I
- * figure this out for sure.
- * e7501 docs claim that CAS1.5 is unsupported, so it may or may not
- * work at all.
- * Steven James 02/06/2003
- *
- * NOTE: values now configured in configure_e7501_cas_latency() based
- * on SPD info and total number of DIMMs (per Intel)
- */
-
- /* FDHC - Fixed DRAM Hole Control ???
- * 0x58 undocumented for e7505, memory hole in southbridge configuration?
- * [7:7] Hole_Enable
- * 0 == No memory Hole
- * 1 == Memory Hole from 15MB to 16MB
- * [6:0] Reserved
- */
-
- /* Another Intel undocumented register
- * 0x88 - 0x8B
- * [31:31] Purpose unknown
- * [26:26] Master DLL Reset?
- * 0 == Normal operation?
- * 1 == Reset?
- * [07:07] Periodic memory recalibration?
- * 0 == Disabled?
- * 1 == Enabled?
- * [04:04] Receive FIFO RE-Sync?
- * 0 == Normal operation?
- * 1 == Reset?
- */
-
-/* DDR RECOMP tables */
-// Slew table for 2x drive?
-static const uint32_t slew_2x[] = {
- 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,
- 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,
-};
-
-// Pull Up / Pull Down offset table, if analogous to IXP2800?
-static const uint32_t pull_updown_offset_table[] = {
- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
- 0x88888888, 0x88888888, 0x88888888, 0x88888888,
-};
-
-/*-----------------------------------------------------------------------------
-Delay functions:
------------------------------------------------------------------------------*/
-
-/* Estimate that SLOW_DOWN_IO takes about 1 us */
-#define SLOW_DOWN_IO inb(0x80)
-static void local_udelay(int i)
-{
- while (i--) {
- SLOW_DOWN_IO;
- }
-}
-
-/* delay for 200us */
-#define DO_DELAY local_udelay(200)
-#define EXTRA_DELAY DO_DELAY
-
-/*-----------------------------------------------------------------------------
-Handle (undocumented) control bits MCHTST and PCI_DEV(0,6,0)
------------------------------------------------------------------------------*/
-typedef enum {
- MCHTST_CMD_0,
- D060_ENABLE,
- D060_DISABLE,
- RCOMP_BAR_ENABLE,
- RCOMP_BAR_DISABLE,
-} mchtst_cc;
-
-typedef enum {
- D060_CMD_0,
- D060_CMD_1,
-} d060_cc;
-
-typedef enum {
- RCOMP_HOLD,
- RCOMP_RELEASE,
- RCOMP_SMR_00,
- RCOMP_SMR_01,
-} rcomp_smr_cc;
-
-/**
- * MCHTST - 0xF4 - 0xF7 -- Based on similarity to 855PM
- *
- * [31:31] Purpose unknown
- * [30:30] Purpose unknown
- * [29:23] Unknown - not used?
- * [22:22] System Memory MMR Enable
- * 0 == Disable: mem space and BAR at 0x14 are not accessible
- * 1 == Enable: mem space and BAR at 0x14 are accessible
- * [21:20] Purpose unknown
- * [19:02] Unknown - not used?
- * [01:01] D6EN (Device #6 enable)
- * 0 == Disable
- * 1 == Enable
- * [00:00] Unknown - not used?
- */
-static void mchtest_control(mchtst_cc cmd)
-{
- uint32_t dword = pci_read_config32(MCHDEV, MCHTST);
- switch (cmd) {
- case MCHTST_CMD_0:
- dword &= ~(3 << 30);
- break;
- case RCOMP_BAR_ENABLE:
- dword |= (1 << 22);
- break;
- case RCOMP_BAR_DISABLE:
- dword &= ~(1 << 22);
- break;
- case D060_ENABLE:
- dword |= (1 << 1);
- break;
- case D060_DISABLE:
- dword &= ~(1 << 1);
- break;
- };
- pci_write_config32(MCHDEV, MCHTST, dword);
-}
-
-
-/**
- *
- */
-static void d060_control(d060_cc cmd)
-{
- mchtest_control(D060_ENABLE);
- uint32_t dword = pci_read_config32(D060DEV, 0xf0);
- switch (cmd) {
- case D060_CMD_0:
- dword |= (1 << 2);
- break;
- case D060_CMD_1:
- dword |= (3 << 27);
- break;
- }
- pci_write_config32(D060DEV, 0xf0, dword);
- mchtest_control(D060_DISABLE);
-}
-
-/**
- *
- */
-static void rcomp_smr_control(rcomp_smr_cc cmd)
-{
- uint32_t dword = read32(RCOMP_MMIO + SMRCTL);
- switch (cmd) {
- case RCOMP_HOLD:
- dword |= (1 << 9);
- break;
- case RCOMP_RELEASE:
- dword &= ~((1 << 9) | (3 << 0));
- dword |= (1 << 10) | (1 << 0);
- break;
- case RCOMP_SMR_00:
- dword &= ~(1 << 8);
- break;
- case RCOMP_SMR_01:
- dword |= (1 << 10) | (1 << 8);
- break;
- }
- write32(RCOMP_MMIO + SMRCTL, dword);
-}
-
-/*-----------------------------------------------------------------------------
-Serial presence detect (SPD) functions:
------------------------------------------------------------------------------*/
-
-static void die_on_spd_error(int spd_return_value)
-{
- if (spd_return_value < 0)
- die("Error reading SPD info\n");
-}
-
-/**
- * Calculate the page size for each physical bank of the DIMM:
- * log2(page size) = (# columns) + log2(data width)
- *
- * NOTE: Page size is the total number of data bits in a row.
- *
- * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
- * @return log2(page size) for each side of the DIMM.
- */
-static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)
-{
- uint16_t module_data_width;
- int value;
- struct dimm_size pgsz;
-
- pgsz.side1 = 0;
- pgsz.side2 = 0;
-
- // Side 1
- value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
- if (value < 0)
- goto hw_err;
- pgsz.side1 = value & 0xf; // # columns in bank 1
-
- /* Get the module data width and convert it to a power of two */
- value =
- spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);
- if (value < 0)
- goto hw_err;
- module_data_width = (value & 0xff) << 8;
-
- value =
- spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);
- if (value < 0)
- goto hw_err;
- module_data_width |= (value & 0xff);
-
- pgsz.side1 += log2(module_data_width);
-
- /* side two */
- value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
- if (value < 0)
- goto hw_err;
- if (value > 2)
- die("Bad SPD value\n");
- if (value == 2) {
-
- pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently
- value =
- spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);
- if (value < 0)
- goto hw_err;
- if ((value & 0xf0) != 0) {
- // Asymmetric banks
- pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */
- pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */
- }
- }
-
- return pgsz;
-
- hw_err:
- die(SPD_ERROR);
- return pgsz; // Never reached
-}
-
-/**
- * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16).
- *
- * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
- * @return Width in bits of each DIMM side's DRAMs.
- */
-static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)
-{
- int value;
- struct dimm_size width;
-
- width.side1 = 0;
- width.side2 = 0;
-
- value =
- spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);
- die_on_spd_error(value);
-
- width.side1 = value & 0x7f; // Mask off bank 2 flag
-
- if (value & 0x80) {
- width.side2 = width.side1 << 1; // Bank 2 exists and is double-width
- } else {
- // If bank 2 exists, it's the same width as bank 1
- value =
- spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
- die_on_spd_error(value);
-
-#ifdef ROMCC_IF_BUG_FIXED
- if (value == 2)
- width.side2 = width.side1;
-#else
- switch (value) {
- case 2:
- width.side2 = width.side1;
- break;
-
- default:
- break;
- }
-#endif
- }
-
- return width;
-}
-
-/**
- * Calculate the log base 2 size in bits of both DIMM sides.
- *
- * log2(# bits) = (# columns) + log2(data width) +
- * (# rows) + log2(banks per SDRAM)
- *
- * Note that it might be easier to use SPD byte 31 here, it has the DIMM size
- * as a multiple of 4MB. The way we do it now we can size both sides of an
- * asymmetric DIMM.
- *
- * @param dimm_socket_address SMBus address of DIMM socket to interrogate.
- * @return log2(number of bits) for each side of the DIMM.
- */
-static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)
-{
- int value;
-
- // Start with log2(page size)
- struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);
-
- if (sz.side1 > 0) {
-
- value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS);
- die_on_spd_error(value);
-
- sz.side1 += value & 0xf;
-
- if (sz.side2 > 0) {
-
- // Double-sided DIMM
- if (value & 0xF0)
- sz.side2 += value >> 4; // Asymmetric
- else
- sz.side2 += value; // Symmetric
- }
-
- value =
- spd_read_byte(dimm_socket_address,
- SPD_NUM_BANKS_PER_SDRAM);
- die_on_spd_error(value);
-
- value = log2(value);
- sz.side1 += value;
- if (sz.side2 > 0)
- sz.side2 += value;
- }
-
- return sz;
-}
-
-#ifdef VALIDATE_DIMM_COMPATIBILITY
-
-/**
- * Determine whether two DIMMs have the same value for an SPD parameter.
- *
- * @param spd_byte_number The SPD byte number to compare in both DIMMs.
- * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate.
- * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate.
- * @return 1 if both DIMM sockets report the same value for the specified
- * SPD parameter, 0 if the values differed or an error occurred.
- */
-static uint8_t are_spd_values_equal(uint8_t spd_byte_number,
- uint16_t dimm0_address,
- uint16_t dimm1_address)
-{
- uint8_t bEqual = 0;
- int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);
- int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);
-
- if ((dimm0_value >= 0) && (dimm1_value >= 0)
- && (dimm0_value == dimm1_value))
- bEqual = 1;
-
- return bEqual;
-}
-#endif
-
-/**
- * Scan for compatible DIMMs.
- *
- * The code in this module only supports dual-channel operation, so we test
- * that compatible DIMMs are paired.
- *
- * @param ctrl PCI addresses of memory controller functions, and SMBus
- * addresses of DIMM slots on the mainboard.
- * @return A bitmask indicating which of the possible sockets for each channel
- * was found to contain a compatible DIMM.
- * Bit 0 corresponds to the closest socket for channel 0
- * Bit 1 to the next socket for channel 0
- * ...
- * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0
- * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1
- * ...
- * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1
- */
-static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
-{
- int i;
- uint8_t dimm_mask = 0;
-
- // Have to increase size of dimm_mask if this assertion is violated
- ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);
-
- // Find DIMMs we can support on channel 0.
- // Then see if the corresponding channel 1 DIMM has the same parameters,
- // since we only support dual-channel.
-
- for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
- uint16_t channel0_dimm = ctrl->channel0[i];
- uint16_t channel1_dimm = ctrl->channel1[i];
- uint8_t bDualChannel = 1;
-#ifdef VALIDATE_DIMM_COMPATIBILITY
- struct dimm_size page_size;
- struct dimm_size sdram_width;
-#endif
- int spd_value;
-
- if (channel0_dimm == 0)
- continue; // No such socket on this mainboard
-
- if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) !=
- SPD_MEMORY_TYPE_SDRAM_DDR)
- continue;
-
-#ifdef VALIDATE_DIMM_COMPATIBILITY
- if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) !=
- SPD_VOLTAGE_SSTL2)
- continue; // Unsupported voltage
-
- // E7501 does not support unregistered DIMMs
- spd_value =
- spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);
- if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))
- continue;
-
- // Must support burst = 4 for dual-channel operation on E7501
- // NOTE: for single-channel, burst = 8 is required
- spd_value =
- spd_read_byte(channel0_dimm,
- SPD_SUPPORTED_BURST_LENGTHS);
- if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
- continue;
-
- page_size = sdram_spd_get_page_size(channel0_dimm);
- sdram_width = sdram_spd_get_width(channel0_dimm);
-
- // Validate DIMM page size
- // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel
- // NOTE: 4 KB = 32 Kb = 2^15
- // 32 KB = 262 Kb = 2^18
-
- if ((page_size.side1 < 15) || (page_size.side1 > 18))
- continue;
-
- // If DIMM is double-sided, verify side2 page size
- if (page_size.side2 != 0) {
- if ((page_size.side2 < 15)
- || (page_size.side2 > 18))
- continue;
- }
- // Validate SDRAM width
- // The E7501 only supports x4 and x8 devices
-
- if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))
- continue;
-
- // If DIMM is double-sided, verify side2 width
- if (sdram_width.side2 != 0) {
- if ((sdram_width.side2 != 4)
- && (sdram_width.side2 != 8))
- continue;
- }
-#endif
- // Channel 0 DIMM looks compatible.
- // Now see if it is paired with the proper DIMM on channel 1.
-
- ASSERT(channel1_dimm != 0); // No such socket on this mainboard??
-
- // NOTE: unpopulated DIMMs cause read to fail
- spd_value =
- spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
- if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
-
- printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
- continue;
- }
-#ifdef VALIDATE_DIMM_COMPATIBILITY
- spd_value =
- spd_read_byte(channel1_dimm,
- SPD_SUPPORTED_BURST_LENGTHS);
- if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))
- continue;
-
- int j;
- for (j = 0; j < sizeof(dual_channel_parameters); ++j) {
- if (!are_spd_values_equal
- (dual_channel_parameters[j], channel0_dimm,
- channel1_dimm)) {
-
- bDualChannel = 0;
- break;
- }
- }
-#endif /* VALIDATE_DIMM_COMPATIBILITY */
-
- // Code around ROMCC bug in optimization of "if" statements
-#ifdef ROMCC_IF_BUG_FIXED
- if (bDualChannel) {
- // Made it through all the checks, this DIMM pair is usable
- dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
- } else
- printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
-#else
- switch (bDualChannel) {
- case 0:
- printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
- break;
-
- default:
- // Made it through all the checks, this DIMM pair is usable
- dimm_mask |= (1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i));
- break;
- }
-#endif
- }
-
- return dimm_mask;
-}
-
-/*-----------------------------------------------------------------------------
-SDRAM configuration functions:
------------------------------------------------------------------------------*/
-
-/**
- * Send the specified command to all DIMMs.
- *
- * @param command Specifies the command to be sent to the DIMMs.
- * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the
- * register value in JEDEC format.
- */
-static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
-{
- uint8_t dimm_start_64M_multiple;
- uintptr_t dimm_start_address;
- uint32_t dram_controller_mode;
- uint8_t i;
-
- // Configure the RAM command
- dram_controller_mode = pci_read_config32(MCHDEV, DRC);
- dram_controller_mode &= 0xFFFFFF8F;
- dram_controller_mode |= command;
- pci_write_config32(MCHDEV, DRC, dram_controller_mode);
-
- // RAM_COMMAND_NORMAL is an exception.
- // It affects only the memory controller and does not need to be "sent" to the DIMMs.
- if (command == RAM_COMMAND_NORMAL) {
- EXTRA_DELAY;
- return;
- }
-
- // NOTE: for mode select commands, some of the location address bits are part of the command
- // Map JEDEC mode bits to E7505
- if (command == RAM_COMMAND_MRS) {
- // Host address lines [25:18] map to DIMM address lines [7:0]
- // Host address lines [17:16] map to DIMM address lines [9:8]
- // Host address lines [15:4] map to DIMM address lines [11:0]
- dimm_start_address = (jedec_mode_bits & 0x00ff) << 18;
- dimm_start_address |= (jedec_mode_bits & 0x0300) << 8;
- dimm_start_address |= (jedec_mode_bits & 0x0fff) << 4;
- } else if (command == RAM_COMMAND_EMRS) {
- // Host address lines [15:4] map to DIMM address lines [11:0]
- dimm_start_address = (jedec_mode_bits << 4);
- } else {
- ASSERT(jedec_mode_bits == 0);
- dimm_start_address = 0;
- }
-
- // Send the command to all DIMMs by accessing a memory location within each
-
- dimm_start_64M_multiple = 0;
-
- /* FIXME: Only address the number of rows present in the system?
- * Seems like rows 4-7 overlap with 0-3.
- */
- for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {
-
- uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i);
-
- if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
- dimm_start_address &= 0x3ffffff;
- dimm_start_address |= dimm_start_64M_multiple << 26;
- read32((void *)dimm_start_address);
- // Set the start of the next DIMM
- dimm_start_64M_multiple = dimm_end_64M_multiple;
- }
- }
- EXTRA_DELAY;
-}
-
-/**
- * Set the mode register of all DIMMs.
- *
- * The proper CAS# latency setting is added to the mode bits specified
- * by the caller.
- *
- * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the
- * register value in JEDEC format.
- */
-static void set_ram_mode(uint16_t jedec_mode_bits)
-{
- ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));
-
- uint32_t dram_cas_latency =
- pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK;
-
- switch (dram_cas_latency) {
- case DRT_CAS_2_5:
- jedec_mode_bits |= SDRAM_CAS_2_5;
- break;
-
- case DRT_CAS_2_0:
- jedec_mode_bits |= SDRAM_CAS_2_0;
- break;
-
- default:
- BUG();
- break;
- }
-
- do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);
-}
-
-/*-----------------------------------------------------------------------------
-DIMM-independent configuration functions:
------------------------------------------------------------------------------*/
-
-/**
- * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory
- * present in the specified DIMM.
- *
- * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of
- * the DIMM.
- * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of
- * 64 MB) for DIMMs < dimm_index.
- * @param dimm_index Which DIMM pair is being processed
- * (0..MAX_DIMM_SOCKETS_PER_CHANNEL).
- * @return New multiple of 64 MB total DRAM in the system.
- */
-static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index)
-{
- int i;
-
- ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);
-
- // DIMM sides must be at least 32 MB
- ASSERT(dimm_log2_num_bits.side1 >= 28);
- ASSERT((dimm_log2_num_bits.side2 == 0)
- || (dimm_log2_num_bits.side2 >= 28));
-
- // In dual-channel mode, we are called only once for each pair of DIMMs.
- // Each time we process twice the capacity of a single DIMM.
-
- // Convert single DIMM capacity to paired DIMM capacity
- // (multiply by two ==> add 1 to log2)
- dimm_log2_num_bits.side1++;
- if (dimm_log2_num_bits.side2 > 0)
- dimm_log2_num_bits.side2++;
-
- // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)
- // to the total capacity of the system
- // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29
-
- total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));
-
- // Configure the boundary address for the row on side 1
- pci_write_config8(MCHDEV, DRB_ROW_0 + (dimm_index << 1),
- total_dram_64M_multiple);
-
- // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair
- // (as a multiple of 64 MB) to the total capacity of the system
- if (dimm_log2_num_bits.side2 >= 29)
- total_dram_64M_multiple +=
- (1 << (dimm_log2_num_bits.side2 - 29));
-
- // Configure the boundary address for the row (if any) on side 2
- pci_write_config8(MCHDEV, DRB_ROW_1 + (dimm_index << 1),
- total_dram_64M_multiple);
-
- // Update boundaries for rows subsequent to these.
- // These settings will be overridden by a subsequent call if a populated physical slot exists
-
- for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
- pci_write_config8(MCHDEV, DRB_ROW_0 + (i << 1),
- total_dram_64M_multiple);
- pci_write_config8(MCHDEV, DRB_ROW_1 + (i << 1),
- total_dram_64M_multiple);
- }
-
- return total_dram_64M_multiple;
-}
-
-/**
- * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM).
- *
- * If necessary, set up a remap window so we don't waste DRAM that ordinarily
- * would lie behind addresses reserved for memory-mapped I/O.
- *
- * @param ctrl PCI addresses of memory controller functions, and SMBus
- * addresses of DIMM slots on the mainboard.
- * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
- */
-static void configure_e7501_ram_addresses(const struct mem_controller
- *ctrl, uint8_t dimm_mask)
-{
- int i;
- uint8_t total_dram_64M_multiple = 0;
-
- // Configure the E7501's DRAM row boundaries
- // Start by zeroing out the temporary initial configuration
- pci_write_config32(MCHDEV, DRB_ROW_0, 0);
- pci_write_config32(MCHDEV, DRB_ROW_4, 0);
-
- for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
- uint16_t dimm_socket_address = ctrl->channel0[i];
- struct dimm_size sz;
-
- if (!(dimm_mask & (1 << i)))
- continue; // This DIMM not present
-
- sz = spd_get_dimm_size(dimm_socket_address);
-
- RAM_DEBUG_MESSAGE("dimm size =");
- RAM_DEBUG_HEX32((u32)sz.side1);
- RAM_DEBUG_MESSAGE(" ");
- RAM_DEBUG_HEX32((u32)sz.side2);
- RAM_DEBUG_MESSAGE("\n");
-
- if (sz.side1 == 0)
- die("Bad SPD value\n");
-
- total_dram_64M_multiple =
- configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);
- }
-
- // Configure the Top Of Low Memory (TOLM) in the E7501
- // This address must be a multiple of 128 MB that is less than 4 GB.
- // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address
- // in the highest 5 bits.
-
- // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system.
- // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes
- // such as flash and memory-mapped I/O.
-
- // If there is more than 3 GB of DRAM, we define a remap window which
- // makes the DRAM "behind" the reserved region available above the top of physical
- // memory.
-
- // NOTE: 0xC0000000 / (64 MB) == 0x30
-
- if (total_dram_64M_multiple <= 0x30) {
-
- // <= 3 GB total RAM
-
- /* I should really adjust all of this in C after I have resources
- * to all of the pci devices.
- */
-
- // Round up to 128MB granularity
- // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?
-
- uint8_t total_dram_128M_multiple =
- (total_dram_64M_multiple + 1) >> 1;
-
- // Convert to high 16 bits of address
- uint16_t top_of_low_memory =
- total_dram_128M_multiple << 11;
-
- pci_write_config16(MCHDEV, TOLM,
- top_of_low_memory);
-
- } else {
-
- // > 3 GB total RAM
-
- // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory
- uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0
- uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF
-
- // Put TOLM at 3 GB
-
- pci_write_config16(MCHDEV, TOLM, 0xc000);
-
- // Define a remap window to make the RAM that would appear from 3 GB - 4 GB
- // visible just beyond 4 GB or the end of physical memory, whichever is larger
- // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address,
- // (i.e. a multiple of 64 MB) in the lowest 10 bits.
- // NOTE: 0x100000000 / (64 MB) == 0x40
-
- if (total_dram_64M_multiple < 0x40) {
- remap_base = 0x40; // 0x100000000
- remap_limit =
- 0x40 + (total_dram_64M_multiple - 0x30) - 1;
- }
-
- pci_write_config16(MCHDEV, REMAPBASE,
- remap_base);
- pci_write_config16(MCHDEV, REMAPLIMIT,
- remap_limit);
- }
-}
-
-/**
- * Execute ECC full-speed scrub once and leave scrubber disabled.
- *
- * NOTE: All cache and stack is lost during ECC scrub loop.
- */
-static inline void __attribute__((always_inline))
- initialize_ecc(unsigned long ret_addr, unsigned long ret_addr2)
-{
- uint16_t scrubbed = pci_read_config16(MCHDEV, MCHCFGNS) & 0x08;
-
- if (!scrubbed) {
- RAM_DEBUG_MESSAGE("Initializing ECC state...\n");
-
- /* ECC scrub flushes cache-lines and stack, need to
- * store return address from romstage.c:main().
- */
- asm volatile(
- "movd %0, %%xmm0;"
- "movd (%0), %%xmm1;"
- "movd %1, %%xmm2;"
- "movd (%1), %%xmm3;"
- :: "r" (ret_addr), "r" (ret_addr2) :
- );
-
- /* NOTE: All cache is lost during this loop.
- * Make sure PCI access does not use stack.
- */
-
- pci_write_config16(MCHDEV, MCHCFGNS, 0x01);
- do {
- scrubbed = pci_read_config16(MCHDEV, MCHCFGNS);
- } while (! (scrubbed & 0x08));
- pci_write_config16(MCHDEV, MCHCFGNS, (scrubbed & ~0x07) | 0x04);
-
- /* Some problem remains with XIP cache from ROM, so for
- * now, I disable XIP and also invalidate cache (again)
- * before the remaining small portion of romstage.
- *
- * Adding NOPs here has unexpected results, making
- * the first do_printk()/vtxprintf() after ECC scrub
- * fail midway. Sometimes vtxprintf() dumps strings
- * completely but with every 4th (fourth) character as "/".
- *
- * An inlined dump to console of the same string,
- * before vtxprintf() call, is successful. So the
- * source string should be completely in cache already.
- *
- * I need to review this again with CPU microcode
- * update applied pre-CAR.
- */
-
- /* Disable and invalidate all cache. */
- msr_t xip_mtrr = rdmsr(MTRR_PHYS_MASK(1));
- xip_mtrr.lo &= ~MTRR_PHYS_MASK_VALID;
- invd();
- wrmsr(MTRR_PHYS_MASK(1), xip_mtrr);
- invd();
-
- RAM_DEBUG_MESSAGE("ECC state initialized.\n");
-
- /* Recover IP for return from main. */
- asm volatile(
- "movd %%xmm0, %%edi;"
- "movd %%xmm1, (%%edi);"
- "movd %%xmm2, %%edi;"
- "movd %%xmm3, (%%edi);"
- ::: "edi"
- );
-
-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)
- unsigned int a1, a2;
- asm volatile("movd %%xmm2, %%eax;" : "=a" (a1) ::);
- asm volatile("movd %%xmm3, %%eax;" : "=a" (a2) ::);
- printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2);
- asm volatile("movd %%xmm0, %%eax;" : "=a" (a1) ::);
- asm volatile("movd %%xmm1, %%eax;" : "=a" (a2) ::);
- printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2);
-#endif
- }
-
- /* Clear the ECC error bits. */
- pci_write_config8(RASDEV, DRAM_FERR, 0x03);
- pci_write_config8(RASDEV, DRAM_NERR, 0x03);
-
- /* Clear DRAM Interface error bits. */
- pci_write_config32(RASDEV, FERR_GLOBAL, 1 << 18);
- pci_write_config32(RASDEV, NERR_GLOBAL, 1 << 18);
-}
-
-/**
- * Program the DRAM Timing register (DRT) of the E7501 (except for CAS#
- * latency, which is assumed to have been programmed already), based on the
- * parameters of the various installed DIMMs.
- *
- * @param ctrl PCI addresses of memory controller functions, and SMBus
- * addresses of DIMM slots on the mainboard.
- * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
- */
-static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
- uint8_t dimm_mask)
-{
- int i;
- uint32_t dram_timing;
- int value;
- uint8_t slowest_row_precharge = 0;
- uint8_t slowest_ras_cas_delay = 0;
- uint8_t slowest_active_to_precharge_delay = 0;
- uint32_t current_cas_latency =
- pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK;
-
- // CAS# latency must be programmed beforehand
- ASSERT((current_cas_latency == DRT_CAS_2_0)
- || (current_cas_latency == DRT_CAS_2_5));
-
- // Each timing parameter is determined by the slowest DIMM
-
- for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
- uint16_t dimm_socket_address;
-
- if (!(dimm_mask & (1 << i)))
- continue; // This DIMM not present
-
- if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
- dimm_socket_address = ctrl->channel0[i];
- else
- dimm_socket_address =
- ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
-
- value =
- spd_read_byte(dimm_socket_address,
- SPD_MIN_ROW_PRECHARGE_TIME);
- if (value < 0)
- goto hw_err;
- if (value > slowest_row_precharge)
- slowest_row_precharge = value;
-
- value =
- spd_read_byte(dimm_socket_address,
- SPD_MIN_RAS_TO_CAS_DELAY);
- if (value < 0)
- goto hw_err;
- if (value > slowest_ras_cas_delay)
- slowest_ras_cas_delay = value;
-
- value =
- spd_read_byte(dimm_socket_address,
- SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);
- if (value < 0)
- goto hw_err;
- if (value > slowest_active_to_precharge_delay)
- slowest_active_to_precharge_delay = value;
- }
-
- // NOTE for timing parameters:
- // At 133 MHz, 1 clock == 7.52 ns
-
- /* Read the initial state */
- dram_timing = pci_read_config32(MCHDEV, DRT);
-
- /* Trp */
-
- // E7501 supports only 2 or 3 clocks for tRP
- if (slowest_row_precharge > ((22 << 2) | (2 << 0)))
- die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks
- else if (slowest_row_precharge > (15 << 2))
- dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks
- else
- dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks
-
- /* Trcd */
-
- // E7501 supports only 2 or 3 clocks for tRCD
- // Use the same value for both read & write
- dram_timing &= ~((1 << 3) | (3 << 1));
- if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))
- die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks
- else if (slowest_ras_cas_delay > (15 << 2))
- dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks
- else
- dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks
-
- /* Tras */
-
- // E7501 supports only 5, 6, or 7 clocks for tRAS
- // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns
- dram_timing &= ~(3 << 9);
-
- if (slowest_active_to_precharge_delay > 52)
- die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks
- else if (slowest_active_to_precharge_delay > 45)
- dram_timing |= (0 << 9); // 46-52 ns: 7 clocks
- else if (slowest_active_to_precharge_delay > 37)
- dram_timing |= (1 << 9); // 38-45 ns: 6 clocks
- else
- dram_timing |= (2 << 9); // < 38 ns: 5 clocks
-
- /* Trd */
-
- /* Set to a 7 clock read delay. This is for 133MHz
- * with a CAS latency of 2.5 if 2.0 a 6 clock
- * delay is good */
-
- dram_timing &= ~(7 << 24); // 7 clocks
- if (current_cas_latency == DRT_CAS_2_0)
- dram_timing |= (1 << 24); // 6 clocks
-
- /*
- * Back to Back Read-Write Turn Around
- */
- /* Set to a 5 clock back to back read to write turn around.
- * 4 is a good delay if the CAS latency is 2.0 */
-
- dram_timing &= ~(1 << 28); // 5 clocks
- if (current_cas_latency == DRT_CAS_2_0)
- dram_timing |= (1 << 28); // 4 clocks
-
- pci_write_config32(MCHDEV, DRT, dram_timing);
-
- return;
-
- hw_err:
- die(SPD_ERROR);
-}
-
-/**
- * Determine the shortest CAS# latency that the E7501 and all DIMMs have in
- * common, and program the E7501 to use it.
- *
- * @param ctrl PCI addresses of memory controller functions, and SMBus
- * addresses of DIMM slots on the mainboard.
- * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
- */
-static void configure_e7501_cas_latency(const struct mem_controller *ctrl,
- uint8_t dimm_mask)
-{
- int i;
- int value;
- uint32_t dram_timing;
- uint16_t dram_read_timing;
- uint32_t dword;
-
- // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format
- // NOTE: E7501 supports only 2.0 and 2.5
- uint32_t system_compatible_cas_latencies =
- SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;
- uint32_t current_cas_latency;
- uint32_t dimm_compatible_cas_latencies;
-
- for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
-
- uint16_t dimm_socket_address;
-
- if (!(dimm_mask & (1 << i)))
- continue; // This DIMM not usable
-
- if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
- dimm_socket_address = ctrl->channel0[i];
- else
- dimm_socket_address =
- ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
-
- value =
- spd_read_byte(dimm_socket_address,
- SPD_ACCEPTABLE_CAS_LATENCIES);
- if (value < 0)
- goto hw_err;
-
- dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM
- current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM
-
- // Can we support the highest CAS# latency?
-
- value =
- spd_read_byte(dimm_socket_address,
- SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
- if (value < 0)
- goto hw_err;
-
- // NOTE: At 133 MHz, 1 clock == 7.52 ns
- if (value > 0x75) {
- // Our bus is too fast for this CAS# latency
- // Remove it from the bitmask of those supported by the DIMM that are compatible
- dimm_compatible_cas_latencies &= ~current_cas_latency;
- }
- // Can we support the next-highest CAS# latency (max - 0.5)?
-
- current_cas_latency >>= 1;
- if (current_cas_latency != 0) {
- value =
- spd_read_byte(dimm_socket_address,
- SPD_SDRAM_CYCLE_TIME_2ND);
- if (value < 0)
- goto hw_err;
- if (value > 0x75)
- dimm_compatible_cas_latencies &=
- ~current_cas_latency;
- }
- // Can we support the next-highest CAS# latency (max - 1.0)?
- current_cas_latency >>= 1;
- if (current_cas_latency != 0) {
- value =
- spd_read_byte(dimm_socket_address,
- SPD_SDRAM_CYCLE_TIME_3RD);
- if (value < 0)
- goto hw_err;
- if (value > 0x75)
- dimm_compatible_cas_latencies &=
- ~current_cas_latency;
- }
- // Restrict the system to CAS# latencies compatible with this DIMM
- system_compatible_cas_latencies &=
- dimm_compatible_cas_latencies;
-
- /* go to the next DIMM */
- }
-
- /* After all of the arduous calculation setup with the fastest
- * cas latency I can use.
- */
-
- dram_timing = pci_read_config32(MCHDEV, DRT);
- dram_timing &= ~(DRT_CAS_MASK);
-
- dram_read_timing =
- pci_read_config16(MCHDEV, DRDCTL);
- dram_read_timing &= 0xF000;
-
- if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {
- dram_timing |= DRT_CAS_2_0;
- dram_read_timing |= 0x0222;
- } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {
-
- uint32_t dram_row_attributes =
- pci_read_config32(MCHDEV, DRA);
-
- dram_timing |= DRT_CAS_2_5;
-
- // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly
- // different value if all DIMM slots are populated
-
- if ((dram_row_attributes & 0xff)
- && (dram_row_attributes & 0xff00)
- && (dram_row_attributes & 0xff0000)
- && (dram_row_attributes & 0xff000000)) {
-
- // All slots populated
- dram_read_timing |= 0x0882;
- } else {
- // Some unpopulated slots
- dram_read_timing |= 0x0662;
- }
- } else
- die("No CAS# latencies compatible with all DIMMs!!\n");
-
- pci_write_config32(MCHDEV, DRT, dram_timing);
-
- /* set master DLL reset */
- dword = pci_read_config32(MCHDEV, 0x88);
- dword |= (1 << 26);
- pci_write_config32(MCHDEV, 0x88, dword);
- /* patch try register 88 is undocumented tnz */
- dword &= 0x0ca17fff;
- dword |= 0xd14a5000;
- pci_write_config32(MCHDEV, 0x88, dword);
-
- pci_write_config16(MCHDEV, DRDCTL,
- dram_read_timing);
-
- /* clear master DLL reset */
- dword = pci_read_config32(MCHDEV, 0x88);
- dword &= ~(1 << 26);
- pci_write_config32(MCHDEV, 0x88, dword);
-
- return;
-
-hw_err:
- die(SPD_ERROR);
-}
-
-/**
- * Configure the refresh interval so that we refresh no more often than
- * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs
- * don't support it.
- *
- * @param ctrl PCI addresses of memory controller functions, and SMBus
- * addresses of DIMM slots on the mainboard.
- * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
- */
-static void configure_e7501_dram_controller_mode(const struct
- mem_controller *ctrl,
- uint8_t dimm_mask)
-{
- int i;
-
- // Initial settings
- uint32_t controller_mode =
- pci_read_config32(MCHDEV, DRC);
- uint32_t system_refresh_mode = (controller_mode >> 8) & 7;
-
- // Code below assumes that most aggressive settings are in
- // force when we are called, either via E7501 reset defaults
- // or by sdram_set_registers():
- // - ECC enabled
- // - No refresh
-
- ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC
- ASSERT(!(controller_mode & (7 << 8))); // Refresh
-
- /* Walk through _all_ dimms and find the least-common denominator for:
- * - ECC support
- * - refresh rates
- */
-
- for (i = 0; i < MAX_DIMM_SOCKETS; i++) {
-
- uint32_t dimm_refresh_mode;
- int value;
- uint16_t dimm_socket_address;
-
- if (!(dimm_mask & (1 << i))) {
- continue; // This DIMM not usable
- }
-
- if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)
- dimm_socket_address = ctrl->channel0[i];
- else
- dimm_socket_address =
- ctrl->channel1[i -
- MAX_DIMM_SOCKETS_PER_CHANNEL];
-
- // Disable ECC mode if any one of the DIMMs does not support ECC
- // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
-
- value =
- spd_read_byte(dimm_socket_address,
- SPD_DIMM_CONFIG_TYPE);
- die_on_spd_error(value);
- if (value != ERROR_SCHEME_ECC) {
- controller_mode &= ~(3 << 20);
- }
-
- value = spd_read_byte(dimm_socket_address, SPD_REFRESH);
- die_on_spd_error(value);
- value &= 0x7f; // Mask off self-refresh bit
- if (value > MAX_SPD_REFRESH_RATE) {
- printk(BIOS_ERR, "unsupported refresh rate\n");
- continue;
- }
- // Get the appropriate E7501 refresh mode for this DIMM
- dimm_refresh_mode = refresh_rate_map[value];
- if (dimm_refresh_mode > 7) {
- printk(BIOS_ERR, "unsupported refresh rate\n");
- continue;
- }
- // If this DIMM requires more frequent refresh than others,
- // update the system setting
- if (refresh_frequency[dimm_refresh_mode] >
- refresh_frequency[system_refresh_mode])
- system_refresh_mode = dimm_refresh_mode;
-
-#ifdef SUSPICIOUS_LOOKING_CODE
-// SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller
-// than the clock period of the memory controller. Also, no other northbridge
-// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.
-
- // Switch to 2 clocks for address/command if required by any one of the DIMMs
- // NOTE: At 133 MHz, 1 clock == 7.52 ns
- value =
- spd_read_byte(dimm_socket_address,
- SPD_CMD_SIGNAL_INPUT_HOLD_TIME);
- die_on_spd_error(value);
- if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */
- controller_mode &= ~(1 << 16); /* Use two clock cycles instead of one */
- }
-#endif
-
- /* go to the next DIMM */
- }
-
- controller_mode |= (system_refresh_mode << 8);
-
- // Configure the E7501
- pci_write_config32(MCHDEV, DRC, controller_mode);
-}
-
-/**
- * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM
- * parameters read via SPD. This tells the controller the width of the SDRAM
- * chips on each DIMM side (x4 or x8) and the page size of each DIMM side
- * (4, 8, 16, or 32 KB).
- *
- * @param ctrl PCI addresses of memory controller functions, and SMBus
- * addresses of DIMM slots on the mainboard.
- * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().
- */
-static void configure_e7501_row_attributes(const struct mem_controller
- *ctrl, uint8_t dimm_mask)
-{
- int i;
- uint32_t row_attributes = 0;
-
- for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
- uint16_t dimm_socket_address = ctrl->channel0[i];
- struct dimm_size page_size;
- struct dimm_size sdram_width;
-
- if (!(dimm_mask & (1 << i)))
- continue; // This DIMM not usable
-
- // Get the relevant parameters via SPD
- page_size = sdram_spd_get_page_size(dimm_socket_address);
- sdram_width = sdram_spd_get_width(dimm_socket_address);
-
- // Update the DRAM Row Attributes.
- // Page size is encoded as log2(page size in bits) - log2(8 Kb)
- // NOTE: 8 Kb = 2^13
- row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row
-
- if (sdram_width.side2 > 0)
- row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD
-
- // Set x4 flags if appropriate
- if (sdram_width.side1 == 4) {
- row_attributes |= 0x08 << (i << 3);
- }
-
- if (sdram_width.side2 == 4) {
- row_attributes |= 0x08 << ((i << 3) + 4);
- }
-
- /* go to the next DIMM */
- }
-
- /* Write the new row attributes register */
- pci_write_config32(MCHDEV, DRA, row_attributes);
-}
-
-/*
- * Enable clock signals for populated DIMM sockets and disable them for
- * unpopulated sockets (to reduce EMI).
- *
- * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().
- */
-static void enable_e7501_clocks(uint8_t dimm_mask)
-{
- int i;
- uint8_t clock_disable = pci_read_config8(MCHDEV, CKDIS);
-
- pci_write_config8(MCHDEV, 0x8e, 0xb0);
-
- for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {
-
- uint8_t socket_mask = 1 << i;
-
- if (dimm_mask & socket_mask)
- clock_disable &= ~socket_mask; // DIMM present, enable clock
- else
- clock_disable |= socket_mask; // DIMM absent, disable clock
- }
-
- pci_write_config8(MCHDEV, CKDIS, clock_disable);
-}
-
-/* DIMM-dependent configuration functions */
-
-/**
- * DDR Receive FIFO RE-Sync (?)
- */
-static void RAM_RESET_DDR_PTR(void)
-{
- uint8_t byte;
- byte = pci_read_config8(MCHDEV, 0x88);
- byte |= (1 << 4);
- pci_write_config8(MCHDEV, 0x88, byte);
-
- byte = pci_read_config8(MCHDEV, 0x88);
- byte &= ~(1 << 4);
- pci_write_config8(MCHDEV, 0x88, byte);
-}
-
-/**
- * Copy 64 bytes from one location to another.
- *
- * @param src_addr TODO
- * @param dst_addr TODO
- */
-static void write_8dwords(const uint32_t *src_addr, u8 *dst_addr)
-{
- int i;
- for (i = 0; i < 8; i++) {
- write32(dst_addr, *src_addr);
- src_addr++;
- dst_addr += sizeof(uint32_t);
- }
-}
-
-/**
- * Set the E7501's (undocumented) RCOMP registers.
- *
- * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual,
- * RCOMP registers appear to affect drive strength, pullup/pulldown offset,
- * and slew rate of various signal groups.
- *
- * Comments below are conjecture based on apparent similarity between the
- * E7501 and these two chips.
- */
-static void rcomp_copy_registers(void)
-{
- uint32_t dword;
- uint8_t strength_control;
-
- RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
-
- /* Begin to write the RCOMP registers */
- write8(RCOMP_MMIO + 0x2c, 0x0);
-
- // Set CMD and DQ/DQS strength to 2x (?)
- strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0x88;
- strength_control |= 0x40;
- write8(RCOMP_MMIO + DQCMDSTR, strength_control);
- write_8dwords(slew_2x, RCOMP_MMIO + 0x80);
- write16(RCOMP_MMIO + 0x42, 0);
-
- // Set CMD and DQ/DQS strength to 2x (?)
- strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0xF8;
- strength_control |= 0x04;
- write8(RCOMP_MMIO + DQCMDSTR, strength_control);
- write_8dwords(slew_2x, RCOMP_MMIO + 0x60);
- write16(RCOMP_MMIO + 0x40, 0);
-
- // Set RCVEnOut# strength to 2x (?)
- strength_control = read8(RCOMP_MMIO + RCVENSTR) & 0xF8;
- strength_control |= 0x04;
- write8(RCOMP_MMIO + RCVENSTR, strength_control);
- write_8dwords(slew_2x, RCOMP_MMIO + 0x1c0);
- write16(RCOMP_MMIO + 0x50, 0);
-
- // Set CS# strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x88;
- strength_control |= 0x04;
- write8(RCOMP_MMIO + CSBSTR, strength_control);
- write_8dwords(slew_2x, RCOMP_MMIO + 0x140);
- write16(RCOMP_MMIO + 0x48, 0);
-
- // Set CS# strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x8F;
- strength_control |= 0x40;
- write8(RCOMP_MMIO + CSBSTR, strength_control);
- write_8dwords(slew_2x, RCOMP_MMIO + 0x160);
- write16(RCOMP_MMIO + 0x4a, 0);
-
- // Set CKE strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CKESTR) & 0x88;
- strength_control |= 0x04;
- write8(RCOMP_MMIO + CKESTR, strength_control);
- write_8dwords(slew_2x, RCOMP_MMIO + 0xa0);
- write16(RCOMP_MMIO + 0x44, 0);
-
- // Set CKE strength for x4 SDRAM to 2x (?)
- strength_control = read8(RCOMP_MMIO + CKESTR) & 0x8F;
- strength_control |= 0x40;
- write8(RCOMP_MMIO + CKESTR, strength_control);
- write_8dwords(slew_2x, RCOMP_MMIO + 0xc0);
- write16(RCOMP_MMIO + 0x46, 0);
-
- // Set CK strength for x4 SDRAM to 1x (?)
- strength_control = read8(RCOMP_MMIO + CKSTR) & 0x88;
- strength_control |= 0x01;
- write8(RCOMP_MMIO + CKSTR, strength_control);
- write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x180);
- write16(RCOMP_MMIO + 0x4c, 0);
-
- // Set CK strength for x4 SDRAM to 1x (?)
- strength_control = read8(RCOMP_MMIO + CKSTR) & 0x8F;
- strength_control |= 0x10;
- write8(RCOMP_MMIO + CKSTR, strength_control);
- write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x1a0);
- write16(RCOMP_MMIO + 0x4e, 0);
-
- dword = read32(RCOMP_MMIO + 0x400);
- dword &= 0x7f7fffff;
- write32(RCOMP_MMIO + 0x400, dword);
-
- dword = read32(RCOMP_MMIO + 0x408);
- dword &= 0x7f7fffff;
- write32(RCOMP_MMIO + 0x408, dword);
-}
-
-static void ram_set_rcomp_regs(void)
-{
- /* Set the RCOMP MMIO base address */
- mchtest_control(RCOMP_BAR_ENABLE);
- pci_write_config32(MCHDEV, SMRBASE, (uintptr_t)RCOMP_MMIO);
-
- /* Block RCOMP updates while we configure the registers */
- rcomp_smr_control(RCOMP_HOLD);
- rcomp_copy_registers();
- d060_control(D060_CMD_0);
- mchtest_control(MCHTST_CMD_0);
-
- uint8_t revision = pci_read_config8(MCHDEV, 0x08);
- if (revision >= 3) {
- rcomp_smr_control(RCOMP_SMR_00);
- rcomp_smr_control(RCOMP_SMR_01);
- }
- rcomp_smr_control(RCOMP_RELEASE);
-
- /* Wait 40 usec */
- SLOW_DOWN_IO;
-
- /* Clear the RCOMP MMIO base address */
- pci_write_config32(MCHDEV, SMRBASE, 0);
- mchtest_control(RCOMP_BAR_DISABLE);
-}
-
-/*-----------------------------------------------------------------------------
-Public interface:
------------------------------------------------------------------------------*/
-
-/**
- * Go through the JEDEC initialization sequence for all DIMMs, then enable
- * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up
- * and running.
- *
- * @param ctrl PCI addresses of memory controller functions, and SMBus
- * addresses of DIMM slots on the mainboard.
- */
-static void sdram_enable(const struct mem_controller *ctrl)
-{
- uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD);
- uint32_t dram_controller_mode;
-
- if (dimm_mask == 0)
- return;
-
- /* 1 & 2 Power up and start clocks */
- RAM_DEBUG_MESSAGE("Ram Enable 1\n");
- RAM_DEBUG_MESSAGE("Ram Enable 2\n");
-
- /* A 200us delay is needed */
- DO_DELAY; EXTRA_DELAY;
-
- /* 3. Apply NOP */
- RAM_DEBUG_MESSAGE("Ram Enable 3\n");
- do_ram_command(RAM_COMMAND_NOP, 0);
-
- /* 4 Precharge all */
- RAM_DEBUG_MESSAGE("Ram Enable 4\n");
- do_ram_command(RAM_COMMAND_PRECHARGE, 0);
- /* wait until the all banks idle state... */
-
- /* 5. Issue EMRS to enable DLL */
- RAM_DEBUG_MESSAGE("Ram Enable 5\n");
- do_ram_command(RAM_COMMAND_EMRS,
- SDRAM_EXTMODE_DLL_ENABLE |
- SDRAM_EXTMODE_DRIVE_NORMAL);
-
- /* 6. Reset DLL */
- RAM_DEBUG_MESSAGE("Ram Enable 6\n");
- set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
- EXTRA_DELAY;
- /* Ensure a 200us delay between the DLL reset in step 6 and the final
- * mode register set in step 9.
- * Infineon needs this before any other command is sent to the ram.
- */
- DO_DELAY; EXTRA_DELAY;
-
- /* 7 Precharge all */
- RAM_DEBUG_MESSAGE("Ram Enable 7\n");
- do_ram_command(RAM_COMMAND_PRECHARGE, 0);
-
- /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
- /* And for good luck 6 more CBRs */
- RAM_DEBUG_MESSAGE("Ram Enable 8\n");
- int i;
- for (i = 0; i < 8; i++)
- do_ram_command(RAM_COMMAND_CBR, 0);
-
- /* 9 mode register set */
- RAM_DEBUG_MESSAGE("Ram Enable 9\n");
- set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
-
- /* 10 DDR Receive FIFO RE-Sync */
- RAM_DEBUG_MESSAGE("Ram Enable 10\n");
- RAM_RESET_DDR_PTR();
- EXTRA_DELAY;
-
- /* 11 normal operation */
- RAM_DEBUG_MESSAGE("Ram Enable 11\n");
- do_ram_command(RAM_COMMAND_NORMAL, 0);
-
- // Reconfigure the row boundaries and Top of Low Memory
- // to match the true size of the DIMMs
- configure_e7501_ram_addresses(ctrl, dimm_mask);
-
- /* Finally enable refresh */
- dram_controller_mode = pci_read_config32(MCHDEV, DRC);
- dram_controller_mode |= (1 << 29);
- pci_write_config32(MCHDEV, DRC, dram_controller_mode);
- EXTRA_DELAY;
-}
-
-/**
- * @param ctrl PCI addresses of memory controller functions, and SMBus
- * addresses of DIMM slots on the mainboard.
- */
-static void sdram_post_ecc(const struct mem_controller *ctrl)
-{
- /* Fast CS# Enable. */
- uint32_t dram_controller_mode = pci_read_config32(MCHDEV, DRC);
- dram_controller_mode = pci_read_config32(MCHDEV, DRC);
- dram_controller_mode |= (1 << 17);
- pci_write_config32(MCHDEV, DRC, dram_controller_mode);
-}
-
-/**
- * Configure SDRAM controller parameters that depend on characteristics of the
- * DIMMs installed in the system. These characteristics are read from the
- * DIMMs via the standard Serial Presence Detect (SPD) interface.
- *
- * @param ctrl PCI addresses of memory controller functions, and SMBus
- * addresses of DIMM slots on the mainboard.
- */
-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
-{
- uint8_t dimm_mask;
-
- RAM_DEBUG_MESSAGE("Reading SPD data...\n");
-
- dimm_mask = spd_get_supported_dimms(ctrl);
-
- if (dimm_mask == 0) {
- printk(BIOS_DEBUG, "No usable memory for this controller\n");
- } else {
- enable_e7501_clocks(dimm_mask);
-
- RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
-
- configure_e7501_row_attributes(ctrl, dimm_mask);
- configure_e7501_dram_controller_mode(ctrl, dimm_mask);
- configure_e7501_cas_latency(ctrl, dimm_mask);
- RAM_RESET_DDR_PTR();
-
- configure_e7501_dram_timing(ctrl, dimm_mask);
- DO_DELAY;
- RAM_DEBUG_MESSAGE("done\n");
- }
-
- /* NOTE: configure_e7501_ram_addresses() is NOT called here.
- * We want to keep the default 64 MB/row mapping until sdram_enable() is called,
- * even though the default mapping is almost certainly incorrect.
- * The default mapping makes it easy to initialize all of the DIMMs
- * even if the total system memory is > 4 GB.
- *
- * Save the dimm_mask for when sdram_enable is called, so it can call
- * configure_e7501_ram_addresses() without having to regenerate the bitmask
- * of usable DIMMs.
- */
- pci_write_config16(MCHDEV, SKPD, dimm_mask);
-}
-
-/**
- * Do basic RAM setup that does NOT depend on serial presence detect
- * information (i.e. independent of DIMM specifics).
- *
- * @param ctrl PCI addresses of memory controller functions, and SMBus
- * addresses of DIMM slots on the mainboard.
- */
-static void sdram_set_registers(const struct mem_controller *ctrl)
-{
- uint32_t dword;
- uint16_t word;
- uint8_t byte;
-
- ram_set_rcomp_regs();
-
- /* Enable 0:0.1, 0:2.1 */
- word = pci_read_config16(MCHDEV, DVNP);
- word &= ~0x05;
- pci_write_config16(MCHDEV, DVNP, word);
-
- /* Disable high-memory remap (power-on defaults, really) */
- pci_write_config16(MCHDEV, REMAPBASE, 0x03ff);
- pci_write_config16(MCHDEV, REMAPLIMIT, 0x0);
-
- /* Disable legacy MMIO (0xC0000-0xEFFFF is DRAM) */
- int i;
- pci_write_config8(MCHDEV, PAM_0, 0x30);
- for (i = 1; i <= 6; i++)
- pci_write_config8(MCHDEV, PAM_0 + i, 0x33);
-
- /* Conservatively say each row has 64MB of ram, we will fix this up later
- * Initial TOLM 8 rows 64MB each (1<<3 * 1<<26) >> 16 = 1<<13
- *
- * FIXME: Hard-coded limit to first four rows to prevent overlap!
- */
- pci_write_config32(MCHDEV, DRB_ROW_0, 0x04030201);
- pci_write_config32(MCHDEV, DRB_ROW_4, 0x04040404);
- //pci_write_config32(MCHDEV, DRB_ROW_4, 0x08070605);
- pci_write_config16(MCHDEV, TOLM, (1<<13));
-
- /* DIMM clocks off */
- pci_write_config8(MCHDEV, CKDIS, 0xff);
-
- /* reset row attributes */
- pci_write_config32(MCHDEV, DRA, 0x0);
-
- // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and
- // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.
- dword = pci_read_config32(MCHDEV, DRT);
- dword &= 0xC7F8FFFF;
- dword |= (0x28<<24)|(0x03<<16);
- pci_write_config32(MCHDEV, DRT, dword);
-
- dword = pci_read_config32(MCHDEV, DRC);
- dword &= 0xffcef8f7;
- dword |= 0x00210008;
- pci_write_config32(MCHDEV, DRC, dword);
-
- /* Undocumented */
- pci_write_config8(MCHDEV, 0x88, 0x80);
-
- /* Undocumented. Set much later in vendor BIOS. */
- byte = pci_read_config8(MCHDEV, 0xd9);
- byte &= ~0x60;
- pci_write_config8(MCHDEV, 0xd9, byte);
-
-#ifdef SUSPICIOUS_LOOKING_CODE
- /* This will access D2:F0:0x50, is this correct??
- * Vendor BIOS reads Device ID before this is set.
- * Undocumented in the p64h2 PCI-X bridge datasheet.
- */
- byte = pci_read_config8(PCI_DEV(0,2,0), 0x50);
- byte &= 0xcf;
- byte |= 0x30
- pci_write_config8(PCI_DEV(0,2,0), 0x50, byte);
-#endif
-
- uint8_t revision = pci_read_config8(MCHDEV, 0x08);
- if (revision >= 3)
- d060_control(D060_CMD_1);
-}
-
-/**
- *
- *
- */
-void e7505_mch_init(const struct mem_controller *memctrl)
-{
- RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
- DUMPNORTH();
-
- sdram_set_registers(memctrl);
- sdram_set_spd_registers(memctrl);
- sdram_enable(memctrl);
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
- u32 tolm = (pci_read_config16(MCHDEV, TOLM) & ~0x7ff) << 16;
- return tolm;
-}
-
-/**
- * Scrub and reset error counts for ECC dimms.
- *
- * NOTE: this will invalidate cache and disable XIP cache for the
- * short remaining part of romstage.
- */
-void e7505_mch_scrub_ecc(unsigned long ret_addr)
-{
- unsigned long ret_addr2 = (unsigned long)((unsigned long*)&ret_addr-1);
- if ((pci_read_config32(MCHDEV, DRC)>>20 & 3) == 2)
- initialize_ecc(ret_addr, ret_addr2);
-}
-
-void e7505_mch_done(const struct mem_controller *memctrl)
-{
- sdram_post_ecc(memctrl);
-
- RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
- DUMPNORTH();
-}
-
-int e7505_mch_is_ready(void)
-{
- uint32_t dword = pci_read_config32(MCHDEV, DRC);
- return !!(dword & DRC_DONE);
-}
diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h
deleted file mode 100644
index 979ae0a..0000000
--- a/src/northbridge/intel/e7505/raminit.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef RAMINIT_H
-#define RAMINIT_H
-
-#define MAX_DIMM_SOCKETS_PER_CHANNEL 4
-#define MAX_NUM_CHANNELS 2
-#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)
-
-struct mem_controller {
- pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller
-
- // SMBus addresses of DIMM slots for each channel,
- // in order from closest to MCH to furthest away
- // 0 == not present
- uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL];
- uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];
-};
-
-void e7505_mch_init(const struct mem_controller *memctrl);
-void e7505_mch_scrub_ecc(unsigned long ret_addr);
-void e7505_mch_done(const struct mem_controller *memctrl);
-int e7505_mch_is_ready(void);
-
-
-/* Mainboard exports this. */
-int spd_read_byte(unsigned device, unsigned address);
-
-#endif /* RAMINIT_H */
diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h
deleted file mode 100644
index b576cc1..0000000
--- a/src/southbridge/intel/i82870/82870.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* for io apic 1461 */
-#define MBAR 0x10
-#define ABAR 0x40
-
-/* for pci bridge 1460 */
-#define MTT 0x042
-#define HCCR 0x0f0
-#define ACNF 0x0e0
-#define STRP 0x44 // Strap status register
-
-#define STRP_EN133 0x0001 // 133 MHz-capable (Px_133EN)
-#define STRP_HPCAP 0x0002 // Hot-plug capable (Hx_SLOT zero/nonzero)
-
-#define ACNF_SYNCPH 0x0010 // PCI(-X) input clock is synchronous to hub input clock
diff --git a/src/southbridge/intel/i82870/Kconfig b/src/southbridge/intel/i82870/Kconfig
deleted file mode 100644
index b56113b..0000000
--- a/src/southbridge/intel/i82870/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-config SOUTHBRIDGE_INTEL_I82870
- bool
diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc
deleted file mode 100644
index 790bd01..0000000
--- a/src/southbridge/intel/i82870/Makefile.inc
+++ /dev/null
@@ -1,7 +0,0 @@
-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y)
-
-ramstage-y += ioapic.c
-ramstage-y += pcibridge.c
-#ramstage-y += pci_parity.c
-
-endif
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
deleted file mode 100644
index da7da5e..0000000
--- a/src/southbridge/intel/i82870/ioapic.c
+++ /dev/null
@@ -1,97 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include <assert.h>
-#include "82870.h"
-
-static int num_p64h2_ioapics = 0;
-
-static void p64h2_ioapic_enable(device_t dev)
-{
- /* We have to enable MEM and Bus Master for IOAPIC */
- uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-
- pci_write_config16(dev, PCI_COMMAND, command);
-}
-
-/**
- * Configure one of the IOAPICs in a P64H2.
- *
- * Note that a PCI bus scan will detect both IOAPICs, so this function
- * will be called twice for each P64H2 in the system.
- *
- * @param dev PCI bus/device/function of P64H2 IOAPIC.
- * NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.
- */
-static void p64h2_ioapic_init(device_t dev)
-{
- uint32_t memoryBase;
- int apic_index, apic_id;
-
- volatile uint32_t* pIndexRegister; /* io apic io memory space command address */
- volatile uint32_t* pWindowRegister; /* io apic io memory space data address */
-
- apic_index = num_p64h2_ioapics;
- num_p64h2_ioapics++;
-
- // A note on IOAPIC addresses:
- // 0 and 1 are used for the local APICs of the dual virtual
- // (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
- // 6 and 7 are used for the local APICs of the dual virtual
- // (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
- // 2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
-
- // Map APIC index into APIC ID
- // IDs 3, 4, 5, and 8+ are available (see above note)
-
- if (apic_index < 3)
- apic_id = apic_index + 3;
- else
- apic_id = apic_index + 5;
-
- ASSERT(apic_id < 16); // ID is only 4 bits
-
- // Read the MBAR address for setting up the IOAPIC in memory space
- // NOTE: this address was assigned during enumeration of the bus
-
- memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- pIndexRegister = (volatile uint32_t*) memoryBase;
- pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
-
- printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n",
- apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
- PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
-
- apic_id <<= 24; // Convert ID to bitmask
-
- *pIndexRegister = 0; // Select APIC ID register
- *pWindowRegister = (*pWindowRegister & ~(0x0f << 24)) | apic_id; // Set the ID
-
- if ((*pWindowRegister & (0x0f << 24)) != apic_id)
- die("p64h2_ioapic_init failed");
-
- *pIndexRegister = 3; // Select Boot Configuration register
- *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts
-
- if (!(*pWindowRegister & 1))
- die("p64h2_ioapic_init failed");
-}
-
-static struct device_operations ioapic_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = p64h2_ioapic_init,
- .scan_bus = 0,
- .enable = p64h2_ioapic_enable,
-};
-
-static const struct pci_driver ioapic_driver __pci_driver = {
- .ops = &ioapic_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82870_1E0,
-
-};
diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c
deleted file mode 100644
index b886c52..0000000
--- a/src/southbridge/intel/i82870/pci_parity.c
+++ /dev/null
@@ -1,23 +0,0 @@
-#include <pci.h>
-#include <arch/io.h>
-#include <printk.h>
-#
-
-void p64h2_pci_parity_enable(void)
-{
- uint8_t reg;
-
- /* 2SERREN - SERR enable for PCI bridge secondary device */
- /* 2PEREN - Parity error for PCI bridge secondary device */
- pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®);
- reg |= ((1 << 1) + (1 << 0));
- pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
-
- /* 2SERREN - SERR enable for PCI bridge secondary device */
- /* 2PEREN - Parity error for PCI bridge secondary device */
- pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®);
- reg |= ((1 << 1) + (1 << 0));
- pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
-
- return;
-}
diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
deleted file mode 100644
index e8d890a..0000000
--- a/src/southbridge/intel/i82870/pcibridge.c
+++ /dev/null
@@ -1,38 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <pc80/mc146818rtc.h>
-#include "82870.h"
-
-static void p64h2_pcix_init(device_t dev)
-{
- u32 dword;
- u8 byte;
-
- /* The purpose of changes to HCCR, ACNF, and MTT is to speed
- * up the PCI bus for cards having high speed transfers.
- */
- dword = 0xc2040002;
- pci_write_config32(dev, HCCR, dword);
- dword = 0x0000c3bf;
- pci_write_config32(dev, ACNF, dword);
- byte = 0x08;
- pci_write_config8(dev, MTT, byte);
-
-}
-static struct device_operations pcix_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = p64h2_pcix_init,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
-};
-
-static const struct pci_driver pcix_driver __pci_driver = {
- .ops = &pcix_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82870_1F0,
-};
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib6c8b3942b66bf43f7e1a42edf24cad32120c61d
Gerrit-Change-Number: 22028
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
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