<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/22028">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Intel e7505 board & chips: Remove - using LATE_CBMEM_INIT<br><br>All boards and chips that are still using LATE_CBMEM_INIT are being<br>removed as previously discussed.<br><br>If these boards and chips are updated to not use LATE_CBMEM_INIT, they<br>can be restored to the active codebase from the 4.8 branch.<br><br>chips:<br>cpu/intel/socket_mPGA604<br>northbridge/intel/e7505<br>southbridge/intel/i82870<br><br>Mainboards:<br>mainboard/aopen/dxplplusu<br><br>Change-Id: Ib6c8b3942b66bf43f7e1a42edf24cad32120c61d<br>Signed-off-by: Martin Roth <gaumless@gmail.com><br>---<br>D src/cpu/intel/socket_mPGA604/Kconfig<br>D src/mainboard/aopen/dxplplusu/Kconfig<br>D src/mainboard/aopen/dxplplusu/Kconfig.name<br>D src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl<br>D src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl<br>D src/mainboard/aopen/dxplplusu/acpi/i82801db.asl<br>D src/mainboard/aopen/dxplplusu/acpi/p64h2.asl<br>D src/mainboard/aopen/dxplplusu/acpi/power.asl<br>D src/mainboard/aopen/dxplplusu/acpi/scsi.asl<br>D src/mainboard/aopen/dxplplusu/acpi/superio.asl<br>D src/mainboard/aopen/dxplplusu/acpi_tables.c<br>D src/mainboard/aopen/dxplplusu/board_info.txt<br>D src/mainboard/aopen/dxplplusu/bus.h<br>D src/mainboard/aopen/dxplplusu/devicetree.cb<br>D src/mainboard/aopen/dxplplusu/dsdt.asl<br>D src/mainboard/aopen/dxplplusu/fadt.c<br>D src/mainboard/aopen/dxplplusu/irq_tables.c<br>D src/mainboard/aopen/dxplplusu/romstage.c<br>D src/northbridge/intel/e7505/Kconfig<br>D src/northbridge/intel/e7505/Makefile.inc<br>D src/northbridge/intel/e7505/debug.c<br>D src/northbridge/intel/e7505/debug.h<br>D src/northbridge/intel/e7505/e7505.h<br>D src/northbridge/intel/e7505/northbridge.c<br>D src/northbridge/intel/e7505/raminit.c<br>D src/northbridge/intel/e7505/raminit.h<br>D src/southbridge/intel/i82870/82870.h<br>D src/southbridge/intel/i82870/Kconfig<br>D src/southbridge/intel/i82870/Makefile.inc<br>D src/southbridge/intel/i82870/ioapic.c<br>D src/southbridge/intel/i82870/pci_parity.c<br>D src/southbridge/intel/i82870/pcibridge.c<br>32 files changed, 0 insertions(+), 4,028 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/22028/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig<br>deleted file mode 100644<br>index 94d6a09..0000000<br>--- a/src/cpu/intel/socket_mPGA604/Kconfig<br>+++ /dev/null<br>@@ -1,31 +0,0 @@<br>-config CPU_INTEL_SOCKET_MPGA604<br>- bool<br>-<br>-if CPU_INTEL_SOCKET_MPGA604<br>-<br>-config SOCKET_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_MODEL_F2X<br>- select CPU_INTEL_MODEL_F3X<br>- select CPU_INTEL_MODEL_F4X<br>- select MMX<br>- select SSE<br>- select UDELAY_TSC<br>- select SIPI_VECTOR_IN_ROM<br>-<br>-# mPGA604 are usually Intel Netburst CPUs which should have SSE2<br>-# but the ramtest.c code on the Dell S1850 seems to choke on<br>-# enabling it, so disable it for now.<br>-config SSE2<br>- bool<br>- default n<br>-<br>-config DCACHE_RAM_BASE<br>- hex<br>- default 0xfefc0000<br>-<br>-config DCACHE_RAM_SIZE<br>- hex<br>- default 0x4000<br>-<br>-endif # CPU_INTEL_SOCKET_MPGA604<br>diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig<br>deleted file mode 100644<br>index 0823161..0000000<br>--- a/src/mainboard/aopen/dxplplusu/Kconfig<br>+++ /dev/null<br>@@ -1,41 +0,0 @@<br>-if BOARD_AOPEN_DXPLPLUSU<br>-<br>-config BOARD_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select CPU_INTEL_SOCKET_MPGA604<br>- select NORTHBRIDGE_INTEL_E7505<br>- select SOUTHBRIDGE_INTEL_I82870<br>- select SOUTHBRIDGE_INTEL_I82801DX<br>- select SUPERIO_SMSC_LPC47M10X<br>-# select HAVE_PIRQ_TABLE<br>-# select PIRQ_ROUTE<br>- select UDELAY_TSC<br>- select HAVE_ACPI_TABLES<br>- select BOARD_ROMSIZE_KB_2048<br>-# select HW_SCRUBBER<br>-<br>-config MAINBOARD_DIR<br>- string<br>- default aopen/dxplplusu<br>-<br>-config MAINBOARD_PART_NUMBER<br>- string<br>- default "DXPL Plus-U"<br>-<br>-config IRQ_SLOT_COUNT<br>- int<br>- default 12<br>-<br>-config MAX_CPUS<br>- int<br>- default 4<br>-<br>-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID<br>- hex<br>- default 0x0<br>-<br>-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID<br>- hex<br>- default 0x0<br>-<br>-endif # BOARD_AOPEN_DXPLPLUSU<br>diff --git a/src/mainboard/aopen/dxplplusu/Kconfig.name b/src/mainboard/aopen/dxplplusu/Kconfig.name<br>deleted file mode 100644<br>index 1310203..0000000<br>--- a/src/mainboard/aopen/dxplplusu/Kconfig.name<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config BOARD_AOPEN_DXPLPLUSU<br>- bool "DXPL Plus-U"<br>diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl<br>deleted file mode 100644<br>index 566704b..0000000<br>--- a/src/mainboard/aopen/dxplplusu/acpi/e7505_pri.asl<br>+++ /dev/null<br>@@ -1,81 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-Device (MBRS)<br>-{<br>- Name (_HID, EisaId ("PNP0C01"))<br>- Name (_UID, 0x01)<br>- Name (MSBF, ResourceTemplate ()<br>- {<br>- /* System memory */<br>- QWordMemory (ResourceProducer, PosDecode, MinFixed,<br>- MaxNotFixed, Prefetchable, ReadWrite,<br>- 0x0, 0x100000000, 0x400000000, 0x0, 0x0, ,, _Y1C,<br>- AddressRangeMemory, TypeStatic)<br>-<br>- /* Top Of Low Memory */<br>- Memory32 (ReadOnly, 0x0, 0x0, 0x1, 0x0, _Y1D)<br>-<br>- /* 640kB who wants more? */<br>- Memory32Fixed (ReadWrite, 0x0, 0xA0000, )<br>-<br>- /* 64k BIOS bootblock */<br>- Memory32Fixed (ReadOnly, 0xF0000, 0x10000,)<br>-<br>- /* ISA memory hole 15-16 MB ? */<br>- /* Memory32Fixed (ReadOnly, 0x100000, 0xF00000,) */<br>- /* ISA memory hole 14-15 MB ? */<br>- /* Memory32Fixed (ReadOnly, 0x100000, 0xE00000,) */<br>-<br>- /* Local APIC */<br>- Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000,)<br>- })<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- CreateQWordField (MSBF, \_SB.MBRS._Y1C._MIN, MEML)<br>- CreateQWordField (MSBF, \_SB.MBRS._Y1C._MAX, MEMM)<br>- CreateQWordField (MSBF, \_SB.MBRS._Y1C._LEN, LELM)<br>-<br>- And (\_SB.PCI0.RLAR, 0x03FF, Local1)<br>- Increment (Local1)<br>- If (LGreater (Local1, 0x40))<br>- {<br>- ShiftLeft (Local1, 0x1A, LELM)<br>- }<br>-<br>-<br>- CreateDWordField (MSBF, \_SB.MBRS._Y1D._MIN, MS00)<br>- CreateDWordField (MSBF, \_SB.MBRS._Y1D._MAX, MS01)<br>- CreateDWordField (MSBF, \_SB.MBRS._Y1D._LEN, MEM2)<br>- And (\_SB.PCI0.TOLM, 0xF800, Local1)<br>- ShiftRight (Local1, 0x04, Local1)<br>- Decrement (Local1)<br>- If (LGreater (Local1, 0x10))<br>- {<br>- Subtract (Local1, 0x0F, Local1)<br>- Store (ShiftLeft (Local1, 0x14), MEM2)<br>- Store (0x01000000, MS00)<br>- Store (MS00, MS01)<br>- }<br>-<br>- Return (MSBF)<br>- }<br>-<br>- Method (_STA, 0, NotSerialized)<br>- {<br>- Return (0x0F)<br>- }<br>-}<br>diff --git a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl b/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl<br>deleted file mode 100644<br>index 6ae2750..0000000<br>--- a/src/mainboard/aopen/dxplplusu/acpi/e7505_sec.asl<br>+++ /dev/null<br>@@ -1,67 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-Name (PBRS, ResourceTemplate ()<br>-{<br>- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,<br>- 0x0000, 0x0000, 0x00FF, 0x0000, 0x0100, ,, )<br>-<br>- /* System IO */<br>- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,<br>- 0x0, 0x0, 0xffff, 0x0000, 0x10000, ,,, TypeStatic)<br>- IO (Decode16, 0x0CF8, 0x0CF8, 0x08, 0x08, )<br>-<br>- /* Video RAM */<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,<br>- 0x00000000, 0x000A0000, 0x000BFFFF,<br>- 0x00000000, 0x00020000, ,,, AddressRangeMemory, TypeStatic)<br>-<br>- /* Video ROM */<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,<br>- 0x00000000, 0x000C0000, 0x000C7FFF,<br>- 0x00000000, 0x00008000, ,,, AddressRangeMemory, TypeStatic)<br>-<br>- /* Option ROMs ? */<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,<br>- 0x00000000, 0x000C8000, 0x000DFFFF,<br>- 0x00000000, 0x00018000, ,,, AddressRangeMemory, TypeStatic)<br>-<br>- /* Top Of Lowmemory to IOAPIC */<br>- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,<br>- 0x00000000, 0x00000000, 0xFEBFFFFF,<br>- 0x00000000, IO_APIC_ADDR, ,, _Y08, AddressRangeMemory, TypeStatic)<br>-})<br>-<br>-<br>-Method (_CRS, 0, NotSerialized)<br>-{<br>-<br>- /* Top Of Lowmemory to IOAPIC */<br>- CreateDWordField (PBRS, \_SB.PCI0._Y08._MIN, MEML)<br>- CreateDWordField (PBRS, \_SB.PCI0._Y08._MAX, MEMH)<br>- CreateDWordField (PBRS, \_SB.PCI0._Y08._LEN, LENM)<br>- And (\_SB.PCI0.TOLM, 0xF800, Local1)<br>- ShiftRight (Local1, 0x04, Local1)<br>- ShiftLeft (Local1, 0x14, MEML)<br>- Subtract (IO_APIC_ADDR, 0x01, MEMH)<br>- Subtract (IO_APIC_ADDR, MEML, LENM)<br>-<br>- Return (PBRS)<br>-}<br>-<br>-Method (_STA, 0, NotSerialized)<br>-{<br>- Return (0x0F)<br>-}<br>diff --git a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl b/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl<br>deleted file mode 100644<br>index 633007d..0000000<br>--- a/src/mainboard/aopen/dxplplusu/acpi/i82801db.asl<br>+++ /dev/null<br>@@ -1,164 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-Device (USB0)<br>-{<br>- Name (_ADR, 0x001D0000)<br>- Name (_PRW, Package () { 0x03, 0x05 })<br>-<br>- OperationRegion (USBS, PCI_Config, 0x00, 0x0100)<br>- Field (USBS, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0xC4), URES, 8<br>- }<br>-}<br>-<br>-Device (USB1)<br>-{<br>- Name (_ADR, 0x001D0001)<br>- Name (_PRW, Package () { 0x04, 0x05 })<br>- OperationRegion (USBS, PCI_Config, 0x00, 0x0100)<br>- Field (USBS, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0xC4), URES, 8<br>- }<br>-}<br>-<br>-Device (USB2)<br>-{<br>- Name (_ADR, 0x001D0002)<br>- Name (_PRW, Package () { 0x0C, 0x05 })<br>- OperationRegion (USBS, PCI_Config, 0x00, 0x0100)<br>- Field (USBS, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0xC4), URES, 8<br>- }<br>-}<br>-<br>-Device (USB3)<br>-{<br>- Name (_ADR, 0x001D0007)<br>- Name (_PRW, Package () { 0x0D, 0x05 }) /* PME_B0_STS any 0:1d or 0:1f device */<br>- OperationRegion (USBS, PCI_Config, 0x00, 0x0100)<br>- Field (USBS, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0xC4), URES, 8<br>- }<br>-}<br>-<br>-Device(PCI5)<br>-{<br>- Name (_ADR, 0x001E0000)<br>- Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */<br>- Name (_PRT, Package() {<br>- Package() { 0x0003ffff, 0, 0, 20 },<br>- Package() { 0x0003ffff, 1, 0, 21 },<br>- Package() { 0x0003ffff, 2, 0, 22 },<br>- Package() { 0x0003ffff, 3, 0, 23 },<br>- })<br>-}<br>-<br>-Device (ICH0)<br>-{<br>- Name (_ADR, 0x001F0000)<br>- OperationRegion (D310, PCI_Config, 0x00, 0xFF)<br>- Field (D310, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0x40), PBAR, 16,<br>- Offset (0x58), GBAR, 16,<br>- }<br>-<br>- OperationRegion (ACPI, SystemIO, 0x0400, 0xC0)<br>- Field (ACPI, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0x00), PS1L,8, PS1H,8, PE1L,8, PE1H,8,<br>- Offset (0x28), GS0L,8, GS0H,8, GSPL,8, GSPH,8,<br>- Offset (0x2C), GE0L,8, GE0H,8, GEPL,8, GEPH,8,<br>- Offset (0xB8), GPLV,8<br>- }<br>-<br>- Name (MSBF, ResourceTemplate ()<br>- {<br>- /* IOAPIC 0 */<br>- Memory32Fixed (ReadWrite, IO_APIC_ADDR, 0x00001000,)<br>-<br>- IO (Decode16, 0x0, 0x0, 0x80, 0x0, PMIO)<br>- IO (Decode16, 0x0, 0x0, 0x40, 0x0, GPIO)<br>-<br>- /* 8254 legacy irq */<br>- IO (Decode16, 0x04D0, 0x04D0, 0x02, 0x02,)<br>-<br>- /* reset generator */<br>- IO (Decode16, 0x0092, 0x0092, 0x01, 0x01, )<br>- })<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MIN, IOA1)<br>- CreateWordField (MSBF, \_SB_.PCI0.ICH0.PMIO._MAX, IOA2)<br>- CreateByteField (MSBF, \_SB_.PCI0.ICH0.PMIO._LEN, IOAL)<br>-<br>- Store (PBAR, Local0)<br>- If ( Land(Local0, 0x01) )<br>- {<br>- And (Local0, 0xFFFE, Local0)<br>- Store (Local0, IOA1)<br>- Store (Local0, IOA2)<br>- Store (0x80, IOAL)<br>- } Else {<br>- Store (0x00, IOAL)<br>- }<br>-<br>- CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MIN, IOS1)<br>- CreateWordField (MSBF, \_SB_.PCI0.ICH0.GPIO._MAX, IOS2)<br>- CreateByteField (MSBF, \_SB_.PCI0.ICH0.GPIO._LEN, IOSL)<br>-<br>- Store (GBAR, Local0)<br>- If ( Land(Local0, 0x01) ) {<br>- And (Local0, 0xFFFE, Local0)<br>- Store (Local0, IOS1)<br>- Store (Local0, IOS2)<br>- Store (0x40, IOSL)<br>- } Else {<br>- Store (0x00, IOSL)<br>- }<br>- Return (MSBF)<br>- }<br>-<br>- Device (FWH)<br>- {<br>- Name (_HID, EisaId ("PNP0C02"))<br>- Name (_UID, 0x01)<br>-<br>-<br>- Name (MSBG, ResourceTemplate () {<br>- Memory32Fixed (ReadOnly, 0xFFF00000, 0x00080000,)<br>- Memory32Fixed (ReadOnly, 0xFFF80000, 0x00080000,)<br>- })<br>-<br>- Method (_CRS, 0, NotSerialized)<br>- {<br>- Return (MSBG)<br>- }<br>- }<br>-<br>- Device (SMSC)<br>- {<br>- Name (_HID, EisaId ("PNP0C02"))<br>- Name (_UID, 0x02)<br>- #include "acpi/superio.asl"<br>- }<br>-<br>-}<br>diff --git a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl b/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl<br>deleted file mode 100644<br>index e3f2e5f..0000000<br>--- a/src/mainboard/aopen/dxplplusu/acpi/p64h2.asl<br>+++ /dev/null<br>@@ -1,91 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* Interrupt routing for PCI 03:xx.x */<br>-<br>-/* I/O APIC id 0x3 */<br>-Device(PBIO)<br>-{<br>- Name (_HID, "ACPI000A")<br>- Name (_ADR, 0x001c0000)<br>-}<br>-<br>-/* PCI-X bridge */<br>-Device(P64B)<br>-{<br>- Name (_ADR, 0x001d0000)<br>- Name (_PRT, Package() {<br>- Package() { 0x0002ffff, 0, 0, 24 }, /* PCI-X slot 1 */<br>- Package() { 0x0002ffff, 1, 0, 25 },<br>- Package() { 0x0002ffff, 2, 0, 26 },<br>- Package() { 0x0002ffff, 3, 0, 27 },<br>- Package() { 0x0003ffff, 0, 0, 28 }, /* PCI-X slot 2 */<br>- Package() { 0x0003ffff, 1, 0, 29 },<br>- Package() { 0x0003ffff, 2, 0, 30 },<br>- Package() { 0x0003ffff, 3, 0, 31 },<br>- Package() { 0x0004ffff, 0, 0, 32 }, /* On-board GbE */<br>- })<br>-<br>- Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */<br>- OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)<br>- Field (PBPC, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0x3E), BCRL, 8, BCRH, 8<br>- }<br>-<br>-<br>- Device (ETH0)<br>- {<br>- Name (_ADR, 0x00040000)<br>- Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */<br>- }<br>-}<br>-<br>-<br>-/* Interrupt routing for PCI 04:xx.x */<br>-<br>-/* I/O APIC id 0x4 */<br>-Device(PAIO)<br>-{<br>- Name (_HID, "ACPI000A")<br>- Name (_ADR, 0x001e0000)<br>-}<br>-<br>-/* PCI-X bridge */<br>-Device(P64A)<br>-{<br>- Name (_ADR, 0x001f0000)<br>- Name (_PRT, Package() {<br>- Package() { 0x0002ffff, 0, 0, 48 }, /* PCI-X slot 3 */<br>- Package() { 0x0002ffff, 1, 0, 49 },<br>- Package() { 0x0002ffff, 2, 0, 50 },<br>- Package() { 0x0002ffff, 3, 0, 51 },<br>- Package() { 0x0003ffff, 0, 0, 52 }, /* PCI-X slot 4 */<br>- Package() { 0x0003ffff, 1, 0, 53 },<br>- Package() { 0x0003ffff, 2, 0, 54 },<br>- Package() { 0x0003ffff, 3, 0, 55 },<br>- Package() { 0x0004ffff, 0, 0, 54 }, /* On-board SCSI, GSI not 56 ? */<br>- Package() { 0x0004ffff, 1, 0, 55 }, /* On-board SCSI, GSI not 57 */<br>- })<br>-<br>- Name (_PRW, Package () { 0x0B, 0x05 }) /* PME# _STS */<br>- OperationRegion (PBPC, PCI_Config, 0x00, 0xFF)<br>- Field (PBPC, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0x3E), BCRL, 8, BCRH, 8<br>- }<br>-<br>- #include "acpi/scsi.asl"<br>-}<br>diff --git a/src/mainboard/aopen/dxplplusu/acpi/power.asl b/src/mainboard/aopen/dxplplusu/acpi/power.asl<br>deleted file mode 100644<br>index 69c1d62..0000000<br>--- a/src/mainboard/aopen/dxplplusu/acpi/power.asl<br>+++ /dev/null<br>@@ -1,90 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-<br>-/* Board powers on with button or PME# from on-board GbE wake-on-lan.<br>- * Board shuts down to S5/G2. Any other power management is untested.<br>- */<br>-<br>-Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })<br>-Name (\_S1, Package () { 0x01, 0x01, 0x00, 0x00 })<br>-Name (\_S3, Package () { 0x05, 0x05, 0x00, 0x00 })<br>-Name (\_S4, Package () { 0x06, 0x06, 0x00, 0x00 })<br>-Name (\_S5, Package () { 0x07, 0x07, 0x00, 0x00 })<br>-<br>-Scope (\_GPE)<br>-{<br>- Method (_L03, 0, NotSerialized)<br>- {<br>- Notify (\_SB.PCI0.USB0, 0x02)<br>- }<br>- Method (_L04, 0, NotSerialized)<br>- {<br>- Notify (\_SB.PCI0.USB1, 0x02)<br>- }<br>-<br>- /* WOL header */<br>- Method (_L08, 0, NotSerialized)<br>- {<br>- Notify (\_SB.PCI0.PCI5, 0x02)<br>- Notify (\_SB.SLBT, 0x02)<br>- }<br>-<br>- /* PME# */<br>- Method (_L0B, 0, NotSerialized)<br>- {<br>-#if 1<br>- Notify (\_SB.LID0, 0x02)<br>-#else<br>- Notify (\_SB.PCI0.HLIB.P64B.ETH0, 0x02)<br>- Notify (\_SB.PCI0.HLIB.P64B, 0x02)<br>- Notify (\_SB.PCI0.HLIB.P64A, 0x02)<br>-#endif<br>- }<br>-<br>- Method (_L0C, 0, NotSerialized)<br>- {<br>- Notify (\_SB.PCI0.USB2, 0x02)<br>- }<br>-<br>- /* PME_B0_STS# */<br>- Method (_L0D, 0, NotSerialized)<br>- {<br>- Notify (\_SB.PCI0.USB3, 0x02)<br>- }<br>-}<br>-<br>-/* Clear power buttons */<br>-Method (\_INI, 0, NotSerialized)<br>-{<br>- Or (\_SB.PCI0.ICH0.PS1H, 0x09, \_SB.PCI0.ICH0.PS1H)<br>- Or (\_SB.PCI0.ICH0.PE1H, 0x01, \_SB.PCI0.ICH0.PE1H)<br>-}<br>-<br>-/* Prepare To Sleep */<br>-Method (\_PTS, 1, NotSerialized)<br>-{<br>- Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H)<br>- Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L)<br>-}<br>-<br>-/* System Wake */<br>-Method (\_WAK, 1, NotSerialized)<br>-{<br>- Or (\_SB.PCI0.ICH0.GS0H, 0x19, \_SB.PCI0.ICH0.GS0H)<br>- Or (\_SB.PCI0.ICH0.GS0L, 0x11, \_SB.PCI0.ICH0.GS0L)<br>-<br>- Return ( Package() { 0x0, 0x0 } )<br>-}<br>diff --git a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl<br>deleted file mode 100644<br>index e76deb7..0000000<br>--- a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl<br>+++ /dev/null<br>@@ -1,58 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/* PCI-X devices 04:04.0 and 04:04.1 : AIC-7902W<br>- * U320 SCSI dual-channel controller<br>- */<br>-<br>-Device (SCS0)<br>-{<br>- Name (_ADR, 0x00040000)<br>- OperationRegion (SCSC, PCI_Config, 0x00, 0x0100)<br>- Field (SCSC, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0x2C), SID, 32,<br>- Offset (0xE0), PMC, 8,<br>- Offset (0xFF), IDW, 8<br>- }<br>-}<br>-<br>-Device (SCS1)<br>-{<br>- Name (_ADR, 0x00040001)<br>- OperationRegion (SCSC, PCI_Config, 0x00, 0x0100)<br>- Field (SCSC, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0x2C), SID, 32,<br>- Offset (0xE0), PMC, 8,<br>- Offset (0xFF), IDW, 8<br>- }<br>-}<br>-<br>-#if 0<br>-/* Set subsystem id for both SCSI devices.<br>- * It may require some delay on wake-up before this can be done.<br>- */<br>- Method ( )<br>- {<br>- Or (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS0.IDW)<br>- Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS0.SID)<br>- And (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS0.IDW)<br>-<br>- Or (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS1.IDW)<br>- Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS1.SID)<br>- And (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS1.IDW)<br>- }<br>-#endif<br>diff --git a/src/mainboard/aopen/dxplplusu/acpi/superio.asl b/src/mainboard/aopen/dxplplusu/acpi/superio.asl<br>deleted file mode 100644<br>index c042c32..0000000<br>--- a/src/mainboard/aopen/dxplplusu/acpi/superio.asl<br>+++ /dev/null<br>@@ -1,178 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-<br>-/* SuperIO GPIO configuration via logical device 0x0A */<br>-<br>-Name (MSBF, ResourceTemplate ()<br>-{<br>- IO (Decode16, 0x0000, 0x0000, 0x01, 0x80, _Y1B)<br>-})<br>-<br>-OperationRegion (LPC0, SystemIO, 0x0E00, 0x60)<br>-Field (LPC0, ByteAcc, NoLock, Preserve)<br>-{<br>- PME0, 8,<br>- Offset (0x02), PME2,8,<br>- Offset (0x04), PME4,8,<br>- Offset (0x0A), PMEA,8,<br>- Offset (0x23),<br>- GC10,8, GC11,8, GC12,8, GC13,8, GC14,8, GC15,8, GC16,8, GC17,8,<br>- GC20,8, GC21,8, GC22,8, GC23,8, GC24,8, GC25,8, GC26,8, GC27,8,<br>- GC30,8, GC31,8, GC32,8, GC33,8, GC34,8, GC35,8, GC36,8, GC37,8,<br>- GC40,8, GC41,8, GC42,8, GC43,8,<br>-<br>- Offset (0x3F),<br>- GC50,8, GC51,8, GC52,8, GC53,8, GC54,8, GC55,8, GC56,8, GC57,8,<br>- GC60,8, GC61,8,<br>-<br>- Offset (0x4B),<br>- GP_1,8, GP_2,8, GP_3,8, GP_4,8, GP_5,8, GP_6,8,<br>- Offset (0x56), FAN1,8,<br>- Offset (0x5D), LED1,8, LED2,8,<br>-}<br>-<br>-OperationRegion (SMC1, SystemIO, 0x2E, 0x02)<br>-Field (SMC1, ByteAcc, NoLock, Preserve)<br>-{<br>- INDX, 8, DATA, 8<br>-}<br>-<br>-IndexField (INDX, DATA, ByteAcc, NoLock, Preserve)<br>-{<br>- Offset (0x07), LDN, 8,<br>- Offset (0x22), PWRC, 8,<br>- Offset (0x30), ACTR, 8,<br>- Offset (0x60),<br>- IOAH, 8, IOAL, 8,<br>- IOBH, 8, IOBL, 8,<br>-<br>- Offset (0x70), INTR, 8,<br>- Offset (0x72), INT1, 8,<br>- Offset (0x74), DMCH, 8,<br>- Offset (0xB2), SPS1, 8, SPS2, 8,<br>- Offset (0xB8), D2TS, 8,<br>- Offset (0xF0), OPT1, 8, OPT2, 8, OPT3, 8,<br>- Offset (0xF4), WDTC, 8,<br>- Offset (0xF6), GP01, 8, GP02, 8, GP04, 8<br>-}<br>-<br>-Method (ECFG, 0, NotSerialized)<br>-{<br>- Store (0x55, INDX)<br>-}<br>-Method (XCFG, 0, NotSerialized)<br>-{<br>- Store (0xAA, INDX)<br>-}<br>-<br>-Method (_CRS, 0, NotSerialized)<br>-{<br>- CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MIN, IOM1)<br>- CreateWordField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._MAX, IOM2)<br>- CreateByteField (MSBF, \_SB.PCI0.ICH0.SMSC._Y1B._LEN, IOML)<br>-<br>- ECFG ()<br>- Store (0x0A, \_SB.PCI0.ICH0.SMSC.LDN)<br>- Store (0x00, IOM1)<br>- Store (0x00, IOM2)<br>- Or (\_SB.PCI0.ICH0.SMSC.IOAH, IOM1, IOM1)<br>- ShiftLeft (IOM1, 0x08, IOM1)<br>- Or (\_SB.PCI0.ICH0.SMSC.IOAL, IOM1, IOM1)<br>- Store (IOM1, IOM2)<br>- If (LNotEqual (IOM1, 0x00))<br>- {<br>- Store (0x80, IOML)<br>- }<br>- XCFG ()<br>-<br>- Return (MSBF)<br>-}<br>-<br>-<br>-Method (_INI, 0, NotSerialized)<br>-{<br>- /* GPIO configuration */<br>- Store (0x00, GC10)<br>- Store (0x81, GC11)<br>- Store (0x00, GC17)<br>- Store (0x0c, GC21)<br>- Store (0x00, GC22)<br>- Store (0x04, GC27)<br>- Store (0x04, GC30)<br>- Store (0x01, GC31)<br>- Store (0x01, GC32)<br>- Store (0x01, GC33)<br>- Store (0x01, GC34) /* GPI password jumper */<br>- Store (0x01, GC35) /* GPI scsi enable jumper */<br>-#if 1<br>- Store (0x01, GC42) /* GPI */<br>-#else<br>- Store (0x84, GC42) /* nIO_PME */<br>-#endif<br>- Store (0x86, GC60) /* led 1 */<br>- Store (0x81, GC61) /* led 2 ?? */<br>-<br>- /* GPIO initial output levels */<br>- Store (GP_1, Local0)<br>- And( Local0, 0x7C, Local0)<br>- Or ( Local0, 0x81, Local0)<br>- Store (Local0, GP_1)<br>-<br>- Store (GP_2, Local0)<br>- And( Local0, 0xFE, Local0)<br>- Or ( Local0, 0x00, Local0)<br>- Store (Local0, GP_2)<br>-<br>- Store (GP_3, Local0)<br>- And( Local0, 0x7F, Local0)<br>- Or ( Local0, 0x80, Local0)<br>- Store (Local0, GP_3)<br>-<br>- Store (GP_4, Local0)<br>- And( Local0, 0x7F, Local0)<br>- Or ( Local0, 0x00, Local0)<br>- Store (Local0, GP_4)<br>-<br>- /* Power Led */<br>- Store (LED1, Local0)<br>- And( Local0, 0xfc, Local0)<br>- Or ( Local0, 0x01, Local0)<br>- Store (Local0, LED1)<br>-<br>-}<br>-<br>-Method (MLED, 1, NotSerialized)<br>-{<br>- If (LEqual (Arg0, 0x00))<br>- {<br>- Store (0x00, LED1)<br>- }<br>-<br>- If (LOr (LEqual (Arg0, 0x01), LEqual (Arg0, 0x02)))<br>- {<br>- Store (0x01, LED1)<br>- }<br>-<br>- If (LEqual (Arg0, 0x03))<br>- {<br>- Store (0x02, LED1)<br>- }<br>-<br>- If (LOr (LEqual (Arg0, 0x04), LEqual (Arg0, 0x05)))<br>- {<br>- Store (0x03, LED1)<br>- }<br>-}<br>diff --git a/src/mainboard/aopen/dxplplusu/acpi_tables.c b/src/mainboard/aopen/dxplplusu/acpi_tables.c<br>deleted file mode 100644<br>index e2f4c23..0000000<br>--- a/src/mainboard/aopen/dxplplusu/acpi_tables.c<br>+++ /dev/null<br>@@ -1,69 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Written by Stefan Reinauer <stepan@openbios.org><br>- * (C) 2005 Stefan Reinauer<br>- * (C) 2005 Digital Design Corporation<br>- *<br>- * Ported to Intel XE7501DEVKIT by Agami Aruma<br>- * Ported to AOpen DXPL Plus-U by Kyösti Mälkki<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <console/console.h><br>-#include <string.h><br>-#include <arch/acpi.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <assert.h><br>-#include "bus.h"<br>-<br>-unsigned long acpi_fill_madt(unsigned long current)<br>-{<br>- unsigned int irq_start = 0;<br>- device_t dev = 0;<br>- struct resource* res = NULL;<br>-<br>- /* SJM: Hard-code CPU LAPIC entries for now */<br>- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 0);<br>- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 6);<br>- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 1);<br>- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 7);<br>-<br>- /* Southbridge IOAPIC */<br>- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH4, 0xfec00000, irq_start);<br>- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;<br>-<br>- /* P64H2 Bus B IOAPIC */<br>- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));<br>- if (!dev)<br>- BUG(); /* Config.lb error? */<br>- res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_B, res->base, irq_start);<br>- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;<br>-<br>- /* P64H2 Bus A IOAPIC */<br>- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));<br>- if (!dev)<br>- BUG(); /* Config.lb error? */<br>- res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_BUS_A, res->base, irq_start);<br>- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;<br>-<br>-<br>- /* Map ISA IRQ 0 to IRQ 2 */<br>- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);<br>-<br>- /* IRQ9 differs from ISA standard - ours is active high, level-triggered */<br>- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);<br>-<br>- return current;<br>-}<br>diff --git a/src/mainboard/aopen/dxplplusu/board_info.txt b/src/mainboard/aopen/dxplplusu/board_info.txt<br>deleted file mode 100644<br>index 4e50628..0000000<br>--- a/src/mainboard/aopen/dxplplusu/board_info.txt<br>+++ /dev/null<br>@@ -1,6 +0,0 @@<br>-Category: server<br>-Board URL: ftp://ftp.aopen.com/pub/server/motherboard/dxplpu/manual/dxplpu-ol-e.pdf<br>-ROM package: PLCC<br>-ROM protocol: FWH<br>-ROM socketed: y<br>-Flashrom support: y<br>diff --git a/src/mainboard/aopen/dxplplusu/bus.h b/src/mainboard/aopen/dxplplusu/bus.h<br>deleted file mode 100644<br>index 965b8b7..0000000<br>--- a/src/mainboard/aopen/dxplplusu/bus.h<br>+++ /dev/null<br>@@ -1,39 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#ifndef DXPLPLUSU_BUS_H_INCLUDED<br>-#define DXPLPLUSU_BUS_H_INCLUDED<br>-<br>-/* These were determined by seeing how coreboot enumerates the various<br>- * PCI (and PCI-like) buses on the board.<br>- */<br>-<br>-#define PCI_BUS_ROOT 0<br>-#define PCI_BUS_AGP 1 /* AGP */<br>-#define PCI_BUS_E7501_HI_B 2 /* P64H2#1 */<br>-#define PCI_BUS_P64H2_B 3 /* P64H2#1 bus B */<br>-#define PCI_BUS_P64H2_A 4 /* P64H2#1 bus A */<br>-#define PCI_BUS_ICH4 5 /* ICH4 */<br>-<br>-/* IOAPIC addresses determined by coreboot enumeration. */<br>-/* Someday add functions to get APIC IDs and versions from the chips themselves. */<br>-<br>-#define IOAPIC_ICH4 2<br>-#define IOAPIC_P64H2_BUS_B 3 /* IOAPIC 3 at 02:1c.0 MBAR = fe300000 DataAddr = fe300010 */<br>-#define IOAPIC_P64H2_BUS_A 4 /* IOAPIC 4 at 02:1e.0 MBAR = fe301000 DataAddr = fe301010 */<br>-<br>-#define INTEL_IOAPIC_NUM_INTERRUPTS 24 /* Both ICH-4 and P64-H2 */<br>-<br>-#endif<br>diff --git a/src/mainboard/aopen/dxplplusu/devicetree.cb b/src/mainboard/aopen/dxplplusu/devicetree.cb<br>deleted file mode 100644<br>index bc80e87..0000000<br>--- a/src/mainboard/aopen/dxplplusu/devicetree.cb<br>+++ /dev/null<br>@@ -1,85 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>-##<br>-## This program is free software; you can redistribute it and/or<br>-## modify it under the terms of the GNU General Public License as<br>-## published by the Free Software Foundation; version 2 of<br>-## the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-chip northbridge/intel/e7505<br>-<br>- device cpu_cluster 0 on<br>- chip cpu/intel/socket_mPGA604<br>- device lapic 0 on end<br>- device lapic 6 on end<br>- end<br>- end<br>-<br>- device domain 0 on<br>- device pci 0.0 on end # Chipset host controller<br>- device pci 0.1 on end # Host RASUM controller<br>- device pci 2.0 on # Hub interface B<br>- chip southbridge/intel/i82870 # P64H2<br>- device pci 1c.0 on end # IOAPIC - bus B<br>- device pci 1d.0 on end # Hub to PCI-B bridge<br>- device pci 1e.0 on end # IOAPIC - bus A<br>- device pci 1f.0 on end # Hub to PCI-A bridge<br>- end<br>- end<br>- device pci 4.0 off end # (undocumented)<br>- device pci 6.0 off end # (undocumented)<br>- chip southbridge/intel/i82801dx<br>- device pci 1d.0 on end # USB UHCI<br>- device pci 1d.1 on end # USB UHCI<br>- device pci 1d.2 on end # USB UHCI<br>- device pci 1d.7 on end # USB EHCI<br>- device pci 1e.0 on # Hub to PCI bridge<br>- device pci 2.0 off end<br>- end<br>- device pci 1f.0 on # LPC bridge<br>- chip superio/smsc/lpc47m10x<br>- device pnp 2e.0 off # Floppy<br>- io 0x60 = 0x3f0<br>- irq 0x70 = 6<br>- drq 0x74 = 2<br>- end<br>- device pnp 2e.3 off # Parallel Port<br>- io 0x60 = 0x378<br>- irq 0x70 = 7<br>- end<br>- device pnp 2e.4 on # Com1<br>- io 0x60 = 0x3f8<br>- irq 0x70 = 4<br>- end<br>- device pnp 2e.5 off # Com2<br>- io 0x60 = 0x2f8<br>- irq 0x70 = 3<br>- end<br>- device pnp 2e.7 off # Keyboard<br>- io 0x60 = 0x60<br>- io 0x62 = 0x64<br>- irq 0x70 = 1 # Keyboard interrupt<br>- irq 0x72 = 12 # Mouse interrupt<br>- end<br>- device pnp 2e.a on # ACPI<br>- io 0x60 = 0x0e00<br>- end<br>- end<br>- end<br>- device pci 1f.1 on end # IDE<br>- register "ide0_enable" = "1"<br>- register "ide1_enable" = "1"<br>- device pci 1f.3 on end # SMBus<br>- device pci 1f.5 on end # AC97 Audio<br>- device pci 1f.6 off end # AC97 Modem<br>- end # SB<br>- end # PCI domain<br>-end<br>diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl<br>deleted file mode 100644<br>index 0fec68c..0000000<br>--- a/src/mainboard/aopen/dxplplusu/dsdt.asl<br>+++ /dev/null<br>@@ -1,110 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/ioapic.h><br>-<br>-DefinitionBlock(<br>- "dsdt.aml",<br>- "DSDT",<br>- 0x04, // DSDT revision: ACPI v4.0<br>- "COREv4", // OEM id<br>- "COREBOOT", // OEM table id<br>- 0x20111103 // OEM revision<br>-) {<br>-<br>-Scope(\_SB)<br>-{<br>- Device(PCI0) {<br>- Name (_HID, EISAID("PNP0A03"))<br>- Name (_ADR, 0x00)<br>- Name (_PRT, Package() {<br>- Package() { 0x001dffff, 0, 0, 16 },<br>- Package() { 0x001dffff, 1, 0, 19 },<br>- Package() { 0x001dffff, 2, 0, 18 },<br>- Package() { 0x001dffff, 3, 0, 23 },<br>- Package() { 0x001fffff, 0, 0, 18 },<br>- Package() { 0x001fffff, 1, 0, 17 },<br>- })<br>-<br>- #include "acpi/e7505_sec.asl"<br>-<br>- OperationRegion (I750, PCI_Config, 0x00, 0x0100)<br>- Field (I750, ByteAcc, NoLock, Preserve)<br>- {<br>- Offset (0xC4),<br>- TOLM, 16, /* Top of Low Memory */<br>- RBAR, 16, /* REMAP_BASE */<br>- RLAR, 16 /* REMAP_LIMIT */<br>- }<br>- }<br>-<br>- #include "acpi/e7505_pri.asl"<br>-<br>-<br>- Device (PWBT)<br>- {<br>- Name (_HID, EisaId ("PNP0C0C"))<br>- Name (_PRW, Package () { 0x08, 0x05 })<br>- }<br>-<br>- Device (SLBT)<br>- {<br>- Name (_HID, EisaId ("PNP0C0E"))<br>- Name (_PRW, Package () { 0x0B, 0x05 })<br>- }<br>-<br>- Device (LID0)<br>- {<br>- Name (_HID, EisaId ("PNP0C0D"))<br>- Name (_PRW, Package () { 0x0B, 0x05 })<br>- }<br>-<br>-}<br>-<br>-Scope(\_SB.PCI0)<br>-{<br>-<br>- Device(PCI1)<br>- {<br>- Name (_ADR, 0x00010000)<br>- Name (_PRT, Package() {<br>- Package() { 0x0000ffff, 0, 0, 16 },<br>- Package() { 0x0000ffff, 1, 0, 17 },<br>- })<br>- }<br>-<br>- Device(HLIB)<br>- {<br>- Name (_ADR, 0x00020000)<br>- Name (_PRT, Package() {<br>- Package() { 0x001dffff, 0, 0, 18 },<br>- Package() { 0x001dffff, 1, 0, 18 },<br>- Package() { 0x001dffff, 2, 0, 18 },<br>- Package() { 0x001dffff, 3, 0, 18 },<br>- Package() { 0x001fffff, 0, 0, 18 },<br>- Package() { 0x001fffff, 1, 0, 18 },<br>- Package() { 0x001fffff, 2, 0, 18 },<br>- Package() { 0x001fffff, 3, 0, 18 },<br>- })<br>-<br>- #include "acpi/p64h2.asl"<br>- }<br>-<br>- #include "acpi/i82801db.asl"<br>-}<br>-<br>-#include "acpi/power.asl"<br>-<br>-}<br>diff --git a/src/mainboard/aopen/dxplplusu/fadt.c b/src/mainboard/aopen/dxplplusu/fadt.c<br>deleted file mode 100644<br>index 418d547..0000000<br>--- a/src/mainboard/aopen/dxplplusu/fadt.c<br>+++ /dev/null<br>@@ -1,162 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2007-2009 coresystems GmbH<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <string.h><br>-#include <device/pci.h><br>-#include <arch/acpi.h><br>-<br>-/* FIXME: This needs to go into a separate .h file<br>- * to be included by the ich7 smi handler, ich7 smi init<br>- * code and the mainboard fadt.<br>- */<br>-#define APM_CNT 0x0 /* ACPI mode only */<br>-#define CST_CONTROL 0x85<br>-#define PST_CONTROL 0x0<br>-#define ACPI_DISABLE 0xAA<br>-#define ACPI_ENABLE 0x55<br>-#define S4_BIOS 0x77<br>-#define GNVS_UPDATE 0xea<br>-<br>-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)<br>-{<br>- acpi_header_t *header = &(fadt->header);<br>- u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;<br>-<br>- memset((void *) fadt, 0, sizeof(acpi_fadt_t));<br>- memcpy(header->signature, "FACP", 4);<br>- header->length = sizeof(acpi_fadt_t);<br>- header->revision = 4;<br>- memcpy(header->oem_id, OEM_ID, 6);<br>- memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);<br>- memcpy(header->asl_compiler_id, ASLC, 4);<br>- header->asl_compiler_revision = 1;<br>-<br>- fadt->firmware_ctrl = (unsigned long) facs;<br>- fadt->dsdt = (unsigned long) dsdt;<br>- fadt->model = 1;<br>- fadt->preferred_pm_profile = 0; /* PM_MOBILE; */<br>-<br>- fadt->sci_int = 0x9;<br>- fadt->smi_cmd = APM_CNT;<br>- fadt->acpi_enable = ACPI_ENABLE;<br>- fadt->acpi_disable = ACPI_DISABLE;<br>- fadt->s4bios_req = S4_BIOS;<br>- fadt->pstate_cnt = PST_CONTROL;<br>-<br>- fadt->pm1a_evt_blk = pmbase;<br>- fadt->pm1b_evt_blk = 0x0;<br>- fadt->pm1a_cnt_blk = pmbase + 0x4;<br>- fadt->pm1b_cnt_blk = 0x0;<br>- fadt->pm2_cnt_blk = 0x0;<br>- fadt->pm_tmr_blk = pmbase + 0x8;<br>- fadt->gpe0_blk = pmbase + 0x28;<br>- fadt->gpe1_blk = 0;<br>-<br>- fadt->pm1_evt_len = 4;<br>- fadt->pm1_cnt_len = 2;<br>- /* XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0) */<br>- fadt->pm2_cnt_len = 0;<br>- fadt->pm_tmr_len = 4;<br>- fadt->gpe0_blk_len = 8;<br>- fadt->gpe1_blk_len = 0;<br>- fadt->gpe1_base = 0;<br>- fadt->cst_cnt = 0; /* CST_CONTROL; */<br>- fadt->p_lvl2_lat = 1;<br>- fadt->p_lvl3_lat = 85;<br>- fadt->flush_size = 1024;<br>- fadt->flush_stride = 16;<br>- fadt->duty_offset = 1;<br>- fadt->duty_width = 0;<br>- fadt->day_alrm = 0xd;<br>- fadt->mon_alrm = 0x00;<br>- fadt->century = 0x00;<br>- fadt->iapc_boot_arch = 0x03;<br>-<br>- fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |<br>- ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |<br>- ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;<br>-<br>- fadt->reset_reg.space_id = 0;<br>- fadt->reset_reg.bit_width = 0;<br>- fadt->reset_reg.bit_offset = 0;<br>- fadt->reset_reg.resv = 0;<br>- fadt->reset_reg.addrl = 0x0;<br>- fadt->reset_reg.addrh = 0x0;<br>-<br>- fadt->reset_value = 0;<br>- fadt->x_firmware_ctl_l = (unsigned long)facs;<br>- fadt->x_firmware_ctl_h = 0;<br>- fadt->x_dsdt_l = (unsigned long)dsdt;<br>- fadt->x_dsdt_h = 0;<br>-<br>- fadt->x_pm1a_evt_blk.space_id = 1;<br>- fadt->x_pm1a_evt_blk.bit_width = 32;<br>- fadt->x_pm1a_evt_blk.bit_offset = 0;<br>- fadt->x_pm1a_evt_blk.resv = 0;<br>- fadt->x_pm1a_evt_blk.addrl = pmbase;<br>- fadt->x_pm1a_evt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm1b_evt_blk.space_id = 1;<br>- fadt->x_pm1b_evt_blk.bit_width = 0;<br>- fadt->x_pm1b_evt_blk.bit_offset = 0;<br>- fadt->x_pm1b_evt_blk.resv = 0;<br>- fadt->x_pm1b_evt_blk.addrl = 0x0;<br>- fadt->x_pm1b_evt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm1a_cnt_blk.space_id = 1;<br>- fadt->x_pm1a_cnt_blk.bit_width = 16;<br>- fadt->x_pm1a_cnt_blk.bit_offset = 0;<br>- fadt->x_pm1a_cnt_blk.resv = 0;<br>- fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;<br>- fadt->x_pm1a_cnt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm1b_cnt_blk.space_id = 1;<br>- fadt->x_pm1b_cnt_blk.bit_width = 0;<br>- fadt->x_pm1b_cnt_blk.bit_offset = 0;<br>- fadt->x_pm1b_cnt_blk.resv = 0;<br>- fadt->x_pm1b_cnt_blk.addrl = 0x0;<br>- fadt->x_pm1b_cnt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm2_cnt_blk.space_id = 1;<br>- fadt->x_pm2_cnt_blk.bit_width = 0;<br>- fadt->x_pm2_cnt_blk.bit_offset = 0;<br>- fadt->x_pm2_cnt_blk.resv = 0;<br>- fadt->x_pm2_cnt_blk.addrl = 0x0;<br>- fadt->x_pm2_cnt_blk.addrh = 0x0;<br>-<br>- fadt->x_pm_tmr_blk.space_id = 1;<br>- fadt->x_pm_tmr_blk.bit_width = 32;<br>- fadt->x_pm_tmr_blk.bit_offset = 0;<br>- fadt->x_pm_tmr_blk.resv = 0;<br>- fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;<br>- fadt->x_pm_tmr_blk.addrh = 0x0;<br>-<br>- fadt->x_gpe0_blk.space_id = 1;<br>- fadt->x_gpe0_blk.bit_width = 64;<br>- fadt->x_gpe0_blk.bit_offset = 0;<br>- fadt->x_gpe0_blk.resv = 0;<br>- fadt->x_gpe0_blk.addrl = pmbase + 0x28;<br>- fadt->x_gpe0_blk.addrh = 0x0;<br>-<br>- fadt->x_gpe1_blk.space_id = 1;<br>- fadt->x_gpe1_blk.bit_width = 0;<br>- fadt->x_gpe1_blk.bit_offset = 0;<br>- fadt->x_gpe1_blk.resv = 0;<br>- fadt->x_gpe1_blk.addrl = 0x0;<br>- fadt->x_gpe1_blk.addrh = 0x0;<br>-<br>- header->checksum =<br>- acpi_checksum((void *) fadt, header->length);<br>-}<br>diff --git a/src/mainboard/aopen/dxplplusu/irq_tables.c b/src/mainboard/aopen/dxplplusu/irq_tables.c<br>deleted file mode 100644<br>index 8d9298b..0000000<br>--- a/src/mainboard/aopen/dxplplusu/irq_tables.c<br>+++ /dev/null<br>@@ -1,72 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/pirq_routing.h><br>-#include <device/pci_def.h><br>-#include <device/pci_ids.h><br>-#include "bus.h"<br>-<br>-#define UNUSED_INTERRUPT {0, 0}<br>-#define PIRQ_A 0x60<br>-#define PIRQ_B 0x61<br>-#define PIRQ_C 0x62<br>-#define PIRQ_D 0x63<br>-#define PIRQ_E 0x68<br>-#define PIRQ_F 0x69<br>-#define PIRQ_G 0x6A<br>-#define PIRQ_H 0x6B<br>-<br>-static const struct irq_routing_table intel_irq_routing_table = {<br>- PIRQ_SIGNATURE,<br>- PIRQ_VERSION,<br>- 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Size of this struct in bytes */<br>- 0, /* PCI bus number on which the interrupt router resides */<br>- PCI_DEVFN(31, 0), /* PCI device/function number of the interrupt router */<br>- 0, /* PCI-exclusive IRQ bitmap */<br>- PCI_VENDOR_ID_INTEL, /* Vendor ID of compatible PCI interrupt router */<br>- PCI_DEVICE_ID_INTEL_82801DB_LPC, /* Device ID of compatible PCI interrupt router */<br>- 0, /* Additional miniport information */<br>- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* Reserved, must be zero */<br>- 0xB1, /* Checksum of the entire structure (causes 8-bit sum == 0) */<br>- {<br>- /* NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space */<br>- /* This was determined from linux-2.6.11/arch/i386/pci/irq.c */<br>- /* bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15 */<br>- /* ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13 */<br>- /* Not sure why IRQ9 isn't routable (inherited from Tyan S2735) */<br>-<br>- /* INTA# INTB# INTC# INTD# */<br>- /* bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu */<br>-<br>- {PCI_BUS_ROOT, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, /* IDE / SMBus */<br>- {PCI_BUS_ROOT, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, /* USB 1.1 */<br>-<br>- {PCI_BUS_P64H2_B, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},<br>- {PCI_BUS_P64H2_B, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},<br>- {PCI_BUS_P64H2_B, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, /* GbE */<br>-<br>- {PCI_BUS_P64H2_A, PCI_DEVFN(2, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},<br>- {PCI_BUS_P64H2_A, PCI_DEVFN(3, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0},<br>- {PCI_BUS_P64H2_A, PCI_DEVFN(4, 0) , {{PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}, {PIRQ_C, 0xdcf8}}, 0, 0}, /* SCSI */<br>-<br>- {PCI_BUS_ICH4, PCI_DEVFN(3, 0), {{PIRQ_E, 0xdcf8}, {PIRQ_F, 0xdcf8}, {PIRQ_G, 0xdcf8}, {PIRQ_H, 0xdcf8}}, 0, 0}, /* 32-bit slot */<br>-<br>- }<br>-};<br>-<br>-unsigned long write_pirq_routing_table(unsigned long addr)<br>-{<br>- return copy_pirq_routing_table(addr, &intel_irq_routing_table);<br>-}<br>diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c<br>deleted file mode 100644<br>index f79d3d3..0000000<br>--- a/src/mainboard/aopen/dxplplusu/romstage.c<br>+++ /dev/null<br>@@ -1,80 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com><br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; version 2 of the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <stdint.h><br>-#include <device/pci_def.h><br>-#include <arch/io.h><br>-#include <arch/cpu.h><br>-#include <stdlib.h><br>-#include <console/console.h><br>-#include <cpu/x86/bist.h><br>-#include <cpu/intel/romstage.h><br>-<br>-#include <southbridge/intel/i82801dx/i82801dx.h><br>-#include <northbridge/intel/e7505/raminit.h><br>-<br>-#include <device/pnp_def.h><br>-#include <superio/smsc/lpc47m10x/lpc47m10x.h><br>-<br>-#define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1)<br>-<br>-int spd_read_byte(unsigned device, unsigned address)<br>-{<br>- return smbus_read_byte(device, address);<br>-}<br>-<br>-void mainboard_romstage_entry(unsigned long bist)<br>-{<br>- static const struct mem_controller memctrl[] = {<br>- {<br>- .d0 = PCI_DEV(0, 0, 0),<br>- .d0f1 = PCI_DEV(0, 0, 1),<br>- .channel0 = { 0x50, 0x52, 0, 0 },<br>- .channel1 = { 0x51, 0x53, 0, 0 },<br>- },<br>- };<br>-<br>- /* Get the serial port running and print a welcome banner */<br>- lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>- console_init();<br>-<br>- /* Halt if there was a built in self test failure */<br>- report_bist_failure(bist);<br>-<br>- /* If this is a warm boot, some initialization can be skipped */<br>- if (!e7505_mch_is_ready()) {<br>- enable_smbus();<br>-<br>- /* The real MCH initialisation. */<br>- e7505_mch_init(memctrl);<br>-<br>- /*<br>- * ECC scrub invalidates cache, so all stack in CAR<br>- * is lost. Only return addresses from main() and<br>- * scrub_ecc() are recovered to stack via xmm0-xmm3.<br>- */<br>-#if IS_ENABLED(CONFIG_HW_SCRUBBER)<br>-#if !IS_ENABLED(CONFIG_USBDEBUG_IN_ROMSTAGE)<br>- unsigned long ret_addr = (unsigned long)((unsigned long*)&bist - 1);<br>- e7505_mch_scrub_ecc(ret_addr);<br>-#endif<br>-#endif<br>-<br>- /* Hook for post ECC scrub settings and debug. */<br>- e7505_mch_done(memctrl);<br>- }<br>-<br>- printk(BIOS_DEBUG, "SDRAM is up.\n");<br>-}<br>diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig<br>deleted file mode 100644<br>index 702ba1c..0000000<br>--- a/src/northbridge/intel/e7505/Kconfig<br>+++ /dev/null<br>@@ -1,31 +0,0 @@<br>-##<br>-## This file is part of the coreboot project.<br>-##<br>-## Copyright (C) 2007-2012 coresystems GmbH<br>-##<br>-## This program is free software; you can redistribute it and/or modify<br>-## it under the terms of the GNU General Public License as published by<br>-## the Free Software Foundation; version 2 of the License.<br>-##<br>-## This program is distributed in the hope that it will be useful,<br>-## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>-## GNU General Public License for more details.<br>-##<br>-<br>-config NORTHBRIDGE_INTEL_E7505<br>- bool<br>-<br>-if NORTHBRIDGE_INTEL_E7505<br>-<br>-config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy<br>- def_bool y<br>- select NO_MMCONF_SUPPORT<br>- select HAVE_DEBUG_RAM_SETUP<br>- select LATE_CBMEM_INIT<br>-<br>-config HW_SCRUBBER<br>- bool<br>- default n<br>-<br>-endif<br>diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc<br>deleted file mode 100644<br>index 89a5b8c..0000000<br>--- a/src/northbridge/intel/e7505/Makefile.inc<br>+++ /dev/null<br>@@ -1,7 +0,0 @@<br>-ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y)<br>-<br>-ramstage-y += northbridge.c<br>-romstage-y += raminit.c<br>-romstage-y += debug.c<br>-<br>-endif<br>diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c<br>deleted file mode 100644<br>index e31106e..0000000<br>--- a/src/northbridge/intel/e7505/debug.c<br>+++ /dev/null<br>@@ -1,184 +0,0 @@<br>-<br>-#include <device/pci_def.h><br>-#include <console/console.h><br>-#include <stdlib.h><br>-#include <arch/io.h><br>-#include <spd.h><br>-<br>-#include "raminit.h"<br>-#include "debug.h"<br>-<br>-/*<br>- * generic debug code, used by mainboard specific romstage.c<br>- *<br>- */<br>-<br>-void print_debug_pci_dev(unsigned dev)<br>-{<br>- printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",<br>- (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);<br>-}<br>-<br>-void print_pci_devices(void)<br>-{<br>- pci_devfn_t dev;<br>- for (dev = PCI_DEV(0, 0, 0);<br>- dev <= PCI_DEV(0xff, 0x1f, 0x7);<br>- dev += PCI_DEV(0,0,1)) {<br>- uint32_t id;<br>- id = pci_read_config32(dev, PCI_VENDOR_ID);<br>- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||<br>- (((id >> 16) & 0xffff) == 0xffff) ||<br>- (((id >> 16) & 0xffff) == 0x0000)) {<br>- continue;<br>- }<br>- print_debug_pci_dev(dev);<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>-}<br>-<br>-void dump_pci_device(unsigned dev)<br>-{<br>- int i;<br>- print_debug_pci_dev(dev);<br>-<br>- for (i = 0; i < 256; i++) {<br>- unsigned char val;<br>- if ((i & 0x0f) == 0)<br>- printk(BIOS_DEBUG, "\n%02x:",i);<br>- val = pci_read_config8(dev, i);<br>- printk(BIOS_DEBUG, " %02x", val);<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>-<br>-void dump_pci_devices(void)<br>-{<br>- pci_devfn_t dev;<br>- for (dev = PCI_DEV(0, 0, 0);<br>- dev <= PCI_DEV(0xff, 0x1f, 0x7);<br>- dev += PCI_DEV(0,0,1)) {<br>- uint32_t id;<br>- id = pci_read_config32(dev, PCI_VENDOR_ID);<br>- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||<br>- (((id >> 16) & 0xffff) == 0xffff) ||<br>- (((id >> 16) & 0xffff) == 0x0000)) {<br>- continue;<br>- }<br>- dump_pci_device(dev);<br>- }<br>-}<br>-<br>-void dump_pci_devices_on_bus(unsigned busn)<br>-{<br>- pci_devfn_t dev;<br>- for (dev = PCI_DEV(busn, 0, 0);<br>- dev <= PCI_DEV(busn, 0x1f, 0x7);<br>- dev += PCI_DEV(0,0,1)) {<br>- uint32_t id;<br>- id = pci_read_config32(dev, PCI_VENDOR_ID);<br>- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||<br>- (((id >> 16) & 0xffff) == 0xffff) ||<br>- (((id >> 16) & 0xffff) == 0x0000)) {<br>- continue;<br>- }<br>- dump_pci_device(dev);<br>- }<br>-}<br>-<br>-void dump_spd_registers(const struct mem_controller *ctrl)<br>-{<br>- int i;<br>- printk(BIOS_DEBUG, "\n");<br>- for (i = 0; i < 4; i++) {<br>- unsigned device;<br>- device = ctrl->channel0[i];<br>- if (device) {<br>- int j;<br>- printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);<br>- for (j = 0; j < 128; j++) {<br>- int status;<br>- unsigned char byte;<br>- if ((j & 0xf) == 0)<br>- printk(BIOS_DEBUG, "\n%02x: ", j);<br>- status = spd_read_byte(device, j);<br>- if (status < 0) {<br>- break;<br>- }<br>- byte = status & 0xff;<br>- printk(BIOS_DEBUG, "%02x ", byte);<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>- device = ctrl->channel1[i];<br>- if (device) {<br>- int j;<br>- printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);<br>- for (j = 0; j < 128; j++) {<br>- int status;<br>- unsigned char byte;<br>- if ((j & 0xf) == 0)<br>- printk(BIOS_DEBUG, "\n%02x: ", j);<br>- status = spd_read_byte(device, j);<br>- if (status < 0) {<br>- break;<br>- }<br>- byte = status & 0xff;<br>- printk(BIOS_DEBUG, "%02x ", byte);<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>- }<br>-}<br>-void dump_smbus_registers(void)<br>-{<br>- unsigned device;<br>- printk(BIOS_DEBUG, "\n");<br>- for (device = 1; device < 0x80; device++) {<br>- int j;<br>- if ( spd_read_byte(device, 0) < 0 ) continue;<br>- printk(BIOS_DEBUG, "smbus: %02x", device);<br>- for (j = 0; j < 256; j++) {<br>- int status;<br>- unsigned char byte;<br>- status = spd_read_byte(device, j);<br>- if (status < 0) {<br>- break;<br>- }<br>- if ((j & 0xf) == 0)<br>- printk(BIOS_DEBUG, "\n%02x: ",j);<br>- byte = status & 0xff;<br>- printk(BIOS_DEBUG, "%02x ", byte);<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>-}<br>-<br>-void dump_io_resources(unsigned port)<br>-{<br>- int i;<br>- printk(BIOS_DEBUG, "%04x:\n", port);<br>- for (i = 0; i < 256; i++) {<br>- uint8_t val;<br>- if ((i & 0x0f) == 0)<br>- printk(BIOS_DEBUG, "%02x:", i);<br>- val = inb(port);<br>- printk(BIOS_DEBUG, " %02x",val);<br>- if ((i & 0x0f) == 0x0f) {<br>- printk(BIOS_DEBUG, "\n");<br>- }<br>- port++;<br>- }<br>-}<br>-<br>-void dump_mem(unsigned start, unsigned end)<br>-{<br>- unsigned i;<br>- printk(BIOS_DEBUG, "dump_mem:");<br>- for (i = start; i < end; i++) {<br>- if ((i & 0xf)==0)<br>- printk(BIOS_DEBUG, "\n%08x:", i);<br>- printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));<br>- }<br>- printk(BIOS_DEBUG, "\n");<br>-}<br>diff --git a/src/northbridge/intel/e7505/debug.h b/src/northbridge/intel/e7505/debug.h<br>deleted file mode 100644<br>index 2b060e6..0000000<br>--- a/src/northbridge/intel/e7505/debug.h<br>+++ /dev/null<br>@@ -1,14 +0,0 @@<br>-#ifndef E7505_DEBUG_H<br>-#define E7505_DEBUG_H<br>-<br>-void print_debug_pci_dev(unsigned dev);<br>-void print_pci_devices(void);<br>-void dump_pci_device(unsigned dev);<br>-void dump_pci_devices(void);<br>-void dump_pci_devices_on_bus(unsigned busn);<br>-void dump_spd_registers(const struct mem_controller *ctrl);<br>-void dump_smbus_registers(void);<br>-void dump_io_resources(unsigned port);<br>-void dump_mem(unsigned start, unsigned end);<br>-<br>-#endif<br>diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h<br>deleted file mode 100644<br>index 9c9171d..0000000<br>--- a/src/northbridge/intel/e7505/e7505.h<br>+++ /dev/null<br>@@ -1,85 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2005 Digital Design Corporation<br>- *<br>- * This program is free software; you can redistribute it and/or modify<br>- * it under the terms of the GNU General Public License as published by<br>- * the Free Software Foundation; either version 2 of the License, or<br>- * (at your option) any later version.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-/*<br>- * e7505.h: PCI configuration space for the Intel E7501 memory controller<br>- */<br>-<br>-#ifndef NORTHBRIDGE_INTEL_E7505_E7505_H<br>-#define NORTHBRIDGE_INTEL_E7505_E7505_H<br>-<br>-/************ D0:F0 ************/<br>-// Register offsets<br>-#define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */<br>-#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */<br>-<br>-#define PAM_0 0x59<br>-<br>-#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */<br>-#define DRB_ROW_1 0x61<br>-#define DRB_ROW_2 0x62<br>-#define DRB_ROW_3 0x63<br>-#define DRB_ROW_4 0x64<br>-#define DRB_ROW_5 0x65<br>-#define DRB_ROW_6 0x66<br>-#define DRB_ROW_7 0x67<br>-<br>-#define DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */<br>-#define DRT 0x78 /* DRAM Timing register, 32 bit */<br>-#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */<br>-#define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */<br>-#define CKDIS 0x8C /* Clock disable register, 8 bit */<br>-#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */<br>-#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */<br>-#define REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */<br>-#define SKPD 0xDE /* Scratchpad register, 16 bit */<br>-#define DVNP 0xE0 /* Device Not Present, 16 bit */<br>-#define MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */<br>-<br>-// CAS# Latency bits in the DRAM Timing (DRT) register<br>-#define DRT_CAS_2_5 (0<<4)<br>-#define DRT_CAS_2_0 (1<<4)<br>-#define DRT_CAS_MASK (3<<4)<br>-<br>-// Mode Select (SMS) bits in the DRAM Controller Mode (DRC) register<br>-#define RAM_COMMAND_NOP (1<<4)<br>-#define RAM_COMMAND_PRECHARGE (2<<4)<br>-#define RAM_COMMAND_MRS (3<<4)<br>-#define RAM_COMMAND_EMRS (4<<4)<br>-#define RAM_COMMAND_CBR (6<<4)<br>-#define RAM_COMMAND_NORMAL (7<<4)<br>-<br>-#define DRC_DONE (1 << 29)<br>-<br>-// RCOMP Memory Map offsets<br>-// Conjecture based on apparent similarity between E7501 and 855PM<br>-// Intel doc. 252613-003 describes these for 855PM<br>-<br>-#define SMRCTL 0x20 /* System Memory RCOMP Control Register? */<br>-#define DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */<br>-#define CKESTR 0x31 /* Strength control for CKE signal group? */<br>-#define CSBSTR 0x32 /* Strength control for CS# signal group? */<br>-#define CKSTR 0x33 /* Strength control for CK signal group? */<br>-#define RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */<br>-<br>-/************ D0:F1 ************/<br>-// Register offsets<br>-#define FERR_GLOBAL 0x40 /* First global error register, 32 bits */<br>-#define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */<br>-#define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */<br>-#define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */<br>-<br>-#endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */<br>diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c<br>deleted file mode 100644<br>index f6e14d6..0000000<br>--- a/src/northbridge/intel/e7505/northbridge.c<br>+++ /dev/null<br>@@ -1,147 +0,0 @@<br>-#include <console/console.h><br>-#include <arch/io.h><br>-#include <stdint.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <cpu/cpu.h><br>-#include <stdlib.h><br>-#include <string.h><br>-#include "e7505.h"<br>-#include <cbmem.h><br>-#include <arch/acpi.h><br>-<br>-unsigned long acpi_fill_mcfg(unsigned long current)<br>-{<br>- /* Just a dummy */<br>- return current;<br>-}<br>-<br>-static void pci_domain_set_resources(device_t dev)<br>-{<br>- device_t mc_dev;<br>- uint32_t pci_tolm;<br>-<br>- pci_tolm = find_pci_tolm(dev->link_list);<br>- mc_dev = dev->link_list->children;<br>- if (mc_dev) {<br>- /* Figure out which areas are/should be occupied by RAM.<br>- * This is all computed in kilobytes and converted to/from<br>- * the memory controller right at the edges.<br>- * Having different variables in different units is<br>- * too confusing to get right. Kilobytes are good up to<br>- * 4 Terabytes of RAM...<br>- */<br>- uint16_t tolm_r, remapbase_r, remaplimit_r;<br>- unsigned long tomk, tolmk;<br>- unsigned long remapbasek, remaplimitk;<br>- int idx;<br>-<br>- /* Get the value of the highest DRB. This tells the end of<br>- * the physical memory. The units are ticks of 64MB<br>- * i.e. 1 means 64MB.<br>- */<br>- tomk = ((unsigned long)pci_read_config8(mc_dev, DRB_ROW_7)) << 16;<br>- /* Compute the top of Low memory */<br>- tolmk = pci_tolm >> 10;<br>- if (tolmk >= tomk) {<br>- /* The PCI hole does not overlap memory<br>- * we won't use the remap window.<br>- */<br>- tolmk = tomk;<br>- remapbasek = 0x3ff << 16;<br>- remaplimitk = 0 << 16;<br>- }<br>- else {<br>- /* The PCI memory hole overlaps memory<br>- * setup the remap window.<br>- */<br>- /* Find the bottom of the remap window<br>- * is it above 4G?<br>- */<br>- remapbasek = 4*1024*1024;<br>- if (tomk > remapbasek) {<br>- remapbasek = tomk;<br>- }<br>- /* Find the limit of the remap window */<br>- remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));<br>- }<br>- /* Write the RAM configuration registers,<br>- * preserving the reserved bits.<br>- */<br>- tolm_r = pci_read_config16(mc_dev, TOLM);<br>- tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);<br>- pci_write_config16(mc_dev, TOLM, tolm_r);<br>-<br>- remapbase_r = pci_read_config16(mc_dev, REMAPBASE);<br>- remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);<br>- pci_write_config16(mc_dev, REMAPBASE, remapbase_r);<br>-<br>- remaplimit_r = pci_read_config16(mc_dev, REMAPLIMIT);<br>- remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);<br>- pci_write_config16(mc_dev, REMAPLIMIT, remaplimit_r);<br>-<br>- /* Report the memory regions */<br>- idx = 10;<br>- ram_resource(dev, idx++, 0, 640);<br>- ram_resource(dev, idx++, 768, tolmk - 768);<br>- if (tomk > 4*1024*1024) {<br>- ram_resource(dev, idx++, 4096*1024, tomk - 4*1024*1024);<br>- }<br>- if (remaplimitk >= remapbasek) {<br>- ram_resource(dev, idx++, remapbasek,<br>- (remaplimitk + 64*1024) - remapbasek);<br>- }<br>-<br>- set_late_cbmem_top(tolmk * 1024);<br>- }<br>- assign_resources(dev->link_list);<br>-}<br>-<br>-static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)<br>-{<br>- pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,<br>- ((device & 0xffff) << 16) | (vendor & 0xffff));<br>-}<br>-<br>-static struct pci_operations intel_pci_ops = {<br>- .set_subsystem = intel_set_subsystem,<br>-};<br>-<br>-static struct device_operations pci_domain_ops = {<br>- .read_resources = pci_domain_read_resources,<br>- .set_resources = pci_domain_set_resources,<br>- .enable_resources = NULL,<br>- .init = NULL,<br>- .scan_bus = pci_domain_scan_bus,<br>- .ops_pci = &intel_pci_ops,<br>- .ops_pci_bus = pci_bus_default_ops,<br>-};<br>-<br>-static void cpu_bus_init(device_t dev)<br>-{<br>- initialize_cpus(dev->link_list);<br>-}<br>-<br>-static struct device_operations cpu_bus_ops = {<br>- .read_resources = DEVICE_NOOP,<br>- .set_resources = DEVICE_NOOP,<br>- .enable_resources = DEVICE_NOOP,<br>- .init = cpu_bus_init,<br>- .scan_bus = 0,<br>-};<br>-<br>-static void enable_dev(struct device *dev)<br>-{<br>- /* Set the operations if it is a special bus type */<br>- if (dev->path.type == DEVICE_PATH_DOMAIN) {<br>- dev->ops = &pci_domain_ops;<br>- }<br>- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {<br>- dev->ops = &cpu_bus_ops;<br>- }<br>-}<br>-<br>-struct chip_operations northbridge_intel_e7505_ops = {<br>- CHIP_NAME("Intel E7505 Northbridge")<br>- .enable_dev = enable_dev,<br>-};<br>diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c<br>deleted file mode 100644<br>index b38132a..0000000<br>--- a/src/northbridge/intel/e7505/raminit.c<br>+++ /dev/null<br>@@ -1,1926 +0,0 @@<br>-/* This was originally for the e7500, modified for e7501<br>- * The primary differences are that 7501 apparently can<br>- * support single channel RAM (i haven't tested),<br>- * CAS1.5 is no longer supported, The ECC scrubber<br>- * now supports a mode to zero RAM and init ECC in one step<br>- * and the undocumented registers at 0x80 require new<br>- * (undocumented) values determined by guesswork and<br>- * comparison w/ OEM BIOS values.<br>- * Steven James 02/06/2003<br>- */<br>-<br>-/* converted to C 6/2004 yhlu */<br>-<br>-<br>-#include <stdint.h><br>-#include <device/pci_def.h><br>-#include <arch/io.h><br>-#include <arch/cpu.h><br>-#include <lib.h><br>-#include <stdlib.h><br>-#include <console/console.h><br>-<br>-#include <cpu/x86/mtrr.h><br>-#include <cpu/x86/cache.h><br>-#include <cpu/x86/msr.h><br>-#include <assert.h><br>-#include <spd.h><br>-#include <sdram_mode.h><br>-#include <cbmem.h><br>-<br>-#include "raminit.h"<br>-#include "e7505.h"<br>-#include "debug.h"<br>-<br>-/*-----------------------------------------------------------------------------<br>-Definitions:<br>------------------------------------------------------------------------------*/<br>-<br>-// Uncomment this to enable run-time checking of DIMM parameters<br>-// for dual-channel operation<br>-// Unfortunately the code seems to chew up several K of space.<br>-//#define VALIDATE_DIMM_COMPATIBILITY<br>-<br>-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>-#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)<br>-#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)<br>-#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)<br>-#define DUMPNORTH() dump_pci_device(MCHDEV)<br>-#else<br>-#define RAM_DEBUG_MESSAGE(x)<br>-#define RAM_DEBUG_HEX32(x)<br>-#define RAM_DEBUG_HEX8(x)<br>-#define DUMPNORTH()<br>-#endif<br>-<br>-#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)<br>-#define SPD_ERROR "Error reading SPD info\n"<br>-<br>-#define MCHDEV PCI_DEV(0,0,0)<br>-#define RASDEV PCI_DEV(0,0,1)<br>-#define D060DEV PCI_DEV(0,6,0)<br>-<br>-// NOTE: This used to be 0x100000.<br>-// That doesn't work on systems where A20M# is asserted, because<br>-// attempts to access 0x1000NN end up accessing 0x0000NN.<br>-#define RCOMP_MMIO ((u8 *)0x200000)<br>-<br>-struct dimm_size {<br>- unsigned long side1;<br>- unsigned long side2;<br>-};<br>-<br>-static const uint32_t refresh_frequency[] = {<br>- /* Relative frequency (array value) of each E7501 Refresh Mode Select<br>- * (RMS) value (array index)<br>- * 0 == least frequent refresh (longest interval between refreshes)<br>- * [0] disabled -> 0<br>- * [1] 15.6 usec -> 2<br>- * [2] 7.8 usec -> 3<br>- * [3] 64 usec -> 1<br>- * [4] reserved -> 0<br>- * [5] reserved -> 0<br>- * [6] reserved -> 0<br>- * [7] 64 clocks -> 4<br>- */<br>- 0, 2, 3, 1, 0, 0, 0, 4<br>-};<br>-<br>-static const uint32_t refresh_rate_map[] = {<br>- /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode<br>- * Select values (array value)<br>- * These are all the rates defined by JESD21-C Appendix D, Rev. 1.0<br>- * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and<br>- * 64 clock (481 ns) (7) refresh.<br>- * [0] == 15.625 us -> 15.6 us<br>- * [1] == 3.9 us -> 481 ns<br>- * [2] == 7.8 us -> 7.8 us<br>- * [3] == 31.3 us -> 15.6 us<br>- * [4] == 62.5 us -> 15.6 us<br>- * [5] == 125 us -> 64 us<br>- */<br>- 1, 7, 2, 1, 1, 3<br>-};<br>-<br>-#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1)<br>-<br>-#ifdef VALIDATE_DIMM_COMPATIBILITY<br>-// SPD parameters that must match for dual-channel operation<br>-static const uint8_t dual_channel_parameters[] = {<br>- SPD_MEMORY_TYPE,<br>- SPD_MODULE_VOLTAGE,<br>- SPD_NUM_COLUMNS,<br>- SPD_NUM_ROWS,<br>- SPD_NUM_DIMM_BANKS,<br>- SPD_PRIMARY_SDRAM_WIDTH,<br>- SPD_NUM_BANKS_PER_SDRAM<br>-};<br>-#endif /* VALIDATE_DIMM_COMPATIBILITY */<br>-<br>- /* Comments here are remains of e7501 or even 855PM.<br>- * They might be partially (in)correct for e7505.<br>- */<br>-<br>- /* (DRAM Read Timing Control, if similar to 855PM?)<br>- * 0x80 - 0x81 documented differently for e7505<br>- * This register has something to do with CAS latencies,<br>- * possibly this is the real chipset control.<br>- * At 0x00 CAS latency 1.5 works.<br>- * At 0x06 CAS latency 2.5 works.<br>- * At 0x01 CAS latency 2.0 works.<br>- *<br>- * This is still undocumented in e7501, but with different values<br>- * CAS 2.0 values taken from Intel BIOS settings, others are a guess<br>- * and may be terribly wrong. Old values preserved as comments until I<br>- * figure this out for sure.<br>- * e7501 docs claim that CAS1.5 is unsupported, so it may or may not<br>- * work at all.<br>- * Steven James 02/06/2003<br>- *<br>- * NOTE: values now configured in configure_e7501_cas_latency() based<br>- * on SPD info and total number of DIMMs (per Intel)<br>- */<br>-<br>- /* FDHC - Fixed DRAM Hole Control ???<br>- * 0x58 undocumented for e7505, memory hole in southbridge configuration?<br>- * [7:7] Hole_Enable<br>- * 0 == No memory Hole<br>- * 1 == Memory Hole from 15MB to 16MB<br>- * [6:0] Reserved<br>- */<br>-<br>- /* Another Intel undocumented register<br>- * 0x88 - 0x8B<br>- * [31:31] Purpose unknown<br>- * [26:26] Master DLL Reset?<br>- * 0 == Normal operation?<br>- * 1 == Reset?<br>- * [07:07] Periodic memory recalibration?<br>- * 0 == Disabled?<br>- * 1 == Enabled?<br>- * [04:04] Receive FIFO RE-Sync?<br>- * 0 == Normal operation?<br>- * 1 == Reset?<br>- */<br>-<br>-/* DDR RECOMP tables */<br>-// Slew table for 2x drive?<br>-static const uint32_t slew_2x[] = {<br>- 0x00000000, 0x76543210, 0xffffeca8, 0xffffffff,<br>- 0x21000000, 0xa8765432, 0xffffffec, 0xffffffff,<br>-};<br>-<br>-// Pull Up / Pull Down offset table, if analogous to IXP2800?<br>-static const uint32_t pull_updown_offset_table[] = {<br>- 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,<br>- 0x88888888, 0x88888888, 0x88888888, 0x88888888,<br>-};<br>-<br>-/*-----------------------------------------------------------------------------<br>-Delay functions:<br>------------------------------------------------------------------------------*/<br>-<br>-/* Estimate that SLOW_DOWN_IO takes about 1 us */<br>-#define SLOW_DOWN_IO inb(0x80)<br>-static void local_udelay(int i)<br>-{<br>- while (i--) {<br>- SLOW_DOWN_IO;<br>- }<br>-}<br>-<br>-/* delay for 200us */<br>-#define DO_DELAY local_udelay(200)<br>-#define EXTRA_DELAY DO_DELAY<br>-<br>-/*-----------------------------------------------------------------------------<br>-Handle (undocumented) control bits MCHTST and PCI_DEV(0,6,0)<br>------------------------------------------------------------------------------*/<br>-typedef enum {<br>- MCHTST_CMD_0,<br>- D060_ENABLE,<br>- D060_DISABLE,<br>- RCOMP_BAR_ENABLE,<br>- RCOMP_BAR_DISABLE,<br>-} mchtst_cc;<br>-<br>-typedef enum {<br>- D060_CMD_0,<br>- D060_CMD_1,<br>-} d060_cc;<br>-<br>-typedef enum {<br>- RCOMP_HOLD,<br>- RCOMP_RELEASE,<br>- RCOMP_SMR_00,<br>- RCOMP_SMR_01,<br>-} rcomp_smr_cc;<br>-<br>-/**<br>- * MCHTST - 0xF4 - 0xF7 -- Based on similarity to 855PM<br>- *<br>- * [31:31] Purpose unknown<br>- * [30:30] Purpose unknown<br>- * [29:23] Unknown - not used?<br>- * [22:22] System Memory MMR Enable<br>- * 0 == Disable: mem space and BAR at 0x14 are not accessible<br>- * 1 == Enable: mem space and BAR at 0x14 are accessible<br>- * [21:20] Purpose unknown<br>- * [19:02] Unknown - not used?<br>- * [01:01] D6EN (Device #6 enable)<br>- * 0 == Disable<br>- * 1 == Enable<br>- * [00:00] Unknown - not used?<br>- */<br>-static void mchtest_control(mchtst_cc cmd)<br>-{<br>- uint32_t dword = pci_read_config32(MCHDEV, MCHTST);<br>- switch (cmd) {<br>- case MCHTST_CMD_0:<br>- dword &= ~(3 << 30);<br>- break;<br>- case RCOMP_BAR_ENABLE:<br>- dword |= (1 << 22);<br>- break;<br>- case RCOMP_BAR_DISABLE:<br>- dword &= ~(1 << 22);<br>- break;<br>- case D060_ENABLE:<br>- dword |= (1 << 1);<br>- break;<br>- case D060_DISABLE:<br>- dword &= ~(1 << 1);<br>- break;<br>- };<br>- pci_write_config32(MCHDEV, MCHTST, dword);<br>-}<br>-<br>-<br>-/**<br>- *<br>- */<br>-static void d060_control(d060_cc cmd)<br>-{<br>- mchtest_control(D060_ENABLE);<br>- uint32_t dword = pci_read_config32(D060DEV, 0xf0);<br>- switch (cmd) {<br>- case D060_CMD_0:<br>- dword |= (1 << 2);<br>- break;<br>- case D060_CMD_1:<br>- dword |= (3 << 27);<br>- break;<br>- }<br>- pci_write_config32(D060DEV, 0xf0, dword);<br>- mchtest_control(D060_DISABLE);<br>-}<br>-<br>-/**<br>- *<br>- */<br>-static void rcomp_smr_control(rcomp_smr_cc cmd)<br>-{<br>- uint32_t dword = read32(RCOMP_MMIO + SMRCTL);<br>- switch (cmd) {<br>- case RCOMP_HOLD:<br>- dword |= (1 << 9);<br>- break;<br>- case RCOMP_RELEASE:<br>- dword &= ~((1 << 9) | (3 << 0));<br>- dword |= (1 << 10) | (1 << 0);<br>- break;<br>- case RCOMP_SMR_00:<br>- dword &= ~(1 << 8);<br>- break;<br>- case RCOMP_SMR_01:<br>- dword |= (1 << 10) | (1 << 8);<br>- break;<br>- }<br>- write32(RCOMP_MMIO + SMRCTL, dword);<br>-}<br>-<br>-/*-----------------------------------------------------------------------------<br>-Serial presence detect (SPD) functions:<br>------------------------------------------------------------------------------*/<br>-<br>-static void die_on_spd_error(int spd_return_value)<br>-{<br>- if (spd_return_value < 0)<br>- die("Error reading SPD info\n");<br>-}<br>-<br>-/**<br>- * Calculate the page size for each physical bank of the DIMM:<br>- * log2(page size) = (# columns) + log2(data width)<br>- *<br>- * NOTE: Page size is the total number of data bits in a row.<br>- *<br>- * @param dimm_socket_address SMBus address of DIMM socket to interrogate.<br>- * @return log2(page size) for each side of the DIMM.<br>- */<br>-static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address)<br>-{<br>- uint16_t module_data_width;<br>- int value;<br>- struct dimm_size pgsz;<br>-<br>- pgsz.side1 = 0;<br>- pgsz.side2 = 0;<br>-<br>- // Side 1<br>- value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);<br>- if (value < 0)<br>- goto hw_err;<br>- pgsz.side1 = value & 0xf; // # columns in bank 1<br>-<br>- /* Get the module data width and convert it to a power of two */<br>- value =<br>- spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB);<br>- if (value < 0)<br>- goto hw_err;<br>- module_data_width = (value & 0xff) << 8;<br>-<br>- value =<br>- spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB);<br>- if (value < 0)<br>- goto hw_err;<br>- module_data_width |= (value & 0xff);<br>-<br>- pgsz.side1 += log2(module_data_width);<br>-<br>- /* side two */<br>- value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);<br>- if (value < 0)<br>- goto hw_err;<br>- if (value > 2)<br>- die("Bad SPD value\n");<br>- if (value == 2) {<br>-<br>- pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently<br>- value =<br>- spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS);<br>- if (value < 0)<br>- goto hw_err;<br>- if ((value & 0xf0) != 0) {<br>- // Asymmetric banks<br>- pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */<br>- pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */<br>- }<br>- }<br>-<br>- return pgsz;<br>-<br>- hw_err:<br>- die(SPD_ERROR);<br>- return pgsz; // Never reached<br>-}<br>-<br>-/**<br>- * Read the width in bits of each DIMM side's DRAMs via SPD (i.e. 4, 8, 16).<br>- *<br>- * @param dimm_socket_address SMBus address of DIMM socket to interrogate.<br>- * @return Width in bits of each DIMM side's DRAMs.<br>- */<br>-static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address)<br>-{<br>- int value;<br>- struct dimm_size width;<br>-<br>- width.side1 = 0;<br>- width.side2 = 0;<br>-<br>- value =<br>- spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH);<br>- die_on_spd_error(value);<br>-<br>- width.side1 = value & 0x7f; // Mask off bank 2 flag<br>-<br>- if (value & 0x80) {<br>- width.side2 = width.side1 << 1; // Bank 2 exists and is double-width<br>- } else {<br>- // If bank 2 exists, it's the same width as bank 1<br>- value =<br>- spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);<br>- die_on_spd_error(value);<br>-<br>-#ifdef ROMCC_IF_BUG_FIXED<br>- if (value == 2)<br>- width.side2 = width.side1;<br>-#else<br>- switch (value) {<br>- case 2:<br>- width.side2 = width.side1;<br>- break;<br>-<br>- default:<br>- break;<br>- }<br>-#endif<br>- }<br>-<br>- return width;<br>-}<br>-<br>-/**<br>- * Calculate the log base 2 size in bits of both DIMM sides.<br>- *<br>- * log2(# bits) = (# columns) + log2(data width) +<br>- * (# rows) + log2(banks per SDRAM)<br>- *<br>- * Note that it might be easier to use SPD byte 31 here, it has the DIMM size<br>- * as a multiple of 4MB. The way we do it now we can size both sides of an<br>- * asymmetric DIMM.<br>- *<br>- * @param dimm_socket_address SMBus address of DIMM socket to interrogate.<br>- * @return log2(number of bits) for each side of the DIMM.<br>- */<br>-static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address)<br>-{<br>- int value;<br>-<br>- // Start with log2(page size)<br>- struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address);<br>-<br>- if (sz.side1 > 0) {<br>-<br>- value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS);<br>- die_on_spd_error(value);<br>-<br>- sz.side1 += value & 0xf;<br>-<br>- if (sz.side2 > 0) {<br>-<br>- // Double-sided DIMM<br>- if (value & 0xF0)<br>- sz.side2 += value >> 4; // Asymmetric<br>- else<br>- sz.side2 += value; // Symmetric<br>- }<br>-<br>- value =<br>- spd_read_byte(dimm_socket_address,<br>- SPD_NUM_BANKS_PER_SDRAM);<br>- die_on_spd_error(value);<br>-<br>- value = log2(value);<br>- sz.side1 += value;<br>- if (sz.side2 > 0)<br>- sz.side2 += value;<br>- }<br>-<br>- return sz;<br>-}<br>-<br>-#ifdef VALIDATE_DIMM_COMPATIBILITY<br>-<br>-/**<br>- * Determine whether two DIMMs have the same value for an SPD parameter.<br>- *<br>- * @param spd_byte_number The SPD byte number to compare in both DIMMs.<br>- * @param dimm0_address SMBus address of the 1st DIMM socket to interrogate.<br>- * @param dimm1_address SMBus address of the 2nd DIMM socket to interrogate.<br>- * @return 1 if both DIMM sockets report the same value for the specified<br>- * SPD parameter, 0 if the values differed or an error occurred.<br>- */<br>-static uint8_t are_spd_values_equal(uint8_t spd_byte_number,<br>- uint16_t dimm0_address,<br>- uint16_t dimm1_address)<br>-{<br>- uint8_t bEqual = 0;<br>- int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number);<br>- int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number);<br>-<br>- if ((dimm0_value >= 0) && (dimm1_value >= 0)<br>- && (dimm0_value == dimm1_value))<br>- bEqual = 1;<br>-<br>- return bEqual;<br>-}<br>-#endif<br>-<br>-/**<br>- * Scan for compatible DIMMs.<br>- *<br>- * The code in this module only supports dual-channel operation, so we test<br>- * that compatible DIMMs are paired.<br>- *<br>- * @param ctrl PCI addresses of memory controller functions, and SMBus<br>- * addresses of DIMM slots on the mainboard.<br>- * @return A bitmask indicating which of the possible sockets for each channel<br>- * was found to contain a compatible DIMM.<br>- * Bit 0 corresponds to the closest socket for channel 0<br>- * Bit 1 to the next socket for channel 0<br>- * ...<br>- * Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0<br>- * Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1<br>- * ...<br>- * Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1<br>- */<br>-static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)<br>-{<br>- int i;<br>- uint8_t dimm_mask = 0;<br>-<br>- // Have to increase size of dimm_mask if this assertion is violated<br>- ASSERT(MAX_DIMM_SOCKETS_PER_CHANNEL <= 4);<br>-<br>- // Find DIMMs we can support on channel 0.<br>- // Then see if the corresponding channel 1 DIMM has the same parameters,<br>- // since we only support dual-channel.<br>-<br>- for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {<br>-<br>- uint16_t channel0_dimm = ctrl->channel0[i];<br>- uint16_t channel1_dimm = ctrl->channel1[i];<br>- uint8_t bDualChannel = 1;<br>-#ifdef VALIDATE_DIMM_COMPATIBILITY<br>- struct dimm_size page_size;<br>- struct dimm_size sdram_width;<br>-#endif<br>- int spd_value;<br>-<br>- if (channel0_dimm == 0)<br>- continue; // No such socket on this mainboard<br>-<br>- if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) !=<br>- SPD_MEMORY_TYPE_SDRAM_DDR)<br>- continue;<br>-<br>-#ifdef VALIDATE_DIMM_COMPATIBILITY<br>- if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) !=<br>- SPD_VOLTAGE_SSTL2)<br>- continue; // Unsupported voltage<br>-<br>- // E7501 does not support unregistered DIMMs<br>- spd_value =<br>- spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES);<br>- if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0))<br>- continue;<br>-<br>- // Must support burst = 4 for dual-channel operation on E7501<br>- // NOTE: for single-channel, burst = 8 is required<br>- spd_value =<br>- spd_read_byte(channel0_dimm,<br>- SPD_SUPPORTED_BURST_LENGTHS);<br>- if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))<br>- continue;<br>-<br>- page_size = sdram_spd_get_page_size(channel0_dimm);<br>- sdram_width = sdram_spd_get_width(channel0_dimm);<br>-<br>- // Validate DIMM page size<br>- // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel<br>- // NOTE: 4 KB = 32 Kb = 2^15<br>- // 32 KB = 262 Kb = 2^18<br>-<br>- if ((page_size.side1 < 15) || (page_size.side1 > 18))<br>- continue;<br>-<br>- // If DIMM is double-sided, verify side2 page size<br>- if (page_size.side2 != 0) {<br>- if ((page_size.side2 < 15)<br>- || (page_size.side2 > 18))<br>- continue;<br>- }<br>- // Validate SDRAM width<br>- // The E7501 only supports x4 and x8 devices<br>-<br>- if ((sdram_width.side1 != 4) && (sdram_width.side1 != 8))<br>- continue;<br>-<br>- // If DIMM is double-sided, verify side2 width<br>- if (sdram_width.side2 != 0) {<br>- if ((sdram_width.side2 != 4)<br>- && (sdram_width.side2 != 8))<br>- continue;<br>- }<br>-#endif<br>- // Channel 0 DIMM looks compatible.<br>- // Now see if it is paired with the proper DIMM on channel 1.<br>-<br>- ASSERT(channel1_dimm != 0); // No such socket on this mainboard??<br>-<br>- // NOTE: unpopulated DIMMs cause read to fail<br>- spd_value =<br>- spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);<br>- if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {<br>-<br>- printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");<br>- continue;<br>- }<br>-#ifdef VALIDATE_DIMM_COMPATIBILITY<br>- spd_value =<br>- spd_read_byte(channel1_dimm,<br>- SPD_SUPPORTED_BURST_LENGTHS);<br>- if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0))<br>- continue;<br>-<br>- int j;<br>- for (j = 0; j < sizeof(dual_channel_parameters); ++j) {<br>- if (!are_spd_values_equal<br>- (dual_channel_parameters[j], channel0_dimm,<br>- channel1_dimm)) {<br>-<br>- bDualChannel = 0;<br>- break;<br>- }<br>- }<br>-#endif /* VALIDATE_DIMM_COMPATIBILITY */<br>-<br>- // Code around ROMCC bug in optimization of "if" statements<br>-#ifdef ROMCC_IF_BUG_FIXED<br>- if (bDualChannel) {<br>- // Made it through all the checks, this DIMM pair is usable<br>- dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));<br>- } else<br>- printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");<br>-#else<br>- switch (bDualChannel) {<br>- case 0:<br>- printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");<br>- break;<br>-<br>- default:<br>- // Made it through all the checks, this DIMM pair is usable<br>- dimm_mask |= (1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i));<br>- break;<br>- }<br>-#endif<br>- }<br>-<br>- return dimm_mask;<br>-}<br>-<br>-/*-----------------------------------------------------------------------------<br>-SDRAM configuration functions:<br>------------------------------------------------------------------------------*/<br>-<br>-/**<br>- * Send the specified command to all DIMMs.<br>- *<br>- * @param command Specifies the command to be sent to the DIMMs.<br>- * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the<br>- * register value in JEDEC format.<br>- */<br>-static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)<br>-{<br>- uint8_t dimm_start_64M_multiple;<br>- uintptr_t dimm_start_address;<br>- uint32_t dram_controller_mode;<br>- uint8_t i;<br>-<br>- // Configure the RAM command<br>- dram_controller_mode = pci_read_config32(MCHDEV, DRC);<br>- dram_controller_mode &= 0xFFFFFF8F;<br>- dram_controller_mode |= command;<br>- pci_write_config32(MCHDEV, DRC, dram_controller_mode);<br>-<br>- // RAM_COMMAND_NORMAL is an exception.<br>- // It affects only the memory controller and does not need to be "sent" to the DIMMs.<br>- if (command == RAM_COMMAND_NORMAL) {<br>- EXTRA_DELAY;<br>- return;<br>- }<br>-<br>- // NOTE: for mode select commands, some of the location address bits are part of the command<br>- // Map JEDEC mode bits to E7505<br>- if (command == RAM_COMMAND_MRS) {<br>- // Host address lines [25:18] map to DIMM address lines [7:0]<br>- // Host address lines [17:16] map to DIMM address lines [9:8]<br>- // Host address lines [15:4] map to DIMM address lines [11:0]<br>- dimm_start_address = (jedec_mode_bits & 0x00ff) << 18;<br>- dimm_start_address |= (jedec_mode_bits & 0x0300) << 8;<br>- dimm_start_address |= (jedec_mode_bits & 0x0fff) << 4;<br>- } else if (command == RAM_COMMAND_EMRS) {<br>- // Host address lines [15:4] map to DIMM address lines [11:0]<br>- dimm_start_address = (jedec_mode_bits << 4);<br>- } else {<br>- ASSERT(jedec_mode_bits == 0);<br>- dimm_start_address = 0;<br>- }<br>-<br>- // Send the command to all DIMMs by accessing a memory location within each<br>-<br>- dimm_start_64M_multiple = 0;<br>-<br>- /* FIXME: Only address the number of rows present in the system?<br>- * Seems like rows 4-7 overlap with 0-3.<br>- */<br>- for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) {<br>-<br>- uint8_t dimm_end_64M_multiple = pci_read_config8(MCHDEV, DRB_ROW_0 + i);<br>-<br>- if (dimm_end_64M_multiple > dimm_start_64M_multiple) {<br>- dimm_start_address &= 0x3ffffff;<br>- dimm_start_address |= dimm_start_64M_multiple << 26;<br>- read32((void *)dimm_start_address);<br>- // Set the start of the next DIMM<br>- dimm_start_64M_multiple = dimm_end_64M_multiple;<br>- }<br>- }<br>- EXTRA_DELAY;<br>-}<br>-<br>-/**<br>- * Set the mode register of all DIMMs.<br>- *<br>- * The proper CAS# latency setting is added to the mode bits specified<br>- * by the caller.<br>- *<br>- * @param jedec_mode_bits For the MRS & EMRS commands, bits 0-12 contain the<br>- * register value in JEDEC format.<br>- */<br>-static void set_ram_mode(uint16_t jedec_mode_bits)<br>-{<br>- ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK));<br>-<br>- uint32_t dram_cas_latency =<br>- pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK;<br>-<br>- switch (dram_cas_latency) {<br>- case DRT_CAS_2_5:<br>- jedec_mode_bits |= SDRAM_CAS_2_5;<br>- break;<br>-<br>- case DRT_CAS_2_0:<br>- jedec_mode_bits |= SDRAM_CAS_2_0;<br>- break;<br>-<br>- default:<br>- BUG();<br>- break;<br>- }<br>-<br>- do_ram_command(RAM_COMMAND_MRS, jedec_mode_bits);<br>-}<br>-<br>-/*-----------------------------------------------------------------------------<br>-DIMM-independent configuration functions:<br>------------------------------------------------------------------------------*/<br>-<br>-/**<br>- * Configure the E7501's DRAM Row Boundary (DRB) registers for the memory<br>- * present in the specified DIMM.<br>- *<br>- * @param dimm_log2_num_bits Specifies log2(number of bits) for each side of<br>- * the DIMM.<br>- * @param total_dram_64M_multiple Total DRAM in the system (as a multiple of<br>- * 64 MB) for DIMMs < dimm_index.<br>- * @param dimm_index Which DIMM pair is being processed<br>- * (0..MAX_DIMM_SOCKETS_PER_CHANNEL).<br>- * @return New multiple of 64 MB total DRAM in the system.<br>- */<br>-static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index)<br>-{<br>- int i;<br>-<br>- ASSERT(dimm_index < MAX_DIMM_SOCKETS_PER_CHANNEL);<br>-<br>- // DIMM sides must be at least 32 MB<br>- ASSERT(dimm_log2_num_bits.side1 >= 28);<br>- ASSERT((dimm_log2_num_bits.side2 == 0)<br>- || (dimm_log2_num_bits.side2 >= 28));<br>-<br>- // In dual-channel mode, we are called only once for each pair of DIMMs.<br>- // Each time we process twice the capacity of a single DIMM.<br>-<br>- // Convert single DIMM capacity to paired DIMM capacity<br>- // (multiply by two ==> add 1 to log2)<br>- dimm_log2_num_bits.side1++;<br>- if (dimm_log2_num_bits.side2 > 0)<br>- dimm_log2_num_bits.side2++;<br>-<br>- // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB)<br>- // to the total capacity of the system<br>- // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29<br>-<br>- total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29));<br>-<br>- // Configure the boundary address for the row on side 1<br>- pci_write_config8(MCHDEV, DRB_ROW_0 + (dimm_index << 1),<br>- total_dram_64M_multiple);<br>-<br>- // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair<br>- // (as a multiple of 64 MB) to the total capacity of the system<br>- if (dimm_log2_num_bits.side2 >= 29)<br>- total_dram_64M_multiple +=<br>- (1 << (dimm_log2_num_bits.side2 - 29));<br>-<br>- // Configure the boundary address for the row (if any) on side 2<br>- pci_write_config8(MCHDEV, DRB_ROW_1 + (dimm_index << 1),<br>- total_dram_64M_multiple);<br>-<br>- // Update boundaries for rows subsequent to these.<br>- // These settings will be overridden by a subsequent call if a populated physical slot exists<br>-<br>- for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {<br>- pci_write_config8(MCHDEV, DRB_ROW_0 + (i << 1),<br>- total_dram_64M_multiple);<br>- pci_write_config8(MCHDEV, DRB_ROW_1 + (i << 1),<br>- total_dram_64M_multiple);<br>- }<br>-<br>- return total_dram_64M_multiple;<br>-}<br>-<br>-/**<br>- * Set the E7501's DRAM row boundary addresses & its Top Of Low Memory (TOLM).<br>- *<br>- * If necessary, set up a remap window so we don't waste DRAM that ordinarily<br>- * would lie behind addresses reserved for memory-mapped I/O.<br>- *<br>- * @param ctrl PCI addresses of memory controller functions, and SMBus<br>- * addresses of DIMM slots on the mainboard.<br>- * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().<br>- */<br>-static void configure_e7501_ram_addresses(const struct mem_controller<br>- *ctrl, uint8_t dimm_mask)<br>-{<br>- int i;<br>- uint8_t total_dram_64M_multiple = 0;<br>-<br>- // Configure the E7501's DRAM row boundaries<br>- // Start by zeroing out the temporary initial configuration<br>- pci_write_config32(MCHDEV, DRB_ROW_0, 0);<br>- pci_write_config32(MCHDEV, DRB_ROW_4, 0);<br>-<br>- for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {<br>-<br>- uint16_t dimm_socket_address = ctrl->channel0[i];<br>- struct dimm_size sz;<br>-<br>- if (!(dimm_mask & (1 << i)))<br>- continue; // This DIMM not present<br>-<br>- sz = spd_get_dimm_size(dimm_socket_address);<br>-<br>- RAM_DEBUG_MESSAGE("dimm size =");<br>- RAM_DEBUG_HEX32((u32)sz.side1);<br>- RAM_DEBUG_MESSAGE(" ");<br>- RAM_DEBUG_HEX32((u32)sz.side2);<br>- RAM_DEBUG_MESSAGE("\n");<br>-<br>- if (sz.side1 == 0)<br>- die("Bad SPD value\n");<br>-<br>- total_dram_64M_multiple =<br>- configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i);<br>- }<br>-<br>- // Configure the Top Of Low Memory (TOLM) in the E7501<br>- // This address must be a multiple of 128 MB that is less than 4 GB.<br>- // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address<br>- // in the highest 5 bits.<br>-<br>- // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system.<br>- // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes<br>- // such as flash and memory-mapped I/O.<br>-<br>- // If there is more than 3 GB of DRAM, we define a remap window which<br>- // makes the DRAM "behind" the reserved region available above the top of physical<br>- // memory.<br>-<br>- // NOTE: 0xC0000000 / (64 MB) == 0x30<br>-<br>- if (total_dram_64M_multiple <= 0x30) {<br>-<br>- // <= 3 GB total RAM<br>-<br>- /* I should really adjust all of this in C after I have resources<br>- * to all of the pci devices.<br>- */<br>-<br>- // Round up to 128MB granularity<br>- // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down?<br>-<br>- uint8_t total_dram_128M_multiple =<br>- (total_dram_64M_multiple + 1) >> 1;<br>-<br>- // Convert to high 16 bits of address<br>- uint16_t top_of_low_memory =<br>- total_dram_128M_multiple << 11;<br>-<br>- pci_write_config16(MCHDEV, TOLM,<br>- top_of_low_memory);<br>-<br>- } else {<br>-<br>- // > 3 GB total RAM<br>-<br>- // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory<br>- uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0<br>- uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF<br>-<br>- // Put TOLM at 3 GB<br>-<br>- pci_write_config16(MCHDEV, TOLM, 0xc000);<br>-<br>- // Define a remap window to make the RAM that would appear from 3 GB - 4 GB<br>- // visible just beyond 4 GB or the end of physical memory, whichever is larger<br>- // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address,<br>- // (i.e. a multiple of 64 MB) in the lowest 10 bits.<br>- // NOTE: 0x100000000 / (64 MB) == 0x40<br>-<br>- if (total_dram_64M_multiple < 0x40) {<br>- remap_base = 0x40; // 0x100000000<br>- remap_limit =<br>- 0x40 + (total_dram_64M_multiple - 0x30) - 1;<br>- }<br>-<br>- pci_write_config16(MCHDEV, REMAPBASE,<br>- remap_base);<br>- pci_write_config16(MCHDEV, REMAPLIMIT,<br>- remap_limit);<br>- }<br>-}<br>-<br>-/**<br>- * Execute ECC full-speed scrub once and leave scrubber disabled.<br>- *<br>- * NOTE: All cache and stack is lost during ECC scrub loop.<br>- */<br>-static inline void __attribute__((always_inline))<br>- initialize_ecc(unsigned long ret_addr, unsigned long ret_addr2)<br>-{<br>- uint16_t scrubbed = pci_read_config16(MCHDEV, MCHCFGNS) & 0x08;<br>-<br>- if (!scrubbed) {<br>- RAM_DEBUG_MESSAGE("Initializing ECC state...\n");<br>-<br>- /* ECC scrub flushes cache-lines and stack, need to<br>- * store return address from romstage.c:main().<br>- */<br>- asm volatile(<br>- "movd %0, %%xmm0;"<br>- "movd (%0), %%xmm1;"<br>- "movd %1, %%xmm2;"<br>- "movd (%1), %%xmm3;"<br>- :: "r" (ret_addr), "r" (ret_addr2) :<br>- );<br>-<br>- /* NOTE: All cache is lost during this loop.<br>- * Make sure PCI access does not use stack.<br>- */<br>-<br>- pci_write_config16(MCHDEV, MCHCFGNS, 0x01);<br>- do {<br>- scrubbed = pci_read_config16(MCHDEV, MCHCFGNS);<br>- } while (! (scrubbed & 0x08));<br>- pci_write_config16(MCHDEV, MCHCFGNS, (scrubbed & ~0x07) | 0x04);<br>-<br>- /* Some problem remains with XIP cache from ROM, so for<br>- * now, I disable XIP and also invalidate cache (again)<br>- * before the remaining small portion of romstage.<br>- *<br>- * Adding NOPs here has unexpected results, making<br>- * the first do_printk()/vtxprintf() after ECC scrub<br>- * fail midway. Sometimes vtxprintf() dumps strings<br>- * completely but with every 4th (fourth) character as "/".<br>- *<br>- * An inlined dump to console of the same string,<br>- * before vtxprintf() call, is successful. So the<br>- * source string should be completely in cache already.<br>- *<br>- * I need to review this again with CPU microcode<br>- * update applied pre-CAR.<br>- */<br>-<br>- /* Disable and invalidate all cache. */<br>- msr_t xip_mtrr = rdmsr(MTRR_PHYS_MASK(1));<br>- xip_mtrr.lo &= ~MTRR_PHYS_MASK_VALID;<br>- invd();<br>- wrmsr(MTRR_PHYS_MASK(1), xip_mtrr);<br>- invd();<br>-<br>- RAM_DEBUG_MESSAGE("ECC state initialized.\n");<br>-<br>- /* Recover IP for return from main. */<br>- asm volatile(<br>- "movd %%xmm0, %%edi;"<br>- "movd %%xmm1, (%%edi);"<br>- "movd %%xmm2, %%edi;"<br>- "movd %%xmm3, (%%edi);"<br>- ::: "edi"<br>- );<br>-<br>-#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)<br>- unsigned int a1, a2;<br>- asm volatile("movd %%xmm2, %%eax;" : "=a" (a1) ::);<br>- asm volatile("movd %%xmm3, %%eax;" : "=a" (a2) ::);<br>- printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2);<br>- asm volatile("movd %%xmm0, %%eax;" : "=a" (a1) ::);<br>- asm volatile("movd %%xmm1, %%eax;" : "=a" (a2) ::);<br>- printk(BIOS_DEBUG, "return EIP @ %x = %x\n", a1, a2);<br>-#endif<br>- }<br>-<br>- /* Clear the ECC error bits. */<br>- pci_write_config8(RASDEV, DRAM_FERR, 0x03);<br>- pci_write_config8(RASDEV, DRAM_NERR, 0x03);<br>-<br>- /* Clear DRAM Interface error bits. */<br>- pci_write_config32(RASDEV, FERR_GLOBAL, 1 << 18);<br>- pci_write_config32(RASDEV, NERR_GLOBAL, 1 << 18);<br>-}<br>-<br>-/**<br>- * Program the DRAM Timing register (DRT) of the E7501 (except for CAS#<br>- * latency, which is assumed to have been programmed already), based on the<br>- * parameters of the various installed DIMMs.<br>- *<br>- * @param ctrl PCI addresses of memory controller functions, and SMBus<br>- * addresses of DIMM slots on the mainboard.<br>- * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().<br>- */<br>-static void configure_e7501_dram_timing(const struct mem_controller *ctrl,<br>- uint8_t dimm_mask)<br>-{<br>- int i;<br>- uint32_t dram_timing;<br>- int value;<br>- uint8_t slowest_row_precharge = 0;<br>- uint8_t slowest_ras_cas_delay = 0;<br>- uint8_t slowest_active_to_precharge_delay = 0;<br>- uint32_t current_cas_latency =<br>- pci_read_config32(MCHDEV, DRT) & DRT_CAS_MASK;<br>-<br>- // CAS# latency must be programmed beforehand<br>- ASSERT((current_cas_latency == DRT_CAS_2_0)<br>- || (current_cas_latency == DRT_CAS_2_5));<br>-<br>- // Each timing parameter is determined by the slowest DIMM<br>-<br>- for (i = 0; i < MAX_DIMM_SOCKETS; i++) {<br>- uint16_t dimm_socket_address;<br>-<br>- if (!(dimm_mask & (1 << i)))<br>- continue; // This DIMM not present<br>-<br>- if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)<br>- dimm_socket_address = ctrl->channel0[i];<br>- else<br>- dimm_socket_address =<br>- ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];<br>-<br>- value =<br>- spd_read_byte(dimm_socket_address,<br>- SPD_MIN_ROW_PRECHARGE_TIME);<br>- if (value < 0)<br>- goto hw_err;<br>- if (value > slowest_row_precharge)<br>- slowest_row_precharge = value;<br>-<br>- value =<br>- spd_read_byte(dimm_socket_address,<br>- SPD_MIN_RAS_TO_CAS_DELAY);<br>- if (value < 0)<br>- goto hw_err;<br>- if (value > slowest_ras_cas_delay)<br>- slowest_ras_cas_delay = value;<br>-<br>- value =<br>- spd_read_byte(dimm_socket_address,<br>- SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY);<br>- if (value < 0)<br>- goto hw_err;<br>- if (value > slowest_active_to_precharge_delay)<br>- slowest_active_to_precharge_delay = value;<br>- }<br>-<br>- // NOTE for timing parameters:<br>- // At 133 MHz, 1 clock == 7.52 ns<br>-<br>- /* Read the initial state */<br>- dram_timing = pci_read_config32(MCHDEV, DRT);<br>-<br>- /* Trp */<br>-<br>- // E7501 supports only 2 or 3 clocks for tRP<br>- if (slowest_row_precharge > ((22 << 2) | (2 << 0)))<br>- die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks<br>- else if (slowest_row_precharge > (15 << 2))<br>- dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks<br>- else<br>- dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks<br>-<br>- /* Trcd */<br>-<br>- // E7501 supports only 2 or 3 clocks for tRCD<br>- // Use the same value for both read & write<br>- dram_timing &= ~((1 << 3) | (3 << 1));<br>- if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0)))<br>- die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks<br>- else if (slowest_ras_cas_delay > (15 << 2))<br>- dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks<br>- else<br>- dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks<br>-<br>- /* Tras */<br>-<br>- // E7501 supports only 5, 6, or 7 clocks for tRAS<br>- // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns<br>- dram_timing &= ~(3 << 9);<br>-<br>- if (slowest_active_to_precharge_delay > 52)<br>- die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks<br>- else if (slowest_active_to_precharge_delay > 45)<br>- dram_timing |= (0 << 9); // 46-52 ns: 7 clocks<br>- else if (slowest_active_to_precharge_delay > 37)<br>- dram_timing |= (1 << 9); // 38-45 ns: 6 clocks<br>- else<br>- dram_timing |= (2 << 9); // < 38 ns: 5 clocks<br>-<br>- /* Trd */<br>-<br>- /* Set to a 7 clock read delay. This is for 133MHz<br>- * with a CAS latency of 2.5 if 2.0 a 6 clock<br>- * delay is good */<br>-<br>- dram_timing &= ~(7 << 24); // 7 clocks<br>- if (current_cas_latency == DRT_CAS_2_0)<br>- dram_timing |= (1 << 24); // 6 clocks<br>-<br>- /*<br>- * Back to Back Read-Write Turn Around<br>- */<br>- /* Set to a 5 clock back to back read to write turn around.<br>- * 4 is a good delay if the CAS latency is 2.0 */<br>-<br>- dram_timing &= ~(1 << 28); // 5 clocks<br>- if (current_cas_latency == DRT_CAS_2_0)<br>- dram_timing |= (1 << 28); // 4 clocks<br>-<br>- pci_write_config32(MCHDEV, DRT, dram_timing);<br>-<br>- return;<br>-<br>- hw_err:<br>- die(SPD_ERROR);<br>-}<br>-<br>-/**<br>- * Determine the shortest CAS# latency that the E7501 and all DIMMs have in<br>- * common, and program the E7501 to use it.<br>- *<br>- * @param ctrl PCI addresses of memory controller functions, and SMBus<br>- * addresses of DIMM slots on the mainboard.<br>- * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().<br>- */<br>-static void configure_e7501_cas_latency(const struct mem_controller *ctrl,<br>- uint8_t dimm_mask)<br>-{<br>- int i;<br>- int value;<br>- uint32_t dram_timing;<br>- uint16_t dram_read_timing;<br>- uint32_t dword;<br>-<br>- // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format<br>- // NOTE: E7501 supports only 2.0 and 2.5<br>- uint32_t system_compatible_cas_latencies =<br>- SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5;<br>- uint32_t current_cas_latency;<br>- uint32_t dimm_compatible_cas_latencies;<br>-<br>- for (i = 0; i < MAX_DIMM_SOCKETS; i++) {<br>-<br>- uint16_t dimm_socket_address;<br>-<br>- if (!(dimm_mask & (1 << i)))<br>- continue; // This DIMM not usable<br>-<br>- if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)<br>- dimm_socket_address = ctrl->channel0[i];<br>- else<br>- dimm_socket_address =<br>- ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];<br>-<br>- value =<br>- spd_read_byte(dimm_socket_address,<br>- SPD_ACCEPTABLE_CAS_LATENCIES);<br>- if (value < 0)<br>- goto hw_err;<br>-<br>- dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM<br>- current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM<br>-<br>- // Can we support the highest CAS# latency?<br>-<br>- value =<br>- spd_read_byte(dimm_socket_address,<br>- SPD_MIN_CYCLE_TIME_AT_CAS_MAX);<br>- if (value < 0)<br>- goto hw_err;<br>-<br>- // NOTE: At 133 MHz, 1 clock == 7.52 ns<br>- if (value > 0x75) {<br>- // Our bus is too fast for this CAS# latency<br>- // Remove it from the bitmask of those supported by the DIMM that are compatible<br>- dimm_compatible_cas_latencies &= ~current_cas_latency;<br>- }<br>- // Can we support the next-highest CAS# latency (max - 0.5)?<br>-<br>- current_cas_latency >>= 1;<br>- if (current_cas_latency != 0) {<br>- value =<br>- spd_read_byte(dimm_socket_address,<br>- SPD_SDRAM_CYCLE_TIME_2ND);<br>- if (value < 0)<br>- goto hw_err;<br>- if (value > 0x75)<br>- dimm_compatible_cas_latencies &=<br>- ~current_cas_latency;<br>- }<br>- // Can we support the next-highest CAS# latency (max - 1.0)?<br>- current_cas_latency >>= 1;<br>- if (current_cas_latency != 0) {<br>- value =<br>- spd_read_byte(dimm_socket_address,<br>- SPD_SDRAM_CYCLE_TIME_3RD);<br>- if (value < 0)<br>- goto hw_err;<br>- if (value > 0x75)<br>- dimm_compatible_cas_latencies &=<br>- ~current_cas_latency;<br>- }<br>- // Restrict the system to CAS# latencies compatible with this DIMM<br>- system_compatible_cas_latencies &=<br>- dimm_compatible_cas_latencies;<br>-<br>- /* go to the next DIMM */<br>- }<br>-<br>- /* After all of the arduous calculation setup with the fastest<br>- * cas latency I can use.<br>- */<br>-<br>- dram_timing = pci_read_config32(MCHDEV, DRT);<br>- dram_timing &= ~(DRT_CAS_MASK);<br>-<br>- dram_read_timing =<br>- pci_read_config16(MCHDEV, DRDCTL);<br>- dram_read_timing &= 0xF000;<br>-<br>- if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) {<br>- dram_timing |= DRT_CAS_2_0;<br>- dram_read_timing |= 0x0222;<br>- } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) {<br>-<br>- uint32_t dram_row_attributes =<br>- pci_read_config32(MCHDEV, DRA);<br>-<br>- dram_timing |= DRT_CAS_2_5;<br>-<br>- // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly<br>- // different value if all DIMM slots are populated<br>-<br>- if ((dram_row_attributes & 0xff)<br>- && (dram_row_attributes & 0xff00)<br>- && (dram_row_attributes & 0xff0000)<br>- && (dram_row_attributes & 0xff000000)) {<br>-<br>- // All slots populated<br>- dram_read_timing |= 0x0882;<br>- } else {<br>- // Some unpopulated slots<br>- dram_read_timing |= 0x0662;<br>- }<br>- } else<br>- die("No CAS# latencies compatible with all DIMMs!!\n");<br>-<br>- pci_write_config32(MCHDEV, DRT, dram_timing);<br>-<br>- /* set master DLL reset */<br>- dword = pci_read_config32(MCHDEV, 0x88);<br>- dword |= (1 << 26);<br>- pci_write_config32(MCHDEV, 0x88, dword);<br>- /* patch try register 88 is undocumented tnz */<br>- dword &= 0x0ca17fff;<br>- dword |= 0xd14a5000;<br>- pci_write_config32(MCHDEV, 0x88, dword);<br>-<br>- pci_write_config16(MCHDEV, DRDCTL,<br>- dram_read_timing);<br>-<br>- /* clear master DLL reset */<br>- dword = pci_read_config32(MCHDEV, 0x88);<br>- dword &= ~(1 << 26);<br>- pci_write_config32(MCHDEV, 0x88, dword);<br>-<br>- return;<br>-<br>-hw_err:<br>- die(SPD_ERROR);<br>-}<br>-<br>-/**<br>- * Configure the refresh interval so that we refresh no more often than<br>- * required by the "most needy" DIMM. Also disable ECC if any of the DIMMs<br>- * don't support it.<br>- *<br>- * @param ctrl PCI addresses of memory controller functions, and SMBus<br>- * addresses of DIMM slots on the mainboard.<br>- * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().<br>- */<br>-static void configure_e7501_dram_controller_mode(const struct<br>- mem_controller *ctrl,<br>- uint8_t dimm_mask)<br>-{<br>- int i;<br>-<br>- // Initial settings<br>- uint32_t controller_mode =<br>- pci_read_config32(MCHDEV, DRC);<br>- uint32_t system_refresh_mode = (controller_mode >> 8) & 7;<br>-<br>- // Code below assumes that most aggressive settings are in<br>- // force when we are called, either via E7501 reset defaults<br>- // or by sdram_set_registers():<br>- // - ECC enabled<br>- // - No refresh<br>-<br>- ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC<br>- ASSERT(!(controller_mode & (7 << 8))); // Refresh<br>-<br>- /* Walk through _all_ dimms and find the least-common denominator for:<br>- * - ECC support<br>- * - refresh rates<br>- */<br>-<br>- for (i = 0; i < MAX_DIMM_SOCKETS; i++) {<br>-<br>- uint32_t dimm_refresh_mode;<br>- int value;<br>- uint16_t dimm_socket_address;<br>-<br>- if (!(dimm_mask & (1 << i))) {<br>- continue; // This DIMM not usable<br>- }<br>-<br>- if (i < MAX_DIMM_SOCKETS_PER_CHANNEL)<br>- dimm_socket_address = ctrl->channel0[i];<br>- else<br>- dimm_socket_address =<br>- ctrl->channel1[i -<br>- MAX_DIMM_SOCKETS_PER_CHANNEL];<br>-<br>- // Disable ECC mode if any one of the DIMMs does not support ECC<br>- // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.<br>-<br>- value =<br>- spd_read_byte(dimm_socket_address,<br>- SPD_DIMM_CONFIG_TYPE);<br>- die_on_spd_error(value);<br>- if (value != ERROR_SCHEME_ECC) {<br>- controller_mode &= ~(3 << 20);<br>- }<br>-<br>- value = spd_read_byte(dimm_socket_address, SPD_REFRESH);<br>- die_on_spd_error(value);<br>- value &= 0x7f; // Mask off self-refresh bit<br>- if (value > MAX_SPD_REFRESH_RATE) {<br>- printk(BIOS_ERR, "unsupported refresh rate\n");<br>- continue;<br>- }<br>- // Get the appropriate E7501 refresh mode for this DIMM<br>- dimm_refresh_mode = refresh_rate_map[value];<br>- if (dimm_refresh_mode > 7) {<br>- printk(BIOS_ERR, "unsupported refresh rate\n");<br>- continue;<br>- }<br>- // If this DIMM requires more frequent refresh than others,<br>- // update the system setting<br>- if (refresh_frequency[dimm_refresh_mode] ><br>- refresh_frequency[system_refresh_mode])<br>- system_refresh_mode = dimm_refresh_mode;<br>-<br>-#ifdef SUSPICIOUS_LOOKING_CODE<br>-// SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller<br>-// than the clock period of the memory controller. Also, no other northbridge<br>-// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME.<br>-<br>- // Switch to 2 clocks for address/command if required by any one of the DIMMs<br>- // NOTE: At 133 MHz, 1 clock == 7.52 ns<br>- value =<br>- spd_read_byte(dimm_socket_address,<br>- SPD_CMD_SIGNAL_INPUT_HOLD_TIME);<br>- die_on_spd_error(value);<br>- if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */<br>- controller_mode &= ~(1 << 16); /* Use two clock cycles instead of one */<br>- }<br>-#endif<br>-<br>- /* go to the next DIMM */<br>- }<br>-<br>- controller_mode |= (system_refresh_mode << 8);<br>-<br>- // Configure the E7501<br>- pci_write_config32(MCHDEV, DRC, controller_mode);<br>-}<br>-<br>-/**<br>- * Configure the E7501's DRAM Row Attributes (DRA) registers based on DIMM<br>- * parameters read via SPD. This tells the controller the width of the SDRAM<br>- * chips on each DIMM side (x4 or x8) and the page size of each DIMM side<br>- * (4, 8, 16, or 32 KB).<br>- *<br>- * @param ctrl PCI addresses of memory controller functions, and SMBus<br>- * addresses of DIMM slots on the mainboard.<br>- * @param dimm_mask Bitmask of populated DIMMs, spd_get_supported_dimms().<br>- */<br>-static void configure_e7501_row_attributes(const struct mem_controller<br>- *ctrl, uint8_t dimm_mask)<br>-{<br>- int i;<br>- uint32_t row_attributes = 0;<br>-<br>- for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {<br>-<br>- uint16_t dimm_socket_address = ctrl->channel0[i];<br>- struct dimm_size page_size;<br>- struct dimm_size sdram_width;<br>-<br>- if (!(dimm_mask & (1 << i)))<br>- continue; // This DIMM not usable<br>-<br>- // Get the relevant parameters via SPD<br>- page_size = sdram_spd_get_page_size(dimm_socket_address);<br>- sdram_width = sdram_spd_get_width(dimm_socket_address);<br>-<br>- // Update the DRAM Row Attributes.<br>- // Page size is encoded as log2(page size in bits) - log2(8 Kb)<br>- // NOTE: 8 Kb = 2^13<br>- row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row<br>-<br>- if (sdram_width.side2 > 0)<br>- row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD<br>-<br>- // Set x4 flags if appropriate<br>- if (sdram_width.side1 == 4) {<br>- row_attributes |= 0x08 << (i << 3);<br>- }<br>-<br>- if (sdram_width.side2 == 4) {<br>- row_attributes |= 0x08 << ((i << 3) + 4);<br>- }<br>-<br>- /* go to the next DIMM */<br>- }<br>-<br>- /* Write the new row attributes register */<br>- pci_write_config32(MCHDEV, DRA, row_attributes);<br>-}<br>-<br>-/*<br>- * Enable clock signals for populated DIMM sockets and disable them for<br>- * unpopulated sockets (to reduce EMI).<br>- *<br>- * @param dimm_mask Bitmask of populated DIMMs, see spd_get_supported_dimms().<br>- */<br>-static void enable_e7501_clocks(uint8_t dimm_mask)<br>-{<br>- int i;<br>- uint8_t clock_disable = pci_read_config8(MCHDEV, CKDIS);<br>-<br>- pci_write_config8(MCHDEV, 0x8e, 0xb0);<br>-<br>- for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) {<br>-<br>- uint8_t socket_mask = 1 << i;<br>-<br>- if (dimm_mask & socket_mask)<br>- clock_disable &= ~socket_mask; // DIMM present, enable clock<br>- else<br>- clock_disable |= socket_mask; // DIMM absent, disable clock<br>- }<br>-<br>- pci_write_config8(MCHDEV, CKDIS, clock_disable);<br>-}<br>-<br>-/* DIMM-dependent configuration functions */<br>-<br>-/**<br>- * DDR Receive FIFO RE-Sync (?)<br>- */<br>-static void RAM_RESET_DDR_PTR(void)<br>-{<br>- uint8_t byte;<br>- byte = pci_read_config8(MCHDEV, 0x88);<br>- byte |= (1 << 4);<br>- pci_write_config8(MCHDEV, 0x88, byte);<br>-<br>- byte = pci_read_config8(MCHDEV, 0x88);<br>- byte &= ~(1 << 4);<br>- pci_write_config8(MCHDEV, 0x88, byte);<br>-}<br>-<br>-/**<br>- * Copy 64 bytes from one location to another.<br>- *<br>- * @param src_addr TODO<br>- * @param dst_addr TODO<br>- */<br>-static void write_8dwords(const uint32_t *src_addr, u8 *dst_addr)<br>-{<br>- int i;<br>- for (i = 0; i < 8; i++) {<br>- write32(dst_addr, *src_addr);<br>- src_addr++;<br>- dst_addr += sizeof(uint32_t);<br>- }<br>-}<br>-<br>-/**<br>- * Set the E7501's (undocumented) RCOMP registers.<br>- *<br>- * Per the 855PM datasheet and IXP2800 HW Initialization Reference Manual,<br>- * RCOMP registers appear to affect drive strength, pullup/pulldown offset,<br>- * and slew rate of various signal groups.<br>- *<br>- * Comments below are conjecture based on apparent similarity between the<br>- * E7501 and these two chips.<br>- */<br>-static void rcomp_copy_registers(void)<br>-{<br>- uint32_t dword;<br>- uint8_t strength_control;<br>-<br>- RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");<br>-<br>- /* Begin to write the RCOMP registers */<br>- write8(RCOMP_MMIO + 0x2c, 0x0);<br>-<br>- // Set CMD and DQ/DQS strength to 2x (?)<br>- strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0x88;<br>- strength_control |= 0x40;<br>- write8(RCOMP_MMIO + DQCMDSTR, strength_control);<br>- write_8dwords(slew_2x, RCOMP_MMIO + 0x80);<br>- write16(RCOMP_MMIO + 0x42, 0);<br>-<br>- // Set CMD and DQ/DQS strength to 2x (?)<br>- strength_control = read8(RCOMP_MMIO + DQCMDSTR) & 0xF8;<br>- strength_control |= 0x04;<br>- write8(RCOMP_MMIO + DQCMDSTR, strength_control);<br>- write_8dwords(slew_2x, RCOMP_MMIO + 0x60);<br>- write16(RCOMP_MMIO + 0x40, 0);<br>-<br>- // Set RCVEnOut# strength to 2x (?)<br>- strength_control = read8(RCOMP_MMIO + RCVENSTR) & 0xF8;<br>- strength_control |= 0x04;<br>- write8(RCOMP_MMIO + RCVENSTR, strength_control);<br>- write_8dwords(slew_2x, RCOMP_MMIO + 0x1c0);<br>- write16(RCOMP_MMIO + 0x50, 0);<br>-<br>- // Set CS# strength for x4 SDRAM to 2x (?)<br>- strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x88;<br>- strength_control |= 0x04;<br>- write8(RCOMP_MMIO + CSBSTR, strength_control);<br>- write_8dwords(slew_2x, RCOMP_MMIO + 0x140);<br>- write16(RCOMP_MMIO + 0x48, 0);<br>-<br>- // Set CS# strength for x4 SDRAM to 2x (?)<br>- strength_control = read8(RCOMP_MMIO + CSBSTR) & 0x8F;<br>- strength_control |= 0x40;<br>- write8(RCOMP_MMIO + CSBSTR, strength_control);<br>- write_8dwords(slew_2x, RCOMP_MMIO + 0x160);<br>- write16(RCOMP_MMIO + 0x4a, 0);<br>-<br>- // Set CKE strength for x4 SDRAM to 2x (?)<br>- strength_control = read8(RCOMP_MMIO + CKESTR) & 0x88;<br>- strength_control |= 0x04;<br>- write8(RCOMP_MMIO + CKESTR, strength_control);<br>- write_8dwords(slew_2x, RCOMP_MMIO + 0xa0);<br>- write16(RCOMP_MMIO + 0x44, 0);<br>-<br>- // Set CKE strength for x4 SDRAM to 2x (?)<br>- strength_control = read8(RCOMP_MMIO + CKESTR) & 0x8F;<br>- strength_control |= 0x40;<br>- write8(RCOMP_MMIO + CKESTR, strength_control);<br>- write_8dwords(slew_2x, RCOMP_MMIO + 0xc0);<br>- write16(RCOMP_MMIO + 0x46, 0);<br>-<br>- // Set CK strength for x4 SDRAM to 1x (?)<br>- strength_control = read8(RCOMP_MMIO + CKSTR) & 0x88;<br>- strength_control |= 0x01;<br>- write8(RCOMP_MMIO + CKSTR, strength_control);<br>- write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x180);<br>- write16(RCOMP_MMIO + 0x4c, 0);<br>-<br>- // Set CK strength for x4 SDRAM to 1x (?)<br>- strength_control = read8(RCOMP_MMIO + CKSTR) & 0x8F;<br>- strength_control |= 0x10;<br>- write8(RCOMP_MMIO + CKSTR, strength_control);<br>- write_8dwords(pull_updown_offset_table, RCOMP_MMIO + 0x1a0);<br>- write16(RCOMP_MMIO + 0x4e, 0);<br>-<br>- dword = read32(RCOMP_MMIO + 0x400);<br>- dword &= 0x7f7fffff;<br>- write32(RCOMP_MMIO + 0x400, dword);<br>-<br>- dword = read32(RCOMP_MMIO + 0x408);<br>- dword &= 0x7f7fffff;<br>- write32(RCOMP_MMIO + 0x408, dword);<br>-}<br>-<br>-static void ram_set_rcomp_regs(void)<br>-{<br>- /* Set the RCOMP MMIO base address */<br>- mchtest_control(RCOMP_BAR_ENABLE);<br>- pci_write_config32(MCHDEV, SMRBASE, (uintptr_t)RCOMP_MMIO);<br>-<br>- /* Block RCOMP updates while we configure the registers */<br>- rcomp_smr_control(RCOMP_HOLD);<br>- rcomp_copy_registers();<br>- d060_control(D060_CMD_0);<br>- mchtest_control(MCHTST_CMD_0);<br>-<br>- uint8_t revision = pci_read_config8(MCHDEV, 0x08);<br>- if (revision >= 3) {<br>- rcomp_smr_control(RCOMP_SMR_00);<br>- rcomp_smr_control(RCOMP_SMR_01);<br>- }<br>- rcomp_smr_control(RCOMP_RELEASE);<br>-<br>- /* Wait 40 usec */<br>- SLOW_DOWN_IO;<br>-<br>- /* Clear the RCOMP MMIO base address */<br>- pci_write_config32(MCHDEV, SMRBASE, 0);<br>- mchtest_control(RCOMP_BAR_DISABLE);<br>-}<br>-<br>-/*-----------------------------------------------------------------------------<br>-Public interface:<br>------------------------------------------------------------------------------*/<br>-<br>-/**<br>- * Go through the JEDEC initialization sequence for all DIMMs, then enable<br>- * refresh and initialize ECC and memory to zero. Upon exit, SDRAM is up<br>- * and running.<br>- *<br>- * @param ctrl PCI addresses of memory controller functions, and SMBus<br>- * addresses of DIMM slots on the mainboard.<br>- */<br>-static void sdram_enable(const struct mem_controller *ctrl)<br>-{<br>- uint8_t dimm_mask = pci_read_config16(MCHDEV, SKPD);<br>- uint32_t dram_controller_mode;<br>-<br>- if (dimm_mask == 0)<br>- return;<br>-<br>- /* 1 & 2 Power up and start clocks */<br>- RAM_DEBUG_MESSAGE("Ram Enable 1\n");<br>- RAM_DEBUG_MESSAGE("Ram Enable 2\n");<br>-<br>- /* A 200us delay is needed */<br>- DO_DELAY; EXTRA_DELAY;<br>-<br>- /* 3. Apply NOP */<br>- RAM_DEBUG_MESSAGE("Ram Enable 3\n");<br>- do_ram_command(RAM_COMMAND_NOP, 0);<br>-<br>- /* 4 Precharge all */<br>- RAM_DEBUG_MESSAGE("Ram Enable 4\n");<br>- do_ram_command(RAM_COMMAND_PRECHARGE, 0);<br>- /* wait until the all banks idle state... */<br>-<br>- /* 5. Issue EMRS to enable DLL */<br>- RAM_DEBUG_MESSAGE("Ram Enable 5\n");<br>- do_ram_command(RAM_COMMAND_EMRS,<br>- SDRAM_EXTMODE_DLL_ENABLE |<br>- SDRAM_EXTMODE_DRIVE_NORMAL);<br>-<br>- /* 6. Reset DLL */<br>- RAM_DEBUG_MESSAGE("Ram Enable 6\n");<br>- set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);<br>- EXTRA_DELAY;<br>- /* Ensure a 200us delay between the DLL reset in step 6 and the final<br>- * mode register set in step 9.<br>- * Infineon needs this before any other command is sent to the ram.<br>- */<br>- DO_DELAY; EXTRA_DELAY;<br>-<br>- /* 7 Precharge all */<br>- RAM_DEBUG_MESSAGE("Ram Enable 7\n");<br>- do_ram_command(RAM_COMMAND_PRECHARGE, 0);<br>-<br>- /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */<br>- /* And for good luck 6 more CBRs */<br>- RAM_DEBUG_MESSAGE("Ram Enable 8\n");<br>- int i;<br>- for (i = 0; i < 8; i++)<br>- do_ram_command(RAM_COMMAND_CBR, 0);<br>-<br>- /* 9 mode register set */<br>- RAM_DEBUG_MESSAGE("Ram Enable 9\n");<br>- set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);<br>-<br>- /* 10 DDR Receive FIFO RE-Sync */<br>- RAM_DEBUG_MESSAGE("Ram Enable 10\n");<br>- RAM_RESET_DDR_PTR();<br>- EXTRA_DELAY;<br>-<br>- /* 11 normal operation */<br>- RAM_DEBUG_MESSAGE("Ram Enable 11\n");<br>- do_ram_command(RAM_COMMAND_NORMAL, 0);<br>-<br>- // Reconfigure the row boundaries and Top of Low Memory<br>- // to match the true size of the DIMMs<br>- configure_e7501_ram_addresses(ctrl, dimm_mask);<br>-<br>- /* Finally enable refresh */<br>- dram_controller_mode = pci_read_config32(MCHDEV, DRC);<br>- dram_controller_mode |= (1 << 29);<br>- pci_write_config32(MCHDEV, DRC, dram_controller_mode);<br>- EXTRA_DELAY;<br>-}<br>-<br>-/**<br>- * @param ctrl PCI addresses of memory controller functions, and SMBus<br>- * addresses of DIMM slots on the mainboard.<br>- */<br>-static void sdram_post_ecc(const struct mem_controller *ctrl)<br>-{<br>- /* Fast CS# Enable. */<br>- uint32_t dram_controller_mode = pci_read_config32(MCHDEV, DRC);<br>- dram_controller_mode = pci_read_config32(MCHDEV, DRC);<br>- dram_controller_mode |= (1 << 17);<br>- pci_write_config32(MCHDEV, DRC, dram_controller_mode);<br>-}<br>-<br>-/**<br>- * Configure SDRAM controller parameters that depend on characteristics of the<br>- * DIMMs installed in the system. These characteristics are read from the<br>- * DIMMs via the standard Serial Presence Detect (SPD) interface.<br>- *<br>- * @param ctrl PCI addresses of memory controller functions, and SMBus<br>- * addresses of DIMM slots on the mainboard.<br>- */<br>-static void sdram_set_spd_registers(const struct mem_controller *ctrl)<br>-{<br>- uint8_t dimm_mask;<br>-<br>- RAM_DEBUG_MESSAGE("Reading SPD data...\n");<br>-<br>- dimm_mask = spd_get_supported_dimms(ctrl);<br>-<br>- if (dimm_mask == 0) {<br>- printk(BIOS_DEBUG, "No usable memory for this controller\n");<br>- } else {<br>- enable_e7501_clocks(dimm_mask);<br>-<br>- RAM_DEBUG_MESSAGE("setting based on SPD data...\n");<br>-<br>- configure_e7501_row_attributes(ctrl, dimm_mask);<br>- configure_e7501_dram_controller_mode(ctrl, dimm_mask);<br>- configure_e7501_cas_latency(ctrl, dimm_mask);<br>- RAM_RESET_DDR_PTR();<br>-<br>- configure_e7501_dram_timing(ctrl, dimm_mask);<br>- DO_DELAY;<br>- RAM_DEBUG_MESSAGE("done\n");<br>- }<br>-<br>- /* NOTE: configure_e7501_ram_addresses() is NOT called here.<br>- * We want to keep the default 64 MB/row mapping until sdram_enable() is called,<br>- * even though the default mapping is almost certainly incorrect.<br>- * The default mapping makes it easy to initialize all of the DIMMs<br>- * even if the total system memory is > 4 GB.<br>- *<br>- * Save the dimm_mask for when sdram_enable is called, so it can call<br>- * configure_e7501_ram_addresses() without having to regenerate the bitmask<br>- * of usable DIMMs.<br>- */<br>- pci_write_config16(MCHDEV, SKPD, dimm_mask);<br>-}<br>-<br>-/**<br>- * Do basic RAM setup that does NOT depend on serial presence detect<br>- * information (i.e. independent of DIMM specifics).<br>- *<br>- * @param ctrl PCI addresses of memory controller functions, and SMBus<br>- * addresses of DIMM slots on the mainboard.<br>- */<br>-static void sdram_set_registers(const struct mem_controller *ctrl)<br>-{<br>- uint32_t dword;<br>- uint16_t word;<br>- uint8_t byte;<br>-<br>- ram_set_rcomp_regs();<br>-<br>- /* Enable 0:0.1, 0:2.1 */<br>- word = pci_read_config16(MCHDEV, DVNP);<br>- word &= ~0x05;<br>- pci_write_config16(MCHDEV, DVNP, word);<br>-<br>- /* Disable high-memory remap (power-on defaults, really) */<br>- pci_write_config16(MCHDEV, REMAPBASE, 0x03ff);<br>- pci_write_config16(MCHDEV, REMAPLIMIT, 0x0);<br>-<br>- /* Disable legacy MMIO (0xC0000-0xEFFFF is DRAM) */<br>- int i;<br>- pci_write_config8(MCHDEV, PAM_0, 0x30);<br>- for (i = 1; i <= 6; i++)<br>- pci_write_config8(MCHDEV, PAM_0 + i, 0x33);<br>-<br>- /* Conservatively say each row has 64MB of ram, we will fix this up later<br>- * Initial TOLM 8 rows 64MB each (1<<3 * 1<<26) >> 16 = 1<<13<br>- *<br>- * FIXME: Hard-coded limit to first four rows to prevent overlap!<br>- */<br>- pci_write_config32(MCHDEV, DRB_ROW_0, 0x04030201);<br>- pci_write_config32(MCHDEV, DRB_ROW_4, 0x04040404);<br>- //pci_write_config32(MCHDEV, DRB_ROW_4, 0x08070605);<br>- pci_write_config16(MCHDEV, TOLM, (1<<13));<br>-<br>- /* DIMM clocks off */<br>- pci_write_config8(MCHDEV, CKDIS, 0xff);<br>-<br>- /* reset row attributes */<br>- pci_write_config32(MCHDEV, DRA, 0x0);<br>-<br>- // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and<br>- // Back-to-Back Write-Read Turnaround. All others are configured based on SPD.<br>- dword = pci_read_config32(MCHDEV, DRT);<br>- dword &= 0xC7F8FFFF;<br>- dword |= (0x28<<24)|(0x03<<16);<br>- pci_write_config32(MCHDEV, DRT, dword);<br>-<br>- dword = pci_read_config32(MCHDEV, DRC);<br>- dword &= 0xffcef8f7;<br>- dword |= 0x00210008;<br>- pci_write_config32(MCHDEV, DRC, dword);<br>-<br>- /* Undocumented */<br>- pci_write_config8(MCHDEV, 0x88, 0x80);<br>-<br>- /* Undocumented. Set much later in vendor BIOS. */<br>- byte = pci_read_config8(MCHDEV, 0xd9);<br>- byte &= ~0x60;<br>- pci_write_config8(MCHDEV, 0xd9, byte);<br>-<br>-#ifdef SUSPICIOUS_LOOKING_CODE<br>- /* This will access D2:F0:0x50, is this correct??<br>- * Vendor BIOS reads Device ID before this is set.<br>- * Undocumented in the p64h2 PCI-X bridge datasheet.<br>- */<br>- byte = pci_read_config8(PCI_DEV(0,2,0), 0x50);<br>- byte &= 0xcf;<br>- byte |= 0x30<br>- pci_write_config8(PCI_DEV(0,2,0), 0x50, byte);<br>-#endif<br>-<br>- uint8_t revision = pci_read_config8(MCHDEV, 0x08);<br>- if (revision >= 3)<br>- d060_control(D060_CMD_1);<br>-}<br>-<br>-/**<br>- *<br>- *<br>- */<br>-void e7505_mch_init(const struct mem_controller *memctrl)<br>-{<br>- RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");<br>- DUMPNORTH();<br>-<br>- sdram_set_registers(memctrl);<br>- sdram_set_spd_registers(memctrl);<br>- sdram_enable(memctrl);<br>-}<br>-<br>-uintptr_t restore_top_of_low_cacheable(void)<br>-{<br>- u32 tolm = (pci_read_config16(MCHDEV, TOLM) & ~0x7ff) << 16;<br>- return tolm;<br>-}<br>-<br>-/**<br>- * Scrub and reset error counts for ECC dimms.<br>- *<br>- * NOTE: this will invalidate cache and disable XIP cache for the<br>- * short remaining part of romstage.<br>- */<br>-void e7505_mch_scrub_ecc(unsigned long ret_addr)<br>-{<br>- unsigned long ret_addr2 = (unsigned long)((unsigned long*)&ret_addr-1);<br>- if ((pci_read_config32(MCHDEV, DRC)>>20 & 3) == 2)<br>- initialize_ecc(ret_addr, ret_addr2);<br>-}<br>-<br>-void e7505_mch_done(const struct mem_controller *memctrl)<br>-{<br>- sdram_post_ecc(memctrl);<br>-<br>- RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");<br>- DUMPNORTH();<br>-}<br>-<br>-int e7505_mch_is_ready(void)<br>-{<br>- uint32_t dword = pci_read_config32(MCHDEV, DRC);<br>- return !!(dword & DRC_DONE);<br>-}<br>diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h<br>deleted file mode 100644<br>index 979ae0a..0000000<br>--- a/src/northbridge/intel/e7505/raminit.h<br>+++ /dev/null<br>@@ -1,27 +0,0 @@<br>-#ifndef RAMINIT_H<br>-#define RAMINIT_H<br>-<br>-#define MAX_DIMM_SOCKETS_PER_CHANNEL 4<br>-#define MAX_NUM_CHANNELS 2<br>-#define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL)<br>-<br>-struct mem_controller {<br>- pci_devfn_t d0, d0f1; // PCI bus/device/fcns of E7501 memory controller<br>-<br>- // SMBus addresses of DIMM slots for each channel,<br>- // in order from closest to MCH to furthest away<br>- // 0 == not present<br>- uint16_t channel0[MAX_DIMM_SOCKETS_PER_CHANNEL];<br>- uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL];<br>-};<br>-<br>-void e7505_mch_init(const struct mem_controller *memctrl);<br>-void e7505_mch_scrub_ecc(unsigned long ret_addr);<br>-void e7505_mch_done(const struct mem_controller *memctrl);<br>-int e7505_mch_is_ready(void);<br>-<br>-<br>-/* Mainboard exports this. */<br>-int spd_read_byte(unsigned device, unsigned address);<br>-<br>-#endif /* RAMINIT_H */<br>diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h<br>deleted file mode 100644<br>index b576cc1..0000000<br>--- a/src/southbridge/intel/i82870/82870.h<br>+++ /dev/null<br>@@ -1,14 +0,0 @@<br>-/* for io apic 1461 */<br>-#define MBAR 0x10<br>-#define ABAR 0x40<br>-<br>-/* for pci bridge 1460 */<br>-#define MTT 0x042<br>-#define HCCR 0x0f0<br>-#define ACNF 0x0e0<br>-#define STRP 0x44 // Strap status register<br>-<br>-#define STRP_EN133 0x0001 // 133 MHz-capable (Px_133EN)<br>-#define STRP_HPCAP 0x0002 // Hot-plug capable (Hx_SLOT zero/nonzero)<br>-<br>-#define ACNF_SYNCPH 0x0010 // PCI(-X) input clock is synchronous to hub input clock<br>diff --git a/src/southbridge/intel/i82870/Kconfig b/src/southbridge/intel/i82870/Kconfig<br>deleted file mode 100644<br>index b56113b..0000000<br>--- a/src/southbridge/intel/i82870/Kconfig<br>+++ /dev/null<br>@@ -1,2 +0,0 @@<br>-config SOUTHBRIDGE_INTEL_I82870<br>- bool<br>diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc<br>deleted file mode 100644<br>index 790bd01..0000000<br>--- a/src/southbridge/intel/i82870/Makefile.inc<br>+++ /dev/null<br>@@ -1,7 +0,0 @@<br>-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y)<br>-<br>-ramstage-y += ioapic.c<br>-ramstage-y += pcibridge.c<br>-#ramstage-y += pci_parity.c<br>-<br>-endif<br>diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c<br>deleted file mode 100644<br>index da7da5e..0000000<br>--- a/src/southbridge/intel/i82870/ioapic.c<br>+++ /dev/null<br>@@ -1,97 +0,0 @@<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <pc80/mc146818rtc.h><br>-#include <assert.h><br>-#include "82870.h"<br>-<br>-static int num_p64h2_ioapics = 0;<br>-<br>-static void p64h2_ioapic_enable(device_t dev)<br>-{<br>- /* We have to enable MEM and Bus Master for IOAPIC */<br>- uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;<br>-<br>- pci_write_config16(dev, PCI_COMMAND, command);<br>-}<br>-<br>-/**<br>- * Configure one of the IOAPICs in a P64H2.<br>- *<br>- * Note that a PCI bus scan will detect both IOAPICs, so this function<br>- * will be called twice for each P64H2 in the system.<br>- *<br>- * @param dev PCI bus/device/function of P64H2 IOAPIC.<br>- * NOTE: There are two IOAPICs per P64H2, at D28:F0 and D30:F0.<br>- */<br>-static void p64h2_ioapic_init(device_t dev)<br>-{<br>- uint32_t memoryBase;<br>- int apic_index, apic_id;<br>-<br>- volatile uint32_t* pIndexRegister; /* io apic io memory space command address */<br>- volatile uint32_t* pWindowRegister; /* io apic io memory space data address */<br>-<br>- apic_index = num_p64h2_ioapics;<br>- num_p64h2_ioapics++;<br>-<br>- // A note on IOAPIC addresses:<br>- // 0 and 1 are used for the local APICs of the dual virtual<br>- // (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).<br>- // 6 and 7 are used for the local APICs of the dual virtual<br>- // (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).<br>- // 2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)<br>-<br>- // Map APIC index into APIC ID<br>- // IDs 3, 4, 5, and 8+ are available (see above note)<br>-<br>- if (apic_index < 3)<br>- apic_id = apic_index + 3;<br>- else<br>- apic_id = apic_index + 5;<br>-<br>- ASSERT(apic_id < 16); // ID is only 4 bits<br>-<br>- // Read the MBAR address for setting up the IOAPIC in memory space<br>- // NOTE: this address was assigned during enumeration of the bus<br>-<br>- memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);<br>- pIndexRegister = (volatile uint32_t*) memoryBase;<br>- pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);<br>-<br>- printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n",<br>- apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),<br>- PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);<br>-<br>- apic_id <<= 24; // Convert ID to bitmask<br>-<br>- *pIndexRegister = 0; // Select APIC ID register<br>- *pWindowRegister = (*pWindowRegister & ~(0x0f << 24)) | apic_id; // Set the ID<br>-<br>- if ((*pWindowRegister & (0x0f << 24)) != apic_id)<br>- die("p64h2_ioapic_init failed");<br>-<br>- *pIndexRegister = 3; // Select Boot Configuration register<br>- *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts<br>-<br>- if (!(*pWindowRegister & 1))<br>- die("p64h2_ioapic_init failed");<br>-}<br>-<br>-static struct device_operations ioapic_ops = {<br>- .read_resources = pci_dev_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_dev_enable_resources,<br>- .init = p64h2_ioapic_init,<br>- .scan_bus = 0,<br>- .enable = p64h2_ioapic_enable,<br>-};<br>-<br>-static const struct pci_driver ioapic_driver __pci_driver = {<br>- .ops = &ioapic_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82870_1E0,<br>-<br>-};<br>diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c<br>deleted file mode 100644<br>index b886c52..0000000<br>--- a/src/southbridge/intel/i82870/pci_parity.c<br>+++ /dev/null<br>@@ -1,23 +0,0 @@<br>-#include <pci.h><br>-#include <arch/io.h><br>-#include <printk.h><br>-#<br>-<br>-void p64h2_pci_parity_enable(void)<br>-{<br>- uint8_t reg;<br>-<br>- /* 2SERREN - SERR enable for PCI bridge secondary device */<br>- /* 2PEREN - Parity error for PCI bridge secondary device */<br>- pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®);<br>- reg |= ((1 << 1) + (1 << 0));<br>- pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);<br>-<br>- /* 2SERREN - SERR enable for PCI bridge secondary device */<br>- /* 2PEREN - Parity error for PCI bridge secondary device */<br>- pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®);<br>- reg |= ((1 << 1) + (1 << 0));<br>- pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);<br>-<br>- return;<br>-}<br>diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c<br>deleted file mode 100644<br>index e8d890a..0000000<br>--- a/src/southbridge/intel/i82870/pcibridge.c<br>+++ /dev/null<br>@@ -1,38 +0,0 @@<br>-#include <console/console.h><br>-#include <device/device.h><br>-#include <device/pci.h><br>-#include <device/pci_ids.h><br>-#include <device/pci_ops.h><br>-#include <pc80/mc146818rtc.h><br>-#include "82870.h"<br>-<br>-static void p64h2_pcix_init(device_t dev)<br>-{<br>- u32 dword;<br>- u8 byte;<br>-<br>- /* The purpose of changes to HCCR, ACNF, and MTT is to speed<br>- * up the PCI bus for cards having high speed transfers.<br>- */<br>- dword = 0xc2040002;<br>- pci_write_config32(dev, HCCR, dword);<br>- dword = 0x0000c3bf;<br>- pci_write_config32(dev, ACNF, dword);<br>- byte = 0x08;<br>- pci_write_config8(dev, MTT, byte);<br>-<br>-}<br>-static struct device_operations pcix_ops = {<br>- .read_resources = pci_bus_read_resources,<br>- .set_resources = pci_dev_set_resources,<br>- .enable_resources = pci_bus_enable_resources,<br>- .init = p64h2_pcix_init,<br>- .scan_bus = pci_scan_bridge,<br>- .reset_bus = pci_bus_reset,<br>-};<br>-<br>-static const struct pci_driver pcix_driver __pci_driver = {<br>- .ops = &pcix_ops,<br>- .vendor = PCI_VENDOR_ID_INTEL,<br>- .device = PCI_DEVICE_ID_INTEL_82870_1F0,<br>-};<br></pre><p>To view, visit <a href="https://review.coreboot.org/22028">change 22028</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib6c8b3942b66bf43f7e1a42edf24cad32120c61d </div>
<div style="display:none"> Gerrit-Change-Number: 22028 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>