[coreboot-gerrit] Change in coreboot[master]: intel/cannonlake_rvp: Modify memory parameters for U-LP4 board
Lijian Zhao (Code Review)
gerrit at coreboot.org
Fri Oct 13 06:06:51 CEST 2017
Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22001
Change subject: intel/cannonlake_rvp: Modify memory parameters for U-LP4 board
......................................................................
intel/cannonlake_rvp: Modify memory parameters for U-LP4 board
Drop the support for Cannonlake U DDR4 board, instead of that will
support Cannonlake U LPDDR4 platform.
TEST=Able to boot up on CNL U-LP4 RVP.
Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/mainboard/intel/cannonlake_rvp/romstage.c
M src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
2 files changed, 10 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/22001/1
diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c
index 03c5807..e0699da 100644
--- a/src/mainboard/intel/cannonlake_rvp/romstage.c
+++ b/src/mainboard/intel/cannonlake_rvp/romstage.c
@@ -36,18 +36,10 @@
mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) {
- mem_cfg->DqPinsInterleaved = 1;
- mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA VREF_DQ_B->CHB */
- spd_index = 1;
- } else { /* For CONFIG_BOARD_INTEL_CANNONLAKE_RVPY */
- mem_cfg->DqPinsInterleaved = 0;
- mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
- mem_cfg->ECT = 1; /* Early Command Training Enabled */
- spd_index = 2;
- }
-
- printk(BIOS_DEBUG,"SPD INDEX =0x%u\n", spd_index);
+ mem_cfg->DqPinsInterleaved = 0;
+ mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */
+ mem_cfg->ECT = 1; /* Early Command Training Enabled */
+ spd_index = 2;
struct region_device spd_rdev;
diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
index 1e95280..4e2f31f 100644
--- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
+++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c
@@ -31,25 +31,17 @@
void mainboard_fill_dq_map_ch1(void *dq_map_ptr)
{
- /* DQ byte map Ch1 */
- const u8 dq_map_u[12] = {
- 0x33, 0xCC, 0x33, 0xCC, 0xFF, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
-
- const u8 dq_map_y[12] = {
+ const u8 dq_map[12] = {
0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
- memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u));
- else
- memcpy(dq_map_ptr, dq_map_y, sizeof(dq_map_y));
+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
}
void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr)
{
/* DQS CPU<>DRAM map Ch0 */
- const u8 dqs_map_u[8] = { 0, 1, 3, 2, 4, 5, 6, 7 };
+ const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };
const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 };
@@ -62,7 +54,7 @@
void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr)
{
/* DQS CPU<>DRAM map Ch1 */
- const u8 dqs_map_u[8] = { 1, 0, 4, 5, 2, 3, 6, 7 };
+ const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };
const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 };
@@ -82,16 +74,8 @@
void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
{
/* Rcomp target */
- static const u16 RcompTarget_U[RCOMP_TARGET_PARAMS] = {
- 100, 33, 32, 33, 28 };
-
- static const u16 RcompTarget_Y[RCOMP_TARGET_PARAMS] = {
+ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
80, 40, 40, 40, 30 };
- if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU))
- memcpy(rcomp_strength_ptr, RcompTarget_U,
- sizeof(RcompTarget_U));
- else
- memcpy(rcomp_strength_ptr, RcompTarget_Y,
- sizeof(RcompTarget_Y));
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148
Gerrit-Change-Number: 22001
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: John Zhao <john.zhao at intel.com>
Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula at intel.com>
Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi at intel.com>
Gerrit-Reviewer: Shaunak Saha <shaunak.saha at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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